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HeungJun, Kim89f95492012-01-16 21:13:05 +00001/*
2 * Copyright (C) 2011 Samsung Electronics
3 * Heungjun Kim <riverful.kim@samsung.com>
4 *
5 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_SAMSUNG /* in a SAMSUNG core */
34#define CONFIG_S5P /* which is in a S5P Family */
35#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
36#define CONFIG_TRATS /* working with TRATS */
Donghwa Lee90464972012-05-09 19:23:46 +000037#define CONFIG_TIZEN /* TIZEN lib */
HeungJun, Kim89f95492012-01-16 21:13:05 +000038
39#include <asm/arch/cpu.h> /* get chip and board defs */
40
41#define CONFIG_ARCH_CPU_INIT
42#define CONFIG_DISPLAY_CPUINFO
43#define CONFIG_DISPLAY_BOARDINFO
44
Łukasz Majewskid0460b02012-08-07 05:42:14 +000045#ifndef CONFIG_SYS_L2CACHE_OFF
46#define CONFIG_SYS_L2_PL310
47#define CONFIG_SYS_PL310_BASE 0x10502000
48#endif
HeungJun, Kim89f95492012-01-16 21:13:05 +000049
50#define CONFIG_SYS_SDRAM_BASE 0x40000000
51#define CONFIG_SYS_TEXT_BASE 0x63300000
52
53/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
54#define CONFIG_SYS_CLK_FREQ_C210 24000000
Chander Kashyap5e46f832012-02-05 23:01:45 +000055#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
HeungJun, Kim89f95492012-01-16 21:13:05 +000056
57#define CONFIG_SETUP_MEMORY_TAGS
58#define CONFIG_CMDLINE_TAG
HeungJun, Kim89f95492012-01-16 21:13:05 +000059#define CONFIG_REVISION_TAG
60#define CONFIG_CMDLINE_EDITING
61#define CONFIG_SKIP_LOWLEVEL_INIT
62#define CONFIG_BOARD_EARLY_INIT_F
63
64/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
65#define MACH_TYPE_TRATS 3928
66#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
67
68/* Size of malloc() pool */
69#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
70
71/* select serial console configuration */
HeungJun, Kim89f95492012-01-16 21:13:05 +000072#define CONFIG_SERIAL2 /* use SERIAL 2 */
73#define CONFIG_BAUDRATE 115200
74
75/* MMC */
76#define CONFIG_GENERIC_MMC
77#define CONFIG_MMC
Jaehoon Chung7d2d58b2012-04-23 02:36:29 +000078#define CONFIG_S5P_SDHCI
79#define CONFIG_SDHCI
Jaehoon Chungb09ed6e2012-08-30 16:24:11 +000080#define CONFIG_MMC_SDMA
HeungJun, Kim89f95492012-01-16 21:13:05 +000081
82/* PWM */
83#define CONFIG_PWM
84
85/* It should define before config_cmd_default.h */
86#define CONFIG_SYS_NO_FLASH
87
88/* Command definition */
89#include <config_cmd_default.h>
90
91#undef CONFIG_CMD_FPGA
92#undef CONFIG_CMD_MISC
93#undef CONFIG_CMD_NET
94#undef CONFIG_CMD_NFS
95#undef CONFIG_CMD_XIMG
96#undef CONFIG_CMD_CACHE
97#undef CONFIG_CMD_ONENAND
98#undef CONFIG_CMD_MTDPARTS
99#define CONFIG_CMD_MMC
Lukasz Majewski93a1ab52012-08-06 14:41:11 +0200100#define CONFIG_CMD_DFU
Lukasz Majewski9960d9a2012-12-11 11:09:48 +0100101#define CONFIG_CMD_GPT
Łukasz Majewski35777e22013-01-02 06:06:02 +0000102#define CONFIG_CMD_SETEXPR
Lukasz Majewski93a1ab52012-08-06 14:41:11 +0200103
104/* FAT */
105#define CONFIG_CMD_FAT
106#define CONFIG_FAT_WRITE
107
108/* USB Composite download gadget - g_dnl */
109#define CONFIG_USBDOWNLOAD_GADGET
110#define CONFIG_DFU_FUNCTION
111#define CONFIG_DFU_MMC
112
113/* USB Samsung's IDs */
114#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
115#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
116#define CONFIG_G_DNL_MANUFACTURER "Samsung"
HeungJun, Kim89f95492012-01-16 21:13:05 +0000117
118#define CONFIG_BOOTDELAY 1
119#define CONFIG_ZERO_BOOTDELAY_CHECK
120#define CONFIG_BOOTARGS "Please use defined boot"
121#define CONFIG_BOOTCOMMAND "run mmcboot"
122
123#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
124#define CONFIG_BOOTBLOCK "10"
125#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
126
Lukasz Majewski9960d9a2012-12-11 11:09:48 +0100127/* Tizen - partitions definitions */
128#define PARTS_CSA "csa-mmc"
129#define PARTS_BOOTLOADER "u-boot"
130#define PARTS_BOOT "boot"
131#define PARTS_ROOT "platform"
132#define PARTS_DATA "data"
133#define PARTS_CSC "csc"
134#define PARTS_UMS "ums"
135
136#define PARTS_DEFAULT \
137 "uuid_disk=${uuid_gpt_disk};" \
138 "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
139 "name="PARTS_BOOTLOADER",size=60MiB," \
140 "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
141 "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
142 "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
143 "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
144 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
145 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
146
Lukasz Majewski93a1ab52012-08-06 14:41:11 +0200147#define CONFIG_DFU_ALT \
Lukasz Majewski93a1ab52012-08-06 14:41:11 +0200148 "u-boot mmc 80 400;" \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000149 "uImage ext4 0 2\0" \
Lukasz Majewski93a1ab52012-08-06 14:41:11 +0200150
HeungJun, Kim89f95492012-01-16 21:13:05 +0000151#define CONFIG_ENV_OVERWRITE
152#define CONFIG_SYS_CONSOLE_INFO_QUIET
153#define CONFIG_SYS_CONSOLE_IS_IN_ENV
154
155#define CONFIG_EXTRA_ENV_SETTINGS \
156 "bootk=" \
157 "run loaduimage; bootm 0x40007FC0\0" \
158 "updatemmc=" \
159 "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
160 "mmc boot 0 1 1 0\0" \
161 "updatebackup=" \
162 "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
163 "mmc boot 0 1 1 0\0" \
164 "updatebootb=" \
165 "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
166 "lpj=lpj=3981312\0" \
167 "nfsboot=" \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000168 "setenv bootargs root=/dev/nfs rw " \
HeungJun, Kim89f95492012-01-16 21:13:05 +0000169 "nfsroot=${nfsroot},nolock,tcp " \
170 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
171 "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
172 "; run bootk\0" \
173 "ramfsboot=" \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000174 "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
HeungJun, Kim89f95492012-01-16 21:13:05 +0000175 "${console} ${meminfo} " \
176 "initrd=0x43000000,8M ramdisk=8192\0" \
177 "mmcboot=" \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000178 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
HeungJun, Kim89f95492012-01-16 21:13:05 +0000179 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
180 "run loaduimage; bootm 0x40007FC0\0" \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000181 "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
HeungJun, Kim89f95492012-01-16 21:13:05 +0000182 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
183 "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
184 "verify=n\0" \
185 "rootfstype=ext4\0" \
186 "console=" CONFIG_DEFAULT_CONSOLE \
187 "meminfo=crashkernel=32M@0x50000000\0" \
188 "nfsroot=/nfsroot/arm\0" \
189 "bootblock=" CONFIG_BOOTBLOCK "\0" \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000190 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
HeungJun, Kim89f95492012-01-16 21:13:05 +0000191 "mmcdev=0\0" \
192 "mmcbootpart=2\0" \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000193 "mmcrootpart=5\0" \
Lukasz Majewski93a1ab52012-08-06 14:41:11 +0200194 "opts=always_resume=1\0" \
Lukasz Majewski9960d9a2012-12-11 11:09:48 +0100195 "partitions=" PARTS_DEFAULT \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000196 "dfu_alt_info=" CONFIG_DFU_ALT \
197 "spladdr=0x40000100\0" \
198 "splsize=0x200\0" \
199 "splfile=falcon.bin\0" \
200 "spl_export=" \
201 "setexpr spl_imgsize ${splsize} + 8 ;" \
Przemyslaw Marczakdc993a62013-03-12 03:41:49 +0000202 "setenv spl_imgsize 0x${spl_imgsize};" \
Łukasz Majewski35777e22013-01-02 06:06:02 +0000203 "setexpr spl_imgaddr ${spladdr} - 8 ;" \
204 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
205 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
206 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
207 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
208 "spl export atags 0x40007FC0;" \
209 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
210 "mw.l ${spl_addr_tmp} ${splsize};" \
211 "ext4write mmc ${mmcdev}:${mmcbootpart}" \
212 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
213 "setenv spl_imgsize;" \
214 "setenv spl_imgaddr;" \
215 "setenv spl_addr_tmp;\0"
HeungJun, Kim89f95492012-01-16 21:13:05 +0000216
217/* Miscellaneous configurable options */
218#define CONFIG_SYS_LONGHELP /* undef to save memory */
219#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
HeungJun, Kim89f95492012-01-16 21:13:05 +0000220#define CONFIG_SYS_PROMPT "TRATS # "
221#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
222#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
223#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
224/* Boot Argument Buffer Size */
225#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
226/* memtest works on */
227#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
228#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
229#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
230
231#define CONFIG_SYS_HZ 1000
232
Piotr Wilczekb5598572012-09-20 00:19:55 +0000233/* TRATS has 4 banks of DRAM */
234#define CONFIG_NR_DRAM_BANKS 4
235#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
236#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
237#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
238#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
239#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
240#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
241#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
242#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
243#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
HeungJun, Kim89f95492012-01-16 21:13:05 +0000244
245#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
246
247#define CONFIG_SYS_MONITOR_BASE 0x00000000
248#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
249
250#define CONFIG_ENV_IS_IN_MMC
251#define CONFIG_SYS_MMC_ENV_DEV 0
252#define CONFIG_ENV_SIZE 4096
253#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
254
255#define CONFIG_DOS_PARTITION
Łukasz Majewski35777e22013-01-02 06:06:02 +0000256#define CONFIG_EFI_PARTITION
257
258/* EXT4 */
259#define CONFIG_CMD_EXT4
260#define CONFIG_CMD_EXT4_WRITE
261/* Falcon mode definitions */
262#define CONFIG_CMD_SPL
263#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100
HeungJun, Kim89f95492012-01-16 21:13:05 +0000264
Lukasz Majewski9960d9a2012-12-11 11:09:48 +0100265/* GPT */
266#define CONFIG_EFI_PARTITION
267#define CONFIG_PARTITION_UUIDS
268
HeungJun, Kim89f95492012-01-16 21:13:05 +0000269#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
270#define CONFIG_SYS_CACHELINE_SIZE 32
271
HeungJun, Kim89f95492012-01-16 21:13:05 +0000272#define CONFIG_SOFT_I2C
273#define CONFIG_SOFT_I2C_READ_REPEATED_START
Łukasz Majewskifd8dca82012-09-04 23:15:21 +0000274#define CONFIG_SYS_I2C_INIT_BOARD
HeungJun, Kim89f95492012-01-16 21:13:05 +0000275#define CONFIG_SYS_I2C_SPEED 50000
276#define CONFIG_I2C_MULTI_BUS
Łukasz Majewskifd8dca82012-09-04 23:15:21 +0000277#define CONFIG_SOFT_I2C_MULTI_BUS
278#define CONFIG_SYS_MAX_I2C_BUS 15
279
280#include <asm/arch/gpio.h>
281
282/* I2C PMIC */
283#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
284#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
285
286/* I2C FG */
287#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
288#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
289
290#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
291#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
292#define I2C_INIT multi_i2c_init()
HeungJun, Kim89f95492012-01-16 21:13:05 +0000293
Łukasz Majewskibe3b51a2012-11-13 03:22:14 +0000294#define CONFIG_POWER
295#define CONFIG_POWER_I2C
296#define CONFIG_POWER_MAX8997
HeungJun, Kim89f95492012-01-16 21:13:05 +0000297
Łukasz Majewski5a773582012-11-13 03:22:07 +0000298#define CONFIG_POWER_FG
299#define CONFIG_POWER_FG_MAX17042
Łukasz Majewski7dcda992012-11-13 03:22:06 +0000300#define CONFIG_POWER_MUIC
301#define CONFIG_POWER_MUIC_MAX8997
Łukasz Majewski61365ff2012-11-13 03:22:08 +0000302#define CONFIG_POWER_BATTERY
303#define CONFIG_POWER_BATTERY_TRATS
HeungJun, Kim89f95492012-01-16 21:13:05 +0000304#define CONFIG_USB_GADGET
305#define CONFIG_USB_GADGET_S3C_UDC_OTG
306#define CONFIG_USB_GADGET_DUALSPEED
Lukasz Majewski93a1ab52012-08-06 14:41:11 +0200307#define CONFIG_USB_GADGET_VBUS_DRAW 2
HeungJun, Kim89f95492012-01-16 21:13:05 +0000308
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000309/* LCD */
310#define CONFIG_EXYNOS_FB
311#define CONFIG_LCD
Donghwa Lee90464972012-05-09 19:23:46 +0000312#define CONFIG_CMD_BMP
313#define CONFIG_BMP_32BPP
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000314#define CONFIG_FB_ADDR 0x52504000
315#define CONFIG_S6E8AX0
316#define CONFIG_EXYNOS_MIPI_DSIM
Donghwa Lee90464972012-05-09 19:23:46 +0000317#define CONFIG_VIDEO_BMP_GZIP
318#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
Donghwa Lee51b1cd62012-04-05 19:36:27 +0000319
Lukasz Majewski83301b42013-03-05 12:10:18 +0100320#define CONFIG_CMD_USB_MASS_STORAGE
321#if defined(CONFIG_CMD_USB_MASS_STORAGE)
322#define CONFIG_USB_GADGET_MASS_STORAGE
323#endif
324
HeungJun, Kim89f95492012-01-16 21:13:05 +0000325#endif /* __CONFIG_H */