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wdenk10767cc2004-05-13 13:23:58 +00001/*
wdenk1d6f9722004-09-09 17:44:35 +00002 * ueberarbeitet durch Christoph Seyfert
3 *
wdenk414eec32005-04-02 22:37:54 +00004 * (C) Copyright 2004-2005 DENX Software Engineering,
wdenk10767cc2004-05-13 13:23:58 +00005 * Wolfgang Grandegger <wg@denx.de>
6 * (C) Copyright 2003
7 * DAVE Srl
8 *
9 * http://www.dave-tech.it
10 * http://www.wawnet.biz
11 * mailto:info@wawnet.biz
12 *
13 * Credits: Stefan Roese, Wolfgang Denk
14 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020015 * SPDX-License-Identifier: GPL-2.0+
wdenk10767cc2004-05-13 13:23:58 +000016 */
17
18/*
19 * board/config.h - configuration options, board specific
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
26#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
27#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
28#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
29#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
30#endif
31
wdenk1d6f9722004-09-09 17:44:35 +000032/* Only one of the following two symbols must be defined (default is 25 MHz)
33 * CONFIG_PPCHAMELEON_CLK_25
34 * CONFIG_PPCHAMELEON_CLK_33
35 */
36#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
37#define CONFIG_PPCHAMELEON_CLK_25
38#endif
39
40#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
41#error "* Two external frequencies (SysClk) are defined! *"
42#endif
43
44#undef CONFIG_PPCHAMELEON_SMI712
45
wdenk10767cc2004-05-13 13:23:58 +000046/*
47 * Debug stuff
48 */
49#undef __DEBUG_START_FROM_SRAM__
50#define __DISABLE_MACHINE_EXCEPTION__
51
52#ifdef __DEBUG_START_FROM_SRAM__
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
wdenk10767cc2004-05-13 13:23:58 +000054#endif
55
56/*
57 * High Level Configuration Options
58 * (easy to change)
59 */
60
61#define CONFIG_405EP 1 /* This is a PPC405 CPU */
62#define CONFIG_4xx 1 /* ...member of PPC4xx family */
63#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
64
Wolfgang Denk2ae18242010-10-06 09:05:45 +020065#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 /* Reserve 320 kB for Monitor */
Wolfgang Denkaa72d8b2010-11-21 17:04:17 +010066#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020067
wdenk10767cc2004-05-13 13:23:58 +000068#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
69#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
70
wdenk1d6f9722004-09-09 17:44:35 +000071#ifdef CONFIG_PPCHAMELEON_CLK_25
72# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
73#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
wdenk10767cc2004-05-13 13:23:58 +000074#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk1d6f9722004-09-09 17:44:35 +000075#else
76# error "* External frequency (SysClk) not defined! *"
77#endif
wdenk10767cc2004-05-13 13:23:58 +000078
Stefan Roese550650d2010-09-20 16:05:31 +020079#define CONFIG_CONS_INDEX 2 /* Use UART1 */
80#define CONFIG_SYS_NS16550
81#define CONFIG_SYS_NS16550_SERIAL
82#define CONFIG_SYS_NS16550_REG_SIZE 1
83#define CONFIG_SYS_NS16550_CLK get_serial_clock()
wdenk10767cc2004-05-13 13:23:58 +000084#define CONFIG_BAUDRATE 115200
85#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
86
wdenk1d6f9722004-09-09 17:44:35 +000087#define CONFIG_VERSION_VARIABLE 1 /* add version variable */
88#define CONFIG_IDENT_STRING "1"
89
wdenk10767cc2004-05-13 13:23:58 +000090#undef CONFIG_BOOTARGS
91
92/* Ethernet stuff */
93#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
wdenk1d6f9722004-09-09 17:44:35 +000094#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
wdenke2ffd592004-12-31 09:32:47 +000095#define CONFIG_HAS_ETH1
wdenk1d6f9722004-09-09 17:44:35 +000096#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
wdenk10767cc2004-05-13 13:23:58 +000097
98#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk10767cc2004-05-13 13:23:58 +0000100
101
Stefan Roese6aa91952010-09-10 16:29:37 +0200102#define CONFIG_PPC4xx_EMAC
wdenk10767cc2004-05-13 13:23:58 +0000103#undef CONFIG_EXT_PHY
104
105#define CONFIG_MII 1 /* MII PHY management */
106#ifndef CONFIG_EXT_PHY
stroesebf418862005-06-30 13:06:07 +0000107#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
stroese3c71f3e2005-07-01 15:53:57 +0000108#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
wdenk10767cc2004-05-13 13:23:58 +0000109#else
110#define CONFIG_PHY_ADDR 2 /* PHY address */
111#endif
112#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
113
wdenk414eec32005-04-02 22:37:54 +0000114#define CONFIG_TIMESTAMP /* Print image info with timestamp */
115
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500116
117/*
Jon Loeliger11799432007-07-10 09:02:57 -0500118 * BOOTP options
119 */
120#define CONFIG_BOOTP_BOOTFILESIZE
121#define CONFIG_BOOTP_BOOTPATH
122#define CONFIG_BOOTP_GATEWAY
123#define CONFIG_BOOTP_HOSTNAME
124
125
126/*
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500127 * Command line configuration.
128 */
129#include <config_cmd_default.h>
130
131#define CONFIG_CMD_DHCP
132#define CONFIG_CMD_ELF
133#define CONFIG_CMD_EEPROM
134#define CONFIG_CMD_I2C
135#define CONFIG_CMD_IRQ
136#define CONFIG_CMD_JFFS2
137#define CONFIG_CMD_MII
138#define CONFIG_CMD_NAND
139#define CONFIG_CMD_NFS
140#define CONFIG_CMD_SNTP
141
wdenk10767cc2004-05-13 13:23:58 +0000142
143#define CONFIG_MAC_PARTITION
144#define CONFIG_DOS_PARTITION
145
wdenk10767cc2004-05-13 13:23:58 +0000146#undef CONFIG_WATCHDOG /* watchdog disabled */
147
148#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
wdenk10767cc2004-05-13 13:23:58 +0000150
151#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
152
153/*
154 * Miscellaneous configurable options
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk10767cc2004-05-13 13:23:58 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
wdenk10767cc2004-05-13 13:23:58 +0000159
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500160#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk10767cc2004-05-13 13:23:58 +0000162#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk10767cc2004-05-13 13:23:58 +0000164#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
166#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
167#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk10767cc2004-05-13 13:23:58 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenk10767cc2004-05-13 13:23:58 +0000170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenk10767cc2004-05-13 13:23:58 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
174#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk10767cc2004-05-13 13:23:58 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_BASE_BAUD 691200
wdenk10767cc2004-05-13 13:23:58 +0000178
179/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk10767cc2004-05-13 13:23:58 +0000181 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
182 57600, 115200, 230400, 460800, 921600 }
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
185#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk10767cc2004-05-13 13:23:58 +0000186
wdenk10767cc2004-05-13 13:23:58 +0000187#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
188
189/*-----------------------------------------------------------------------
190 * NAND-FLASH stuff
191 *-----------------------------------------------------------------------
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_NAND0_BASE 0xFF400000
194#define CONFIG_SYS_NAND1_BASE 0xFF000000
195#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
Marian Balakowicz6db39702006-04-08 19:08:06 +0200196#define NAND_BIG_DELAY_US 25
wdenk10767cc2004-05-13 13:23:58 +0000197
198/* For CATcenter there is only NAND on the module */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
wdenk10767cc2004-05-13 13:23:58 +0000200#define NAND_NO_RB
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
203#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
204#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
205#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
wdenk10767cc2004-05-13 13:23:58 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
208#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
209#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
210#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
wdenk10767cc2004-05-13 13:23:58 +0000211
212
Marian Balakowicz6db39702006-04-08 19:08:06 +0200213#define MACRO_NAND_DISABLE_CE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000214{ \
Marian Balakowicz6db39702006-04-08 19:08:06 +0200215 switch((unsigned long)nandptr) \
wdenk10767cc2004-05-13 13:23:58 +0000216 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217 case CONFIG_SYS_NAND0_BASE: \
218 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
wdenk10767cc2004-05-13 13:23:58 +0000219 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220 case CONFIG_SYS_NAND1_BASE: \
221 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
wdenk10767cc2004-05-13 13:23:58 +0000222 break; \
223 } \
224} while(0)
225
Marian Balakowicz6db39702006-04-08 19:08:06 +0200226#define MACRO_NAND_ENABLE_CE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000227{ \
Marian Balakowicz6db39702006-04-08 19:08:06 +0200228 switch((unsigned long)nandptr) \
wdenk10767cc2004-05-13 13:23:58 +0000229 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230 case CONFIG_SYS_NAND0_BASE: \
231 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
wdenk10767cc2004-05-13 13:23:58 +0000232 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 case CONFIG_SYS_NAND1_BASE: \
234 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
wdenk10767cc2004-05-13 13:23:58 +0000235 break; \
236 } \
237} while(0)
238
Marian Balakowicz6db39702006-04-08 19:08:06 +0200239#define MACRO_NAND_CTL_CLRALE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000240{ \
241 switch((unsigned long)nandptr) \
242 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243 case CONFIG_SYS_NAND0_BASE: \
244 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
wdenk10767cc2004-05-13 13:23:58 +0000245 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 case CONFIG_SYS_NAND1_BASE: \
247 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
wdenk10767cc2004-05-13 13:23:58 +0000248 break; \
249 } \
250} while(0)
251
Marian Balakowicz6db39702006-04-08 19:08:06 +0200252#define MACRO_NAND_CTL_SETALE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000253{ \
254 switch((unsigned long)nandptr) \
255 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256 case CONFIG_SYS_NAND0_BASE: \
257 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
wdenk10767cc2004-05-13 13:23:58 +0000258 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259 case CONFIG_SYS_NAND1_BASE: \
260 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
wdenk10767cc2004-05-13 13:23:58 +0000261 break; \
262 } \
263} while(0)
264
Marian Balakowicz6db39702006-04-08 19:08:06 +0200265#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000266{ \
267 switch((unsigned long)nandptr) \
268 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269 case CONFIG_SYS_NAND0_BASE: \
270 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
wdenk10767cc2004-05-13 13:23:58 +0000271 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 case CONFIG_SYS_NAND1_BASE: \
273 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
wdenk10767cc2004-05-13 13:23:58 +0000274 break; \
275 } \
276} while(0)
277
Marian Balakowicz6db39702006-04-08 19:08:06 +0200278#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
wdenk10767cc2004-05-13 13:23:58 +0000279 switch((unsigned long)nandptr) { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280 case CONFIG_SYS_NAND0_BASE: \
281 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
wdenk10767cc2004-05-13 13:23:58 +0000282 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283 case CONFIG_SYS_NAND1_BASE: \
284 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
wdenk10767cc2004-05-13 13:23:58 +0000285 break; \
286 } \
287} while(0)
288
289#ifdef NAND_NO_RB
290/* constant delay (see also tR in the datasheet) */
291#define NAND_WAIT_READY(nand) do { \
292 udelay(12); \
293} while (0)
294#else
295/* use the R/B pin */
296/* TBD */
297#endif
298
299#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
300#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
301#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
302#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
303
304/*-----------------------------------------------------------------------
305 * PCI stuff
306 *-----------------------------------------------------------------------
307 */
308#if 0 /* No PCI on CATcenter */
309#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
310#define PCI_HOST_FORCE 1 /* configure as pci host */
311#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
312
313#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000314#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenk10767cc2004-05-13 13:23:58 +0000315#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
316#undef CONFIG_PCI_PNP /* do pci plug-and-play */
317 /* resource configuration */
318
319#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
322#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
323#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
wdenk1d6f9722004-09-09 17:44:35 +0000324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
326#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
327#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
328#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
329#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
330#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk10767cc2004-05-13 13:23:58 +0000331#endif /* No PCI */
332
333/*-----------------------------------------------------------------------
334 * Start addresses for the final memory configuration
335 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk10767cc2004-05-13 13:23:58 +0000337 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_SDRAM_BASE 0x00000000
339#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
340#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
341#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
342#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
wdenk10767cc2004-05-13 13:23:58 +0000343
344/*
345 * For booting Linux, the board info and command line data
346 * have to be in the first 8 MB of memory, since this is
347 * the maximum mapped by the Linux kernel during initialization.
348 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk10767cc2004-05-13 13:23:58 +0000350/*-----------------------------------------------------------------------
351 * FLASH organization
352 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
354#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk10767cc2004-05-13 13:23:58 +0000355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
357#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
wdenk10767cc2004-05-13 13:23:58 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
360#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
361#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenk10767cc2004-05-13 13:23:58 +0000362/*
363 * The following defines are added for buggy IOP480 byte interface.
364 * All other boards should use the standard values (CPCI405 etc.)
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
367#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
368#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenk10767cc2004-05-13 13:23:58 +0000369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk10767cc2004-05-13 13:23:58 +0000371
wdenk10767cc2004-05-13 13:23:58 +0000372/*-----------------------------------------------------------------------
373 * Environment Variable setup
374 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200375#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200376#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
377#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
378#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
379#define CONFIG_ENV_SIZE_REDUND 0x2000
wdenk10767cc2004-05-13 13:23:58 +0000380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
384#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
wdenk10767cc2004-05-13 13:23:58 +0000385
386/*-----------------------------------------------------------------------
387 * I2C EEPROM (CAT24WC16) for environment
388 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000389#define CONFIG_SYS_I2C
390#define CONFIG_SYS_I2C_PPC4XX
391#define CONFIG_SYS_I2C_PPC4XX_CH0
392#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
393#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenk10767cc2004-05-13 13:23:58 +0000394
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
396#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenk10767cc2004-05-13 13:23:58 +0000397/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
399#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenk10767cc2004-05-13 13:23:58 +0000400 /* 16 byte page write mode using*/
401 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk10767cc2004-05-13 13:23:58 +0000403
wdenk10767cc2004-05-13 13:23:58 +0000404/*
405 * Init Memory Controller:
406 *
407 * BR0/1 and OR0/1 (FLASH)
408 */
409
410#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
411
412/*-----------------------------------------------------------------------
413 * External Bus Controller (EBC) Setup
414 */
415
416/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_EBC_PB0AP 0x92015480
418#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenk10767cc2004-05-13 13:23:58 +0000419
420/* Memory Bank 1 (External SRAM) initialization */
421/* Since this must replace NOR Flash, we use the same settings for CS0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_EBC_PB1AP 0x92015480
423#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
wdenk10767cc2004-05-13 13:23:58 +0000424
425/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_EBC_PB2AP 0x92015480
427#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
wdenk10767cc2004-05-13 13:23:58 +0000428
429/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_EBC_PB3AP 0x92015480
431#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
wdenk10767cc2004-05-13 13:23:58 +0000432
wdenk1d6f9722004-09-09 17:44:35 +0000433#ifdef CONFIG_PPCHAMELEON_SMI712
434/*
435 * Video console (graphic: SMI LynxEM)
436 */
437#define CONFIG_VIDEO
438#define CONFIG_CFB_CONSOLE
439#define CONFIG_VIDEO_SMI_LYNXEM
440#define CONFIG_VIDEO_LOGO
441/*#define CONFIG_VIDEO_BMP_LOGO*/
442#define CONFIG_CONSOLE_EXTRA_INFO
443#define CONFIG_VGA_AS_SINGLE_DEVICE
444/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_ISA_IO 0xE8000000
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100446/* see also drivers/video/videomodes.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
wdenk10767cc2004-05-13 13:23:58 +0000448#endif
449
450/*-----------------------------------------------------------------------
451 * FPGA stuff
452 */
453/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_FPGA_MODE 0x00
455#define CONFIG_SYS_FPGA_STATUS 0x02
456#define CONFIG_SYS_FPGA_TS 0x04
457#define CONFIG_SYS_FPGA_TS_LOW 0x06
458#define CONFIG_SYS_FPGA_TS_CAP0 0x10
459#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
460#define CONFIG_SYS_FPGA_TS_CAP1 0x14
461#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
462#define CONFIG_SYS_FPGA_TS_CAP2 0x18
463#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
464#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
465#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenk10767cc2004-05-13 13:23:58 +0000466
467/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
469#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
470#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
471#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenk10767cc2004-05-13 13:23:58 +0000472
473/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
475#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
476#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
477#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
478#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenk10767cc2004-05-13 13:23:58 +0000479
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
481#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
wdenk10767cc2004-05-13 13:23:58 +0000482
483/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
485#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
486#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
487#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
488#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenk10767cc2004-05-13 13:23:58 +0000489
490/*-----------------------------------------------------------------------
491 * Definitions for initial stack pointer and data area (in data cache)
492 */
493/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenk10767cc2004-05-13 13:23:58 +0000495
496/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
498#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
499#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200500#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
wdenk10767cc2004-05-13 13:23:58 +0000501
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200502#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk10767cc2004-05-13 13:23:58 +0000504
505/*-----------------------------------------------------------------------
506 * Definitions for GPIO setup (PPC405EP specific)
507 *
508 * GPIO0[0] - External Bus Controller BLAST output
509 * GPIO0[1-9] - Instruction trace outputs -> GPIO
510 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
511 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
512 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
513 * GPIO0[24-27] - UART0 control signal inputs/outputs
514 * GPIO0[28-29] - UART1 data signal input/output
515 * GPIO0[30] - EMAC0 input
516 * GPIO0[31] - EMAC1 reject packet as output
517 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200518#define CONFIG_SYS_GPIO0_OSRL 0x40000550
519#define CONFIG_SYS_GPIO0_OSRH 0x00000110
520#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
521/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
522#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200524#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200525#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
wdenk10767cc2004-05-13 13:23:58 +0000526
wdenk10767cc2004-05-13 13:23:58 +0000527#define CONFIG_NO_SERIAL_EEPROM
528
529/*--------------------------------------------------------------------*/
530
531#ifdef CONFIG_NO_SERIAL_EEPROM
532
533/*
534!-----------------------------------------------------------------------
535! Defines for entry options.
536! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
537! are plugged in the board will be utilized as non-ECC DIMMs.
538!-----------------------------------------------------------------------
539*/
540#undef AUTO_MEMORY_CONFIG
541#define DIMM_READ_ADDR 0xAB
542#define DIMM_WRITE_ADDR 0xAA
543
wdenk10767cc2004-05-13 13:23:58 +0000544/* Defines for CPC0_PLLMR1 Register fields */
545#define PLL_ACTIVE 0x80000000
546#define CPC0_PLLMR1_SSCS 0x80000000
547#define PLL_RESET 0x40000000
548#define CPC0_PLLMR1_PLLR 0x40000000
549 /* Feedback multiplier */
550#define PLL_FBKDIV 0x00F00000
551#define CPC0_PLLMR1_FBDV 0x00F00000
552#define PLL_FBKDIV_16 0x00000000
553#define PLL_FBKDIV_1 0x00100000
554#define PLL_FBKDIV_2 0x00200000
555#define PLL_FBKDIV_3 0x00300000
556#define PLL_FBKDIV_4 0x00400000
557#define PLL_FBKDIV_5 0x00500000
558#define PLL_FBKDIV_6 0x00600000
559#define PLL_FBKDIV_7 0x00700000
560#define PLL_FBKDIV_8 0x00800000
561#define PLL_FBKDIV_9 0x00900000
562#define PLL_FBKDIV_10 0x00A00000
563#define PLL_FBKDIV_11 0x00B00000
564#define PLL_FBKDIV_12 0x00C00000
565#define PLL_FBKDIV_13 0x00D00000
566#define PLL_FBKDIV_14 0x00E00000
567#define PLL_FBKDIV_15 0x00F00000
568 /* Forward A divisor */
569#define PLL_FWDDIVA 0x00070000
570#define CPC0_PLLMR1_FWDVA 0x00070000
571#define PLL_FWDDIVA_8 0x00000000
572#define PLL_FWDDIVA_7 0x00010000
573#define PLL_FWDDIVA_6 0x00020000
574#define PLL_FWDDIVA_5 0x00030000
575#define PLL_FWDDIVA_4 0x00040000
576#define PLL_FWDDIVA_3 0x00050000
577#define PLL_FWDDIVA_2 0x00060000
578#define PLL_FWDDIVA_1 0x00070000
579 /* Forward B divisor */
580#define PLL_FWDDIVB 0x00007000
581#define CPC0_PLLMR1_FWDVB 0x00007000
582#define PLL_FWDDIVB_8 0x00000000
583#define PLL_FWDDIVB_7 0x00001000
584#define PLL_FWDDIVB_6 0x00002000
585#define PLL_FWDDIVB_5 0x00003000
586#define PLL_FWDDIVB_4 0x00004000
587#define PLL_FWDDIVB_3 0x00005000
588#define PLL_FWDDIVB_2 0x00006000
589#define PLL_FWDDIVB_1 0x00007000
590 /* PLL tune bits */
591#define PLL_TUNE_MASK 0x000003FF
592#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
593#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
594#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
595#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
596#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
597#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
598#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
599
600/* Defines for CPC0_PLLMR0 Register fields */
601 /* CPU divisor */
602#define PLL_CPUDIV 0x00300000
603#define CPC0_PLLMR0_CCDV 0x00300000
604#define PLL_CPUDIV_1 0x00000000
605#define PLL_CPUDIV_2 0x00100000
606#define PLL_CPUDIV_3 0x00200000
607#define PLL_CPUDIV_4 0x00300000
608 /* PLB divisor */
609#define PLL_PLBDIV 0x00030000
610#define CPC0_PLLMR0_CBDV 0x00030000
611#define PLL_PLBDIV_1 0x00000000
612#define PLL_PLBDIV_2 0x00010000
613#define PLL_PLBDIV_3 0x00020000
614#define PLL_PLBDIV_4 0x00030000
615 /* OPB divisor */
616#define PLL_OPBDIV 0x00003000
617#define CPC0_PLLMR0_OPDV 0x00003000
618#define PLL_OPBDIV_1 0x00000000
619#define PLL_OPBDIV_2 0x00001000
620#define PLL_OPBDIV_3 0x00002000
621#define PLL_OPBDIV_4 0x00003000
622 /* EBC divisor */
623#define PLL_EXTBUSDIV 0x00000300
624#define CPC0_PLLMR0_EPDV 0x00000300
625#define PLL_EXTBUSDIV_2 0x00000000
626#define PLL_EXTBUSDIV_3 0x00000100
627#define PLL_EXTBUSDIV_4 0x00000200
628#define PLL_EXTBUSDIV_5 0x00000300
629 /* MAL divisor */
630#define PLL_MALDIV 0x00000030
631#define CPC0_PLLMR0_MPDV 0x00000030
632#define PLL_MALDIV_1 0x00000000
633#define PLL_MALDIV_2 0x00000010
634#define PLL_MALDIV_3 0x00000020
635#define PLL_MALDIV_4 0x00000030
636 /* PCI divisor */
637#define PLL_PCIDIV 0x00000003
638#define CPC0_PLLMR0_PPFD 0x00000003
639#define PLL_PCIDIV_1 0x00000000
640#define PLL_PCIDIV_2 0x00000001
641#define PLL_PCIDIV_3 0x00000002
642#define PLL_PCIDIV_4 0x00000003
643
wdenk1d6f9722004-09-09 17:44:35 +0000644#ifdef CONFIG_PPCHAMELEON_CLK_25
645/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
646#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
647 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
648 PLL_MALDIV_1 | PLL_PCIDIV_4)
649#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
650 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
651 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
652
653#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
654 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
655 PLL_MALDIV_1 | PLL_PCIDIV_4)
656#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
657 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
658 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
659
660#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
661 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
662 PLL_MALDIV_1 | PLL_PCIDIV_4)
663#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
664 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
665 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
666
667#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
668 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
669 PLL_MALDIV_1 | PLL_PCIDIV_2)
670#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
671 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
672 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
673
674#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
675
wdenk10767cc2004-05-13 13:23:58 +0000676/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
wdenk1d6f9722004-09-09 17:44:35 +0000677#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
678 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000679 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000680#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
681 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
wdenk10767cc2004-05-13 13:23:58 +0000682 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000683
684#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
685 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000686 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000687#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
688 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000689 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000690
691#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
692 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000693 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000694#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
695 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000696 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000697
698#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
699 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000700 PLL_MALDIV_1 | PLL_PCIDIV_2)
wdenk1d6f9722004-09-09 17:44:35 +0000701#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
702 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000703 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
704
wdenk1d6f9722004-09-09 17:44:35 +0000705#else
706#error "* External frequency (SysClk) not defined! *"
707#endif
708
wdenk10767cc2004-05-13 13:23:58 +0000709#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
710/* Model HI */
wdenk1d6f9722004-09-09 17:44:35 +0000711#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
712#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200713#define CONFIG_SYS_OPB_FREQ 55555555
wdenk10767cc2004-05-13 13:23:58 +0000714/* Model ME */
715#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
wdenk1d6f9722004-09-09 17:44:35 +0000716#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
717#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200718#define CONFIG_SYS_OPB_FREQ 66666666
wdenk10767cc2004-05-13 13:23:58 +0000719#else
720/* Model BA (default) */
wdenk1d6f9722004-09-09 17:44:35 +0000721#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
722#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200723#define CONFIG_SYS_OPB_FREQ 66666666
wdenk10767cc2004-05-13 13:23:58 +0000724#endif
725
726#endif /* CONFIG_NO_SERIAL_EEPROM */
727
728#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
wdenk10767cc2004-05-13 13:23:58 +0000729#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
730
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200731/*
732 * JFFS2 partitions
733 *
734 */
735/* No command line, one static partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100736#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200737#define CONFIG_JFFS2_DEV "nand"
738#define CONFIG_JFFS2_PART_SIZE 0x00200000
739#define CONFIG_JFFS2_PART_OFFSET 0x00000000
740
741/* mtdparts command line support
742 *
743 * Note: fake mtd_id used, no linux mtd map file
744 */
745/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100746#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200747#define MTDIDS_DEFAULT "nand0=catcenter"
748#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
749*/
750
wdenk10767cc2004-05-13 13:23:58 +0000751#endif /* __CONFIG_H */