blob: bdb8eb529d70064a366b83817e9ef1fa4e668a00 [file] [log] [blame]
Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
Paul Gortmaker2738bc82009-09-20 20:36:06 -04002 * Copyright 2007,2009 Wind River Systems <www.windriver.com>
Joe Hamman9e3ed392007-12-13 06:45:14 -06003 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Joe Hamman9e3ed392007-12-13 06:45:14 -06007 */
8
9/*
10 * sbc8548 board configuration file
Paul Gortmaker2738bc82009-09-20 20:36:06 -040011 * Please refer to doc/README.sbc8548 for more info.
Joe Hamman9e3ed392007-12-13 06:45:14 -060012 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Paul Gortmaker2738bc82009-09-20 20:36:06 -040016/*
17 * Top level Makefile configuration choices
18 */
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020019#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000020#define CONFIG_PCI_INDIRECT_BRIDGE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040021#define CONFIG_PCI1
22#endif
23
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020024#ifdef CONFIG_66
Paul Gortmaker2738bc82009-09-20 20:36:06 -040025#define CONFIG_SYS_CLK_DIV 1
26#endif
27
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020028#ifdef CONFIG_33
Paul Gortmaker2738bc82009-09-20 20:36:06 -040029#define CONFIG_SYS_CLK_DIV 2
30#endif
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_PCIE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040033#define CONFIG_PCIE1
34#endif
35
36/*
37 * High Level Configuration Options
38 */
Joe Hamman9e3ed392007-12-13 06:45:14 -060039#define CONFIG_BOOKE 1 /* BOOKE */
40#define CONFIG_E500 1 /* BOOKE e500 family */
41#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
42#define CONFIG_MPC8548 1 /* MPC8548 specific */
43#define CONFIG_SBC8548 1 /* SBC8548 board specific */
44
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050045/*
46 * If you want to boot from the SODIMM flash, instead of the soldered
47 * on flash, set this, and change JP12, SW2:8 accordingly.
48 */
49#undef CONFIG_SYS_ALT_BOOT
50
Wolfgang Denk2ae18242010-10-06 09:05:45 +020051#ifndef CONFIG_SYS_TEXT_BASE
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050052#ifdef CONFIG_SYS_ALT_BOOT
53#define CONFIG_SYS_TEXT_BASE 0xfff00000
54#else
Wolfgang Denk2ae18242010-10-06 09:05:45 +020055#define CONFIG_SYS_TEXT_BASE 0xfffa0000
56#endif
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050057#endif
Wolfgang Denk2ae18242010-10-06 09:05:45 +020058
Joe Hamman9e3ed392007-12-13 06:45:14 -060059#undef CONFIG_RIO
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040060
61#ifdef CONFIG_PCI
62#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
63#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
64#endif
65#ifdef CONFIG_PCIE1
66#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
67#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -060068
69#define CONFIG_TSEC_ENET /* tsec ethernet support */
70#define CONFIG_ENV_OVERWRITE
Joe Hamman9e3ed392007-12-13 06:45:14 -060071
Joe Hamman9e3ed392007-12-13 06:45:14 -060072#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
73
Kumar Galae2b159d2008-01-16 09:05:27 -060074#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060075
Paul Gortmaker2738bc82009-09-20 20:36:06 -040076/*
77 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
78 */
79#ifndef CONFIG_SYS_CLK_DIV
80#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
81#endif
82#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -060083
84/*
85 * These can be toggled for performance analysis, otherwise use default.
86 */
87#define CONFIG_L2_CACHE /* toggle L2 cache */
88#define CONFIG_BTB /* toggle branch predition */
Joe Hamman9e3ed392007-12-13 06:45:14 -060089
90/*
91 * Only possible on E500 Version 2 or newer cores.
92 */
93#define CONFIG_ENABLE_36BIT_PHYS 1
94
95#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
98#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
99#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600100
Timur Tabie46fedf2011-08-04 18:03:41 -0500101#define CONFIG_SYS_CCSRBAR 0xe0000000
102#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Joe Hamman9e3ed392007-12-13 06:45:14 -0600103
Kumar Gala33b90792008-08-26 23:15:28 -0500104/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700105#define CONFIG_SYS_FSL_DDR2
Kumar Gala33b90792008-08-26 23:15:28 -0500106#undef CONFIG_FSL_DDR_INTERACTIVE
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500107#undef CONFIG_DDR_ECC /* only for ECC DDR module */
108/*
109 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
110 * to collide, meaning you couldn't reliably read either. So
111 * physically remove the LBC PC100 SDRAM module from the board
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500112 * before enabling the two SPD options below, or check that you
113 * have the hardware fix on your board via "i2c probe" and looking
114 * for a device at 0x53.
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500115 */
Kumar Gala33b90792008-08-26 23:15:28 -0500116#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
117#undef CONFIG_DDR_SPD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600118
Kumar Gala33b90792008-08-26 23:15:28 -0500119#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
120#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
123#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala33b90792008-08-26 23:15:28 -0500124#define CONFIG_VERY_BIG_RAM
125
126#define CONFIG_NUM_DDR_CONTROLLERS 1
127#define CONFIG_DIMM_SLOTS_PER_CTLR 1
128#define CONFIG_CHIP_SELECTS_PER_CTRL 2
129
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500130/*
131 * The hardware fix for the I2C address collision puts the DDR
132 * SPD at 0x53, but if we are running on an older board w/o the
133 * fix, it will still be at 0x51. We check 0x53 1st.
134 */
Kumar Gala33b90792008-08-26 23:15:28 -0500135#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500136#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600137
138/*
139 * Make sure required options are set
140 */
141#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Paul Gortmaker2a6b3b72011-12-30 23:53:11 -0500143 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600144#endif
145
146#undef CONFIG_CLOCKS_IN_MHZ
147
148/*
149 * FLASH on the Local Bus
150 * Two banks, one 8MB the other 64MB, using the CFI driver.
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500151 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
152 * CS0 the 8MB boot flash, and CS6 the 64MB flash.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600153 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500154 * Default:
155 * ec00_0000 efff_ffff 64MB SODIMM
156 * ff80_0000 ffff_ffff 8MB soldered flash
157 *
158 * Alternate:
159 * ef80_0000 efff_ffff 8MB soldered flash
160 * fc00_0000 ffff_ffff 64MB SODIMM
161 *
162 * BR0_8M:
Joe Hamman9e3ed392007-12-13 06:45:14 -0600163 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
164 * Port Size = 8 bits = BRx[19:20] = 01
165 * Use GPCM = BRx[24:26] = 000
166 * Valid = BRx[31] = 1
167 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500168 * BR0_64M:
169 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600170 * Port Size = 32 bits = BRx[19:20] = 11
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500171 *
172 * 0 4 8 12 16 20 24 28
173 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
174 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
175 */
176#define CONFIG_SYS_BR0_8M 0xff800801
177#define CONFIG_SYS_BR0_64M 0xfc001801
178
179/*
180 * BR6_8M:
181 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
182 * Port Size = 8 bits = BRx[19:20] = 01
Joe Hamman9e3ed392007-12-13 06:45:14 -0600183 * Use GPCM = BRx[24:26] = 000
184 * Valid = BRx[31] = 1
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500185
186 * BR6_64M:
187 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
188 * Port Size = 32 bits = BRx[19:20] = 11
Joe Hamman9e3ed392007-12-13 06:45:14 -0600189 *
190 * 0 4 8 12 16 20 24 28
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500191 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
192 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
193 */
194#define CONFIG_SYS_BR6_8M 0xef800801
195#define CONFIG_SYS_BR6_64M 0xec001801
196
197/*
198 * OR0_8M:
Joe Hamman9e3ed392007-12-13 06:45:14 -0600199 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
200 * XAM = OR0[17:18] = 11
201 * CSNT = OR0[20] = 1
202 * ACS = half cycle delay = OR0[21:22] = 11
203 * SCY = 6 = OR0[24:27] = 0110
204 * TRLX = use relaxed timing = OR0[29] = 1
205 * EAD = use external address latch delay = OR0[31] = 1
206 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500207 * OR0_64M:
208 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600209 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500210 *
211 * 0 4 8 12 16 20 24 28
212 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
213 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
214 */
215#define CONFIG_SYS_OR0_8M 0xff806e65
216#define CONFIG_SYS_OR0_64M 0xfc006e65
217
218/*
219 * OR6_8M:
220 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600221 * XAM = OR6[17:18] = 11
222 * CSNT = OR6[20] = 1
223 * ACS = half cycle delay = OR6[21:22] = 11
224 * SCY = 6 = OR6[24:27] = 0110
225 * TRLX = use relaxed timing = OR6[29] = 1
226 * EAD = use external address latch delay = OR6[31] = 1
227 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500228 * OR6_64M:
229 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
230 *
Joe Hamman9e3ed392007-12-13 06:45:14 -0600231 * 0 4 8 12 16 20 24 28
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500232 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
233 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
Joe Hamman9e3ed392007-12-13 06:45:14 -0600234 */
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500235#define CONFIG_SYS_OR6_8M 0xff806e65
236#define CONFIG_SYS_OR6_64M 0xfc006e65
Joe Hamman9e3ed392007-12-13 06:45:14 -0600237
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500238#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
Paul Gortmaker3fd673c2011-12-30 23:53:07 -0500240#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600241
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500242#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
243#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
Joe Hamman9e3ed392007-12-13 06:45:14 -0600244
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500245#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
246#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
247#else /* JP12 in alternate position */
248#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
249#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600250
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500251#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
252#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
253
254#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
255#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
256#endif
257
258#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400259#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
260 CONFIG_SYS_ALT_FLASH}
261#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
262#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#undef CONFIG_SYS_FLASH_CHECKSUM
264#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
265#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600266
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200267#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600268
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200269#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_FLASH_CFI
271#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600272
273/* CS5 = Local bus peripherals controlled by the EPLD */
274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_BR5_PRELIM 0xf8000801
276#define CONFIG_SYS_OR5_PRELIM 0xff006e65
277#define CONFIG_SYS_EPLD_BASE 0xf8000000
278#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
279#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
280#define CONFIG_SYS_BD_REV 0xf8300000
281#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600282
283/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400284 * SDRAM on the Local Bus (CS3 and CS4)
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500285 * Note that most boards have a hardware errata where both the
286 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
287 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500288 * A hardware workaround is also available, see README.sbc8548 file.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400291#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600292
293/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400294 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600296 *
297 * For BR3, need:
298 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
299 * port-size = 32-bits = BR2[19:20] = 11
300 * no parity checking = BR2[21:22] = 00
301 * SDRAM for MSEL = BR2[24:26] = 011
302 * Valid = BR[31] = 1
303 *
304 * 0 4 8 12 16 20 24 28
305 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
306 *
307 */
308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_BR3_PRELIM 0xf0001861
Joe Hamman9e3ed392007-12-13 06:45:14 -0600310
311/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400312 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600313 *
314 * For OR3, need:
315 * 64MB mask for AM, OR3[0:7] = 1111 1100
316 * XAM, OR3[17:18] = 11
317 * 10 columns OR3[19-21] = 011
318 * 12 rows OR3[23-25] = 011
319 * EAD set for extra time OR[31] = 0
320 *
321 * 0 4 8 12 16 20 24 28
322 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
323 */
324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600326
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400327/*
328 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
329 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
330 *
331 * For BR4, need:
332 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
333 * port-size = 32-bits = BR2[19:20] = 11
334 * no parity checking = BR2[21:22] = 00
335 * SDRAM for MSEL = BR2[24:26] = 011
336 * Valid = BR[31] = 1
337 *
338 * 0 4 8 12 16 20 24 28
339 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
340 *
341 */
342
343#define CONFIG_SYS_BR4_PRELIM 0xf4001861
344
345/*
346 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
347 *
348 * For OR4, need:
349 * 64MB mask for AM, OR3[0:7] = 1111 1100
350 * XAM, OR3[17:18] = 11
351 * 10 columns OR3[19-21] = 011
352 * 12 rows OR3[23-25] = 011
353 * EAD set for extra time OR[31] = 0
354 *
355 * 0 4 8 12 16 20 24 28
356 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
357 */
358
359#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
362#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
363#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
364#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600365
366/*
Joe Hamman9e3ed392007-12-13 06:45:14 -0600367 * Common settings for all Local Bus SDRAM commands.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600368 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500369#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500370 | LSDMR_BSMA1516 \
371 | LSDMR_PRETOACT3 \
372 | LSDMR_ACTTORW3 \
373 | LSDMR_BUFCMD \
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500374 | LSDMR_BL8 \
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500375 | LSDMR_WRC2 \
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500376 | LSDMR_CL3 \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600377 )
378
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500379#define CONFIG_SYS_LBC_LSDMR_PCHALL \
380 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
381#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
382 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
383#define CONFIG_SYS_LBC_LSDMR_MRW \
384 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
385#define CONFIG_SYS_LBC_LSDMR_RFEN \
386 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
387
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_INIT_RAM_LOCK 1
389#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200390#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600393
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200394#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hamman9e3ed392007-12-13 06:45:14 -0600396
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400397/*
398 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200399 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400400 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200401 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400402 * thing for MONITOR_LEN in both cases.
403 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200404#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500405#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600406
407/* Serial Port */
408#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_NS16550
410#define CONFIG_SYS_NS16550_SERIAL
411#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Gortmaker2738bc82009-09-20 20:36:06 -0400412#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600413
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600415 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
416
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
418#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600419
420/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_HUSH_PARSER
Joe Hamman9e3ed392007-12-13 06:45:14 -0600422
423/* pass open firmware flat tree */
424#define CONFIG_OF_LIBFDT 1
425#define CONFIG_OF_BOARD_SETUP 1
426#define CONFIG_OF_STDOUT_VIA_ALIAS 1
427
428/*
429 * I2C
430 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200431#define CONFIG_SYS_I2C
432#define CONFIG_SYS_I2C_FSL
433#define CONFIG_SYS_FSL_I2C_SPEED 400000
434#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
435#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
Joe Hamman9e3ed392007-12-13 06:45:14 -0600437
438/*
439 * General PCI
440 * Memory space is mapped 1-1, but I/O space must start from 0.
441 */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400442#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600444
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400445#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
446#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
447#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400449#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
450#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
451#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
452#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600453
454#ifdef CONFIG_PCIE1
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400455#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
456#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
457#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400459#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
460#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
461#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
462#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600463#endif
464
465#ifdef CONFIG_RIO
466/*
467 * RapidIO MMU
468 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
470#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600471#endif
472
Joe Hamman9e3ed392007-12-13 06:45:14 -0600473#if defined(CONFIG_PCI)
474
Joe Hamman9e3ed392007-12-13 06:45:14 -0600475#define CONFIG_PCI_PNP /* do pci plug-and-play */
476
477#undef CONFIG_EEPRO100
478#undef CONFIG_TULIP
479
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400480#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600481
Joe Hamman9e3ed392007-12-13 06:45:14 -0600482#endif /* CONFIG_PCI */
483
484
485#if defined(CONFIG_TSEC_ENET)
486
Joe Hamman9e3ed392007-12-13 06:45:14 -0600487#define CONFIG_MII 1 /* MII PHY management */
488#define CONFIG_TSEC1 1
489#define CONFIG_TSEC1_NAME "eTSEC0"
490#define CONFIG_TSEC2 1
491#define CONFIG_TSEC2_NAME "eTSEC1"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600492#undef CONFIG_MPC85XX_FEC
493
Paul Gortmaker58da8892008-12-11 15:47:50 -0500494#define TSEC1_PHY_ADDR 0x19
495#define TSEC2_PHY_ADDR 0x1a
Joe Hamman9e3ed392007-12-13 06:45:14 -0600496
497#define TSEC1_PHYIDX 0
498#define TSEC2_PHYIDX 0
Paul Gortmakerbd931052008-12-11 15:47:49 -0500499
Joe Hamman9e3ed392007-12-13 06:45:14 -0600500#define TSEC1_FLAGS TSEC_GIGABIT
501#define TSEC2_FLAGS TSEC_GIGABIT
Joe Hamman9e3ed392007-12-13 06:45:14 -0600502
503/* Options are: eTSEC[0-3] */
504#define CONFIG_ETHPRIME "eTSEC0"
505#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
506#endif /* CONFIG_TSEC_ENET */
507
508/*
509 * Environment
510 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200511#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200512#define CONFIG_ENV_SIZE 0x2000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200513#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400514#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
515#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200516#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400517#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
518#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
519#else
520#warning undefined environment size/location.
521#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -0600522
523#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600525
526/*
527 * BOOTP options
528 */
529#define CONFIG_BOOTP_BOOTFILESIZE
530#define CONFIG_BOOTP_BOOTPATH
531#define CONFIG_BOOTP_GATEWAY
532#define CONFIG_BOOTP_HOSTNAME
533
534
535/*
536 * Command line configuration.
537 */
538#include <config_cmd_default.h>
539
540#define CONFIG_CMD_PING
541#define CONFIG_CMD_I2C
542#define CONFIG_CMD_MII
543#define CONFIG_CMD_ELF
Becky Bruce199e2622010-06-17 11:37:25 -0500544#define CONFIG_CMD_REGINFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600545
546#if defined(CONFIG_PCI)
547 #define CONFIG_CMD_PCI
548#endif
549
550
551#undef CONFIG_WATCHDOG /* watchdog disabled */
552
553/*
554 * Miscellaneous configurable options
555 */
Paul Gortmakerad22f922008-12-11 15:47:51 -0500556#define CONFIG_CMDLINE_EDITING /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500557#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_LONGHELP /* undef to save memory */
559#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600560#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600562#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600564#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
566#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
567#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600568
569/*
570 * For booting Linux, the board info and command line data
571 * have to be in the first 8 MB of memory, since this is
572 * the maximum mapped by the Linux kernel during initialization.
573 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600575
Joe Hamman9e3ed392007-12-13 06:45:14 -0600576#if defined(CONFIG_CMD_KGDB)
577#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
578#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
579#endif
580
581/*
582 * Environment Configuration
583 */
584
585/* The mac addresses for all ethernet interface */
586#if defined(CONFIG_TSEC_ENET)
587#define CONFIG_HAS_ETH0
588#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
589#define CONFIG_HAS_ETH1
590#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600591#endif
592
593#define CONFIG_IPADDR 192.168.0.55
594
595#define CONFIG_HOSTNAME sbc8548
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000596#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000597#define CONFIG_BOOTFILE "/uImage"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600598#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
599
600#define CONFIG_SERVERIP 192.168.0.2
601#define CONFIG_GATEWAYIP 192.168.0.1
602#define CONFIG_NETMASK 255.255.255.0
603
604#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
605
606#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
607#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
608
609#define CONFIG_BAUDRATE 115200
610
611#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200612"netdev=eth0\0" \
613"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
614"tftpflash=tftpboot $loadaddr $uboot; " \
615 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
616 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
617 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
618 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
619 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
620"consoledev=ttyS0\0" \
621"ramdiskaddr=2000000\0" \
622"ramdiskfile=uRamdisk\0" \
623"fdtaddr=c00000\0" \
624"fdtfile=sbc8548.dtb\0"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600625
626#define CONFIG_NFSBOOTCOMMAND \
627 "setenv bootargs root=/dev/nfs rw " \
628 "nfsroot=$serverip:$rootpath " \
629 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
630 "console=$consoledev,$baudrate $othbootargs;" \
631 "tftp $loadaddr $bootfile;" \
632 "tftp $fdtaddr $fdtfile;" \
633 "bootm $loadaddr - $fdtaddr"
634
635
636#define CONFIG_RAMBOOTCOMMAND \
637 "setenv bootargs root=/dev/ram rw " \
638 "console=$consoledev,$baudrate $othbootargs;" \
639 "tftp $ramdiskaddr $ramdiskfile;" \
640 "tftp $loadaddr $bootfile;" \
641 "tftp $fdtaddr $fdtfile;" \
642 "bootm $loadaddr $ramdiskaddr $fdtaddr"
643
644#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
645
646#endif /* __CONFIG_H */