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wdenk4d75a502003-03-25 16:50:56 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1972dc02005-09-25 16:27:55 +02005 * Copyright (c) 2005 MontaVista Software, Inc.
6 * Vitaly Bordug <vbordug@ru.mvista.com>
7 * Added support for PCI bridge on MPC8272ADS
8 *
wdenk4d75a502003-03-25 16:50:56 +00009 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29
30#ifdef CONFIG_PCI
31
32#include <pci.h>
wdenk5d232d02003-05-22 22:52:13 +000033#include <mpc8260.h>
wdenk4d75a502003-03-25 16:50:56 +000034#include <asm/m8260_pci.h>
wdenk3c74e322004-02-22 23:46:08 +000035#include <asm/io.h>
wdenk4d75a502003-03-25 16:50:56 +000036/*
wdenk3c74e322004-02-22 23:46:08 +000037 * Local->PCI map (from CPU) controlled by
wdenk4d75a502003-03-25 16:50:56 +000038 * MPC826x master window
39 *
wdenk3c74e322004-02-22 23:46:08 +000040 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
41 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
wdenk8bde7f72003-06-27 21:31:46 +000042 *
wdenk3c74e322004-02-22 23:46:08 +000043 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
44 * PCI Mem with prefetch
wdenk5d232d02003-05-22 22:52:13 +000045 *
wdenk3c74e322004-02-22 23:46:08 +000046 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
47 * PCI Mem w/o prefetch
wdenk5d232d02003-05-22 22:52:13 +000048 *
wdenk3c74e322004-02-22 23:46:08 +000049 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
50 * 32-bit PCI IO
wdenk8bde7f72003-06-27 21:31:46 +000051 *
wdenk4d75a502003-03-25 16:50:56 +000052 * PCI->Local map (from PCI)
wdenk3c74e322004-02-22 23:46:08 +000053 * MPC826x slave window controlled by
wdenk4d75a502003-03-25 16:50:56 +000054 *
wdenk3c74e322004-02-22 23:46:08 +000055 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
56 * MPC826x local memory
wdenk4d75a502003-03-25 16:50:56 +000057 */
58
wdenk8bde7f72003-06-27 21:31:46 +000059/*
60 * Slave window that allows PCI masters to access MPC826x local memory.
wdenk4d75a502003-03-25 16:50:56 +000061 * This window is set up using the first set of Inbound ATU registers
62 */
63
wdenk8bde7f72003-06-27 21:31:46 +000064#ifndef CFG_PCI_SLV_MEM_LOCAL
wdenk3c74e322004-02-22 23:46:08 +000065#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +000066#else
67#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
wdenk5d232d02003-05-22 22:52:13 +000068#endif
69
70#ifndef CFG_PCI_SLV_MEM_BUS
wdenk3c74e322004-02-22 23:46:08 +000071#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
wdenk5d232d02003-05-22 22:52:13 +000072#else
73#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
74#endif
75
76#ifndef CFG_PICMR0_MASK_ATTRIB
wdenk4d75a502003-03-25 16:50:56 +000077#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
wdenk8bde7f72003-06-27 21:31:46 +000078 PICMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +000079#else
80#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
81#endif
wdenk4d75a502003-03-25 16:50:56 +000082
wdenk8bde7f72003-06-27 21:31:46 +000083/*
wdenk5d232d02003-05-22 22:52:13 +000084 * These are the windows that allow the CPU to access PCI address space.
wdenk8bde7f72003-06-27 21:31:46 +000085 * All three PCI master windows, which allow the CPU to access PCI
86 * prefetch, non prefetch, and IO space (see below), must all fit within
wdenk5d232d02003-05-22 22:52:13 +000087 * these windows.
wdenk4d75a502003-03-25 16:50:56 +000088 */
89
wdenk5d232d02003-05-22 22:52:13 +000090/* PCIBR0 */
91#ifndef CFG_PCI_MSTR0_LOCAL
wdenk3c74e322004-02-22 23:46:08 +000092#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +000093#else
wdenk5d232d02003-05-22 22:52:13 +000094#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
95#endif
96
97#ifndef CFG_PCIMSK0_MASK
wdenk3c74e322004-02-22 23:46:08 +000098#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +000099#else
100#define PCIMSK0_MASK CFG_PCIMSK0_MASK
101#endif
102
103/* PCIBR1 */
104#ifndef CFG_PCI_MSTR1_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000105#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000106#else
107#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000108#endif
109
110#ifndef CFG_PCIMSK1_MASK
wdenk3c74e322004-02-22 23:46:08 +0000111#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000112#else
wdenk3c74e322004-02-22 23:46:08 +0000113#define PCIMSK1_MASK CFG_PCIMSK1_MASK
wdenk5d232d02003-05-22 22:52:13 +0000114#endif
wdenk4d75a502003-03-25 16:50:56 +0000115
wdenk8bde7f72003-06-27 21:31:46 +0000116/*
wdenk4d75a502003-03-25 16:50:56 +0000117 * Master window that allows the CPU to access PCI Memory (prefetch).
118 * This window will be setup with the first set of Outbound ATU registers
119 * in the bridge.
120 */
121
wdenk5d232d02003-05-22 22:52:13 +0000122#ifndef CFG_PCI_MSTR_MEM_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000123#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
wdenk5d232d02003-05-22 22:52:13 +0000124#else
125#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
126#endif
127
128#ifndef CFG_PCI_MSTR_MEM_BUS
wdenk3c74e322004-02-22 23:46:08 +0000129#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
wdenk5d232d02003-05-22 22:52:13 +0000130#else
131#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
132#endif
133
134#ifndef CFG_CPU_PCI_MEM_START
135#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
136#else
137#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
138#endif
139
140#ifndef CFG_PCI_MSTR_MEM_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000141#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
wdenk5d232d02003-05-22 22:52:13 +0000142#else
143#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
144#endif
145
146#ifndef CFG_POCMR0_MASK_ATTRIB
wdenk4d75a502003-03-25 16:50:56 +0000147#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000148#else
149#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
150#endif
wdenk4d75a502003-03-25 16:50:56 +0000151
wdenk8bde7f72003-06-27 21:31:46 +0000152/*
wdenk4d75a502003-03-25 16:50:56 +0000153 * Master window that allows the CPU to access PCI Memory (non-prefetch).
154 * This window will be setup with the second set of Outbound ATU registers
155 * in the bridge.
156 */
157
wdenk8bde7f72003-06-27 21:31:46 +0000158#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000159#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000160#else
161#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000162#endif
163
wdenk8bde7f72003-06-27 21:31:46 +0000164#ifndef CFG_PCI_MSTR_MEMIO_BUS
wdenk3c74e322004-02-22 23:46:08 +0000165#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
wdenk8bde7f72003-06-27 21:31:46 +0000166#else
167#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
wdenk5d232d02003-05-22 22:52:13 +0000168#endif
169
wdenk8bde7f72003-06-27 21:31:46 +0000170#ifndef CFG_CPU_PCI_MEMIO_START
171#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
172#else
173#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
wdenk5d232d02003-05-22 22:52:13 +0000174#endif
175
wdenk8bde7f72003-06-27 21:31:46 +0000176#ifndef CFG_PCI_MSTR_MEMIO_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000177#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
wdenk8bde7f72003-06-27 21:31:46 +0000178#else
179#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000180#endif
181
182#ifndef CFG_POCMR1_MASK_ATTRIB
wdenk3c74e322004-02-22 23:46:08 +0000183#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
wdenk5d232d02003-05-22 22:52:13 +0000184#else
185#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
186#endif
wdenk4d75a502003-03-25 16:50:56 +0000187
wdenk8bde7f72003-06-27 21:31:46 +0000188/*
wdenk4d75a502003-03-25 16:50:56 +0000189 * Master window that allows the CPU to access PCI IO space.
190 * This window will be setup with the third set of Outbound ATU registers
191 * in the bridge.
192 */
193
wdenk8bde7f72003-06-27 21:31:46 +0000194#ifndef CFG_PCI_MSTR_IO_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000195#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000196#else
197#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
wdenk66fd3d12003-05-18 11:30:09 +0000198#endif
wdenk5d232d02003-05-22 22:52:13 +0000199
wdenk8bde7f72003-06-27 21:31:46 +0000200#ifndef CFG_PCI_MSTR_IO_BUS
wdenk3c74e322004-02-22 23:46:08 +0000201#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
wdenk8bde7f72003-06-27 21:31:46 +0000202#else
203#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
wdenk5d232d02003-05-22 22:52:13 +0000204#endif
205
wdenk8bde7f72003-06-27 21:31:46 +0000206#ifndef CFG_CPU_PCI_IO_START
207#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
208#else
209#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
wdenk5d232d02003-05-22 22:52:13 +0000210#endif
211
wdenk8bde7f72003-06-27 21:31:46 +0000212#ifndef CFG_PCI_MSTR_IO_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000213#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
wdenk8bde7f72003-06-27 21:31:46 +0000214#else
215#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000216#endif
217
218#ifndef CFG_POCMR2_MASK_ATTRIB
wdenk3c74e322004-02-22 23:46:08 +0000219#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
wdenk5d232d02003-05-22 22:52:13 +0000220#else
221#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
222#endif
wdenk4d75a502003-03-25 16:50:56 +0000223
224/* PCI bus configuration registers.
225 */
226
227#define PCI_CLASS_BRIDGE_CTLR 0x06
228
229
wdenk3c74e322004-02-22 23:46:08 +0000230static inline void pci_outl (u32 addr, u32 data)
wdenk4d75a502003-03-25 16:50:56 +0000231{
wdenk3c74e322004-02-22 23:46:08 +0000232 *(volatile u32 *) addr = cpu_to_le32 (data);
wdenk4d75a502003-03-25 16:50:56 +0000233}
234
wdenk3c74e322004-02-22 23:46:08 +0000235void pci_mpc8250_init (struct pci_controller *hose)
wdenk4d75a502003-03-25 16:50:56 +0000236{
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200237#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk3c74e322004-02-22 23:46:08 +0000238 DECLARE_GLOBAL_DATA_PTR;
wdenk5d232d02003-05-22 22:52:13 +0000239#endif
wdenk3c74e322004-02-22 23:46:08 +0000240 u16 tempShort;
wdenk4d75a502003-03-25 16:50:56 +0000241
wdenk3c74e322004-02-22 23:46:08 +0000242 volatile immap_t *immap = (immap_t *) CFG_IMMR;
243 pci_dev_t host_devno = PCI_BDF (0, 0, 0);
wdenk4d75a502003-03-25 16:50:56 +0000244
wdenk3c74e322004-02-22 23:46:08 +0000245 pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
246 CFG_IMMR + PCI_CFG_DATA_REG);
247
248 /*
249 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
250 */
wdenk5d232d02003-05-22 22:52:13 +0000251#ifdef CONFIG_MPC8266ADS
wdenk3c74e322004-02-22 23:46:08 +0000252 immap->im_siu_conf.sc_siumcr =
253 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
254 | SIUMCR_LBPC01;
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200255#elif defined CONFIG_MPC8272
256 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
257 ~SIUMCR_BBD &
258 ~SIUMCR_ESE &
259 ~SIUMCR_PBSE &
260 ~SIUMCR_CDIS &
261 ~SIUMCR_DPPC11 &
262 ~SIUMCR_L2CPC11 &
263 ~SIUMCR_LBPC11 &
264 ~SIUMCR_APPC11 &
265 ~SIUMCR_CS10PC11 &
266 ~SIUMCR_BCTLC11 &
267 ~SIUMCR_MMR11)
268 | SIUMCR_DPPC11
269 | SIUMCR_L2CPC01
270 | SIUMCR_LBPC00
271 | SIUMCR_APPC10
272 | SIUMCR_CS10PC00
273 | SIUMCR_BCTLC00
274 | SIUMCR_MMR11;
275
wdenk5d232d02003-05-22 22:52:13 +0000276#else
wdenk3c74e322004-02-22 23:46:08 +0000277 /*
278 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
279 * and local bus for PCI (SIUMCR [LBPC]).
280 */
281 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
282 ~SIUMCR_LBPC11 &
wdenk8bde7f72003-06-27 21:31:46 +0000283 ~SIUMCR_CS10PC11 &
wdenk3c74e322004-02-22 23:46:08 +0000284 ~SIUMCR_LBPC11) |
285 SIUMCR_LBPC01 |
286 SIUMCR_CS10PC01 |
287 SIUMCR_APPC10;
wdenk5d232d02003-05-22 22:52:13 +0000288#endif
wdenk4d75a502003-03-25 16:50:56 +0000289
wdenk3c74e322004-02-22 23:46:08 +0000290 /* Make PCI lowest priority */
291 /* Each 4 bits is a device bus request and the MS 4bits
292 is highest priority */
293 /* Bus 4bit value
294 --- ----------
295 CPM high 0b0000
296 CPM middle 0b0001
297 CPM low 0b0010
298 PCI reguest 0b0011
299 Reserved 0b0100
300 Reserved 0b0101
301 Internal Core 0b0110
302 External Master 1 0b0111
303 External Master 2 0b1000
304 External Master 3 0b1001
305 The rest are reserved */
306 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
wdenk4d75a502003-03-25 16:50:56 +0000307
wdenk3c74e322004-02-22 23:46:08 +0000308 /* Park bus on core while modifying PCI Bus accesses */
309 immap->im_siu_conf.sc_ppc_acr = 0x6;
wdenk4d75a502003-03-25 16:50:56 +0000310
wdenk3c74e322004-02-22 23:46:08 +0000311 /*
312 * Set up master windows that allow the CPU to access PCI space. These
313 * windows are set up using the two SIU PCIBR registers.
314 */
315 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
316 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
wdenk5d232d02003-05-22 22:52:13 +0000317
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200318#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenkd4326ac2004-04-18 21:17:30 +0000319 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
320 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
wdenk8bde7f72003-06-27 21:31:46 +0000321#endif
wdenk4d75a502003-03-25 16:50:56 +0000322
wdenk3c74e322004-02-22 23:46:08 +0000323 /* Release PCI RST (by default the PCI RST signal is held low) */
324 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
wdenk4d75a502003-03-25 16:50:56 +0000325
wdenk3c74e322004-02-22 23:46:08 +0000326 /* give it some time */
327 {
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200328#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk8bde7f72003-06-27 21:31:46 +0000329 /* Give the PCI cards more time to initialize before query
wdenk3c74e322004-02-22 23:46:08 +0000330 This might be good for other boards also
331 */
332 int i;
333
334 for (i = 0; i < 1000; ++i)
wdenk5d232d02003-05-22 22:52:13 +0000335#endif
wdenk3c74e322004-02-22 23:46:08 +0000336 udelay (1000);
337 }
wdenk4d75a502003-03-25 16:50:56 +0000338
wdenk3c74e322004-02-22 23:46:08 +0000339 /*
340 * Set up master window that allows the CPU to access PCI Memory (prefetch)
341 * space. This window is set up using the first set of Outbound ATU registers.
342 */
343 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
344 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
345 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000346
wdenk3c74e322004-02-22 23:46:08 +0000347 /*
348 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
349 * space. This window is set up using the second set of Outbound ATU registers.
350 */
351 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
352 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
353 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
wdenk8bde7f72003-06-27 21:31:46 +0000354
wdenk3c74e322004-02-22 23:46:08 +0000355 /*
356 * Set up master window that allows the CPU to access PCI IO space. This window
357 * is set up using the third set of Outbound ATU registers.
358 */
359 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
360 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
361 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000362
wdenk3c74e322004-02-22 23:46:08 +0000363 /*
364 * Set up slave window that allows PCI masters to access MPC826x local memory.
365 * This window is set up using the first set of Inbound ATU registers
366 */
367 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
368 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
369 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000370
wdenk3c74e322004-02-22 23:46:08 +0000371 /* See above for description - puts PCI request as highest priority */
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200372#ifdef CONFIG_MPC8272
373 immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
374#else
wdenk3c74e322004-02-22 23:46:08 +0000375 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200376#endif
wdenk4d75a502003-03-25 16:50:56 +0000377
wdenk3c74e322004-02-22 23:46:08 +0000378 /* Park the bus on the PCI */
379 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
wdenk4d75a502003-03-25 16:50:56 +0000380
wdenk3c74e322004-02-22 23:46:08 +0000381 /* Host mode - specify the bridge as a host-PCI bridge */
wdenk4d75a502003-03-25 16:50:56 +0000382
wdenk3c74e322004-02-22 23:46:08 +0000383 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
384 PCI_CLASS_BRIDGE_CTLR);
wdenk4d75a502003-03-25 16:50:56 +0000385
wdenk3c74e322004-02-22 23:46:08 +0000386 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
387 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
388 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
389 tempShort | PCI_COMMAND_MASTER |
390 PCI_COMMAND_MEMORY);
wdenk4d75a502003-03-25 16:50:56 +0000391
wdenk7a8e9bed2003-05-31 18:35:21 +0000392 /* do some bridge init, should be done on all 8260 based bridges */
wdenk3c74e322004-02-22 23:46:08 +0000393 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
394 0x08);
395 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
396 0xF8);
wdenk7a8e9bed2003-05-31 18:35:21 +0000397
wdenk3c74e322004-02-22 23:46:08 +0000398 hose->first_busno = 0;
399 hose->last_busno = 0xff;
wdenk4d75a502003-03-25 16:50:56 +0000400
wdenk3c74e322004-02-22 23:46:08 +0000401 /* System memory space */
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200402#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk3c74e322004-02-22 23:46:08 +0000403 pci_set_region (hose->regions + 0,
404 PCI_SLV_MEM_BUS,
405 PCI_SLV_MEM_LOCAL,
406 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
wdenk5d232d02003-05-22 22:52:13 +0000407#else
wdenk3c74e322004-02-22 23:46:08 +0000408 pci_set_region (hose->regions + 0,
409 CFG_SDRAM_BASE,
410 CFG_SDRAM_BASE,
411 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
wdenk5d232d02003-05-22 22:52:13 +0000412#endif
wdenk4d75a502003-03-25 16:50:56 +0000413
wdenk3c74e322004-02-22 23:46:08 +0000414 /* PCI memory space */
Wolfgang Denk1972dc02005-09-25 16:27:55 +0200415#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
wdenk3c74e322004-02-22 23:46:08 +0000416 pci_set_region (hose->regions + 1,
417 PCI_MSTR_MEMIO_BUS,
418 PCI_MSTR_MEMIO_LOCAL,
419 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
wdenk5d232d02003-05-22 22:52:13 +0000420#else
wdenk3c74e322004-02-22 23:46:08 +0000421 pci_set_region (hose->regions + 1,
422 PCI_MSTR_MEM_BUS,
423 PCI_MSTR_MEM_LOCAL,
424 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
wdenk5d232d02003-05-22 22:52:13 +0000425#endif
wdenk4d75a502003-03-25 16:50:56 +0000426
wdenk3c74e322004-02-22 23:46:08 +0000427 /* PCI I/O space */
428 pci_set_region (hose->regions + 2,
429 PCI_MSTR_IO_BUS,
430 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
wdenk4d75a502003-03-25 16:50:56 +0000431
wdenk3c74e322004-02-22 23:46:08 +0000432 hose->region_count = 3;
wdenk4d75a502003-03-25 16:50:56 +0000433
wdenk3c74e322004-02-22 23:46:08 +0000434 pci_register_hose (hose);
435 /* Mask off master abort machine checks */
436 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
437 eieio ();
wdenk4d75a502003-03-25 16:50:56 +0000438
wdenk3c74e322004-02-22 23:46:08 +0000439 hose->last_busno = pci_hose_scan (hose);
440
441
442 /* clear the error in the error status register */
443 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
444
445 /* unmask master abort machine checks */
446 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
wdenk4d75a502003-03-25 16:50:56 +0000447}
448
wdenk3c74e322004-02-22 23:46:08 +0000449#endif /* CONFIG_PCI */