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wdenkf39748a2004-06-09 13:37:52 +00001/*
2 * See file CREDITS for list of people who contributed to this
3 * project.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/*
22 * lh7a400 SoC interface
23 */
24
25#ifndef __LH7A400_H__
26#define __LH7A400_H__
27
28#include "lh7a40x.h"
29
30/* Interrupt Controller (userguide 8.2.1) */
31typedef struct {
32 volatile u32 intsr;
33 volatile u32 intrsr;
34 volatile u32 intens;
35 volatile u32 intenc;
36 volatile u32 rsvd1;
37 volatile u32 rsvd2;
38 volatile u32 rsvd3;
39} /*__attribute__((__packed__))*/ lh7a400_interrupt_t;
40#define LH7A400_INTERRUPT_BASE (0x80000500)
wdenkf832d8a2004-06-10 21:55:33 +000041#define LH7A400_INTERRUPT_PTR ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE)
wdenkf39748a2004-06-09 13:37:52 +000042
43/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
44typedef struct {
wdenkf832d8a2004-06-10 21:55:33 +000045 lh7a40x_dmachan_t chan[15];
wdenkf39748a2004-06-09 13:37:52 +000046 volatile u32 glblint;
47 volatile u32 rsvd1;
48 volatile u32 rsvd2;
49 volatile u32 rsvd3;
50} /*__attribute__((__packed__))*/ lh7a400_dma_t;
wdenkf832d8a2004-06-10 21:55:33 +000051
wdenkf39748a2004-06-09 13:37:52 +000052#define LH7A400_DMA_BASE (0x80002800)
53#define DMA_USBTX_OFFSET (0x000)
54#define DMA_USBRX_OFFSET (0x040)
55#define DMA_MMCTX_OFFSET (0x080)
56#define DMA_MMCRX_OFFSET (0x0C0)
57#define DMA_AC97_BASE (0x80002A00)
58
wdenkf832d8a2004-06-10 21:55:33 +000059#define LH7A400_DMA_PTR ((lh7a400_dma_t*) LH7A400_DMA_BASE)
60#define LH7A400_DMA_USBTX \
61 ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET))
62#define LH7A400_DMA_USBRX \
63 ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET))
64#define LH7A400_DMA_MMCTX \
65 ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET))
66#define LH7A400_DMA_MMCRX \
67 ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET))
68#define LH7A400_AC97RX(n) \
69 ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
70 ((2*n) * sizeof(lh7a400_dmachan_t))))
71#define LH7A400_AC97TX(n) \
72 ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
73 (((2*n)+1) * sizeof(lh7a400_dmachan_t))))
wdenkf39748a2004-06-09 13:37:52 +000074
75#endif /* __LH7A400_H__ */