Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | 19dc7e1 | 2009-05-16 10:47:42 +0200 | [diff] [blame^] | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 3 | * |
| 4 | * MPC512x Internal Memory Map |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | * |
| 21 | * Based on the MPC83xx header. |
| 22 | */ |
| 23 | |
| 24 | #ifndef __IMMAP_512x__ |
| 25 | #define __IMMAP_512x__ |
| 26 | |
| 27 | #include <asm/types.h> |
| 28 | |
| 29 | typedef struct law512x { |
| 30 | u32 bar; /* Base Addr Register */ |
| 31 | u32 ar; /* Attributes Register */ |
John Rigby | 5f91db7 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 32 | } law512x_t; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 33 | |
| 34 | /* |
| 35 | * System configuration registers |
| 36 | */ |
| 37 | typedef struct sysconf512x { |
| 38 | u32 immrbar; /* Internal memory map base address register */ |
| 39 | u8 res0[0x1c]; |
| 40 | u32 lpbaw; /* LP Boot Access Window */ |
| 41 | u32 lpcs0aw; /* LP CS0 Access Window */ |
| 42 | u32 lpcs1aw; /* LP CS1 Access Window */ |
| 43 | u32 lpcs2aw; /* LP CS2 Access Window */ |
| 44 | u32 lpcs3aw; /* LP CS3 Access Window */ |
| 45 | u32 lpcs4aw; /* LP CS4 Access Window */ |
| 46 | u32 lpcs5aw; /* LP CS5 Access Window */ |
| 47 | u32 lpcs6aw; /* LP CS6 Access Window */ |
| 48 | u32 lpcs7aw; /* LP CS7 Access Window */ |
| 49 | u8 res1[0x1c]; |
John Rigby | 5f91db7 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 50 | law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 51 | u8 res2[0x28]; |
John Rigby | 5f91db7 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 52 | law512x_t ddrlaw; /* DDR Local Access Window */ |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 53 | u8 res3[0x18]; |
| 54 | u32 mbxbar; /* MBX Base Address */ |
| 55 | u32 srambar; /* SRAM Base Address */ |
| 56 | u32 nfcbar; /* NFC Base Address */ |
| 57 | u8 res4[0x34]; |
| 58 | u32 spridr; /* System Part and Revision ID Register */ |
| 59 | u32 spcr; /* System Priority Configuration Register */ |
| 60 | u8 res5[0xf8]; |
| 61 | } sysconf512x_t; |
| 62 | |
| 63 | /* |
| 64 | * Watch Dog Timer (WDT) Registers |
| 65 | */ |
| 66 | typedef struct wdt512x { |
| 67 | u8 res0[4]; |
| 68 | u32 swcrr; /* System watchdog control register */ |
| 69 | u32 swcnr; /* System watchdog count register */ |
| 70 | u8 res1[2]; |
| 71 | u16 swsrr; /* System watchdog service register */ |
| 72 | u8 res2[0xF0]; |
| 73 | } wdt512x_t; |
| 74 | |
| 75 | /* |
| 76 | * RTC Module Registers |
| 77 | */ |
| 78 | typedef struct rtclk512x { |
| 79 | u8 fixme[0x100]; |
| 80 | } rtclk512x_t; |
| 81 | |
| 82 | /* |
| 83 | * General Purpose Timer |
| 84 | */ |
| 85 | typedef struct gpt512x { |
| 86 | u8 fixme[0x100]; |
| 87 | } gpt512x_t; |
| 88 | |
| 89 | /* |
| 90 | * Integrated Programmable Interrupt Controller |
| 91 | */ |
| 92 | typedef struct ipic512x { |
| 93 | u8 fixme[0x100]; |
| 94 | } ipic512x_t; |
| 95 | |
| 96 | /* |
| 97 | * System Arbiter Registers |
| 98 | */ |
| 99 | typedef struct arbiter512x { |
| 100 | u32 acr; /* Arbiter Configuration Register */ |
| 101 | u32 atr; /* Arbiter Timers Register */ |
| 102 | u32 ater; /* Arbiter Transfer Error Register */ |
| 103 | u32 aer; /* Arbiter Event Register */ |
| 104 | u32 aidr; /* Arbiter Interrupt Definition Register */ |
| 105 | u32 amr; /* Arbiter Mask Register */ |
| 106 | u32 aeatr; /* Arbiter Event Attributes Register */ |
| 107 | u32 aeadr; /* Arbiter Event Address Register */ |
| 108 | u32 aerr; /* Arbiter Event Response Register */ |
| 109 | u8 res1[0xDC]; |
| 110 | } arbiter512x_t; |
| 111 | |
| 112 | /* |
| 113 | * Reset Module |
| 114 | */ |
| 115 | typedef struct reset512x { |
| 116 | u32 rcwl; /* Reset Configuration Word Low Register */ |
| 117 | u32 rcwh; /* Reset Configuration Word High Register */ |
| 118 | u8 res0[8]; |
| 119 | u32 rsr; /* Reset Status Register */ |
| 120 | u32 rmr; /* Reset Mode Register */ |
| 121 | u32 rpr; /* Reset protection Register */ |
| 122 | u32 rcr; /* Reset Control Register */ |
| 123 | u32 rcer; /* Reset Control Enable Register */ |
| 124 | u8 res1[0xDC]; |
| 125 | } reset512x_t; |
| 126 | |
| 127 | /* |
| 128 | * Clock Module |
| 129 | */ |
| 130 | typedef struct clk512x { |
| 131 | u32 spmr; /* System PLL Mode Register */ |
| 132 | u32 sccr[2]; /* System Clock Control Registers */ |
| 133 | u32 scfr[2]; /* System Clock Frequency Registers */ |
| 134 | u8 res0[4]; |
| 135 | u32 bcr; /* Bread Crumb Register */ |
| 136 | u32 pscccr[12]; /* PSC0-11 Clock Control Registers */ |
| 137 | u32 spccr; /* SPDIF Clock Control Registers */ |
| 138 | u32 cccr; /* CFM Clock Control Registers */ |
| 139 | u32 dccr; /* DIU Clock Control Registers */ |
| 140 | u8 res1[0xa8]; |
| 141 | } clk512x_t; |
| 142 | |
| 143 | /* |
| 144 | * Power Management Control Module |
| 145 | */ |
| 146 | typedef struct pmc512x { |
| 147 | u8 fixme[0x100]; |
| 148 | } pmc512x_t; |
| 149 | |
| 150 | /* |
| 151 | * General purpose I/O module |
| 152 | */ |
| 153 | typedef struct gpio512x { |
Wolfgang Denk | 19dc7e1 | 2009-05-16 10:47:42 +0200 | [diff] [blame^] | 154 | u32 gpdir; |
| 155 | u32 gpodr; |
| 156 | u32 gpdat; |
| 157 | u32 gpier; |
| 158 | u32 gpimr; |
| 159 | u32 gpicr1; |
| 160 | u32 gpicr2; |
| 161 | u8 res0[0xE4]; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 162 | } gpio512x_t; |
| 163 | |
| 164 | /* |
| 165 | * DDR Memory Controller Memory Map |
| 166 | */ |
| 167 | typedef struct ddr512x { |
| 168 | u32 ddr_sys_config; /* System Configuration Register */ |
| 169 | u32 ddr_time_config0; /* Timing Configuration Register */ |
| 170 | u32 ddr_time_config1; /* Timing Configuration Register */ |
| 171 | u32 ddr_time_config2; /* Timing Configuration Register */ |
| 172 | u32 ddr_command; /* Command Register */ |
| 173 | u32 ddr_compact_command; /* Compact Command Register */ |
| 174 | u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */ |
| 175 | u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */ |
| 176 | u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */ |
| 177 | u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */ |
| 178 | u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */ |
| 179 | u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ |
| 180 | u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ |
| 181 | u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ |
| 182 | u32 DQS_config_offset_count; /* DQS Config Offset Count */ |
| 183 | u32 DQS_config_offset_time; /* DQS Config Offset Time */ |
| 184 | u32 DQS_delay_status; /* DQS Delay Status */ |
| 185 | u32 res0[0xF]; |
| 186 | u32 prioman_config1; /* Priority Manager Configuration */ |
| 187 | u32 prioman_config2; /* Priority Manager Configuration */ |
| 188 | u32 hiprio_config; /* High Priority Configuration */ |
| 189 | u32 lut_table0_main_upper; /* LUT0 Main Upper */ |
| 190 | u32 lut_table1_main_upper; /* LUT1 Main Upper */ |
| 191 | u32 lut_table2_main_upper; /* LUT2 Main Upper */ |
| 192 | u32 lut_table3_main_upper; /* LUT3 Main Upper */ |
| 193 | u32 lut_table4_main_upper; /* LUT4 Main Upper */ |
| 194 | u32 lut_table0_main_lower; /* LUT0 Main Lower */ |
| 195 | u32 lut_table1_main_lower; /* LUT1 Main Lower */ |
| 196 | u32 lut_table2_main_lower; /* LUT2 Main Lower */ |
| 197 | u32 lut_table3_main_lower; /* LUT3 Main Lower */ |
| 198 | u32 lut_table4_main_lower; /* LUT4 Main Lower */ |
| 199 | u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */ |
| 200 | u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */ |
| 201 | u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */ |
| 202 | u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */ |
| 203 | u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */ |
| 204 | u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */ |
| 205 | u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */ |
| 206 | u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */ |
| 207 | u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */ |
| 208 | u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */ |
| 209 | u32 performance_monitor_config; |
| 210 | u32 event_time_counter; |
| 211 | u32 event_time_preset; |
| 212 | u32 performance_monitor1_address_low; |
| 213 | u32 performance_monitor2_address_low; |
| 214 | u32 performance_monitor1_address_hi; |
| 215 | u32 performance_monitor2_address_hi; |
| 216 | u32 res1[2]; |
| 217 | u32 performance_monitor1_read_counter; |
| 218 | u32 performance_monitor2_read_counter; |
| 219 | u32 performance_monitor1_write_counter; |
| 220 | u32 performance_monitor2_write_counter; |
| 221 | u32 granted_ack_counter0; |
| 222 | u32 granted_ack_counter1; |
| 223 | u32 granted_ack_counter2; |
| 224 | u32 granted_ack_counter3; |
| 225 | u32 granted_ack_counter4; |
| 226 | u32 cumulative_wait_counter0; |
| 227 | u32 cumulative_wait_counter1; |
| 228 | u32 cumulative_wait_counter2; |
| 229 | u32 cumulative_wait_counter3; |
| 230 | u32 cumulative_wait_counter4; |
| 231 | u32 summed_priority_counter0; |
| 232 | u32 summed_priority_counter1; |
| 233 | u32 summed_priority_counter2; |
| 234 | u32 summed_priority_counter3; |
| 235 | u32 summed_priority_counter4; |
| 236 | u32 res2[0x3AD]; |
| 237 | } ddr512x_t; |
| 238 | |
| 239 | |
| 240 | /* |
| 241 | * DMA/Messaging Unit |
| 242 | */ |
| 243 | typedef struct dma512x { |
| 244 | u8 fixme[0x1800]; |
| 245 | } dma512x_t; |
| 246 | |
| 247 | /* |
| 248 | * PCI Software Configuration Registers |
| 249 | */ |
| 250 | typedef struct pciconf512x { |
John Rigby | 5f91db7 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 251 | u32 config_address; |
| 252 | u32 config_data; |
| 253 | u32 int_ack; |
| 254 | u8 res[116]; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 255 | } pciconf512x_t; |
| 256 | |
| 257 | /* |
John Rigby | 5f91db7 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 258 | * PCI Outbound Translation Register |
| 259 | */ |
| 260 | typedef struct pci_outbound_window { |
| 261 | u32 potar; |
| 262 | u8 res0[4]; |
| 263 | u32 pobar; |
| 264 | u8 res1[4]; |
| 265 | u32 pocmr; |
| 266 | u8 res2[4]; |
| 267 | } pot512x_t; |
| 268 | |
| 269 | /* |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 270 | * Sequencer |
| 271 | */ |
| 272 | typedef struct ios512x { |
John Rigby | 5f91db7 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 273 | pot512x_t pot[6]; |
| 274 | u8 res0[0x60]; |
| 275 | u32 pmcr; |
| 276 | u8 res1[4]; |
| 277 | u32 dtcr; |
| 278 | u8 res2[4]; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 279 | } ios512x_t; |
| 280 | |
| 281 | /* |
| 282 | * PCI Controller |
| 283 | */ |
| 284 | typedef struct pcictrl512x { |
John Rigby | 5f91db7 | 2008-02-26 09:38:14 -0700 | [diff] [blame] | 285 | u32 esr; |
| 286 | u32 ecdr; |
| 287 | u32 eer; |
| 288 | u32 eatcr; |
| 289 | u32 eacr; |
| 290 | u32 eeacr; |
| 291 | u32 edlcr; |
| 292 | u32 edhcr; |
| 293 | u32 gcr; |
| 294 | u32 ecr; |
| 295 | u32 gsr; |
| 296 | u8 res0[12]; |
| 297 | u32 pitar2; |
| 298 | u8 res1[4]; |
| 299 | u32 pibar2; |
| 300 | u32 piebar2; |
| 301 | u32 piwar2; |
| 302 | u8 res2[4]; |
| 303 | u32 pitar1; |
| 304 | u8 res3[4]; |
| 305 | u32 pibar1; |
| 306 | u32 piebar1; |
| 307 | u32 piwar1; |
| 308 | u8 res4[4]; |
| 309 | u32 pitar0; |
| 310 | u8 res5[4]; |
| 311 | u32 pibar0; |
| 312 | u8 res6[4]; |
| 313 | u32 piwar0; |
| 314 | u8 res7[132]; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 315 | } pcictrl512x_t; |
| 316 | |
| 317 | |
| 318 | /* |
| 319 | * MSCAN |
| 320 | */ |
| 321 | typedef struct mscan512x { |
| 322 | u8 fixme[0x100]; |
| 323 | } mscan512x_t; |
| 324 | |
| 325 | /* |
| 326 | * BDLC |
| 327 | */ |
| 328 | typedef struct bdlc512x { |
| 329 | u8 fixme[0x100]; |
| 330 | } bdlc512x_t; |
| 331 | |
| 332 | /* |
| 333 | * SDHC |
| 334 | */ |
| 335 | typedef struct sdhc512x { |
| 336 | u8 fixme[0x100]; |
| 337 | } sdhc512x_t; |
| 338 | |
| 339 | /* |
| 340 | * SPDIF |
| 341 | */ |
| 342 | typedef struct spdif512x { |
| 343 | u8 fixme[0x100]; |
| 344 | } spdif512x_t; |
| 345 | |
| 346 | /* |
| 347 | * I2C |
| 348 | */ |
| 349 | typedef struct i2c512x_dev { |
| 350 | volatile u32 madr; /* I2Cn + 0x00 */ |
| 351 | volatile u32 mfdr; /* I2Cn + 0x04 */ |
| 352 | volatile u32 mcr; /* I2Cn + 0x08 */ |
| 353 | volatile u32 msr; /* I2Cn + 0x0C */ |
| 354 | volatile u32 mdr; /* I2Cn + 0x10 */ |
| 355 | u8 res0[0x0C]; |
| 356 | } i2c512x_dev_t; |
| 357 | |
| 358 | typedef struct i2c512x { |
| 359 | i2c512x_dev_t dev[3]; |
| 360 | volatile u32 icr; |
| 361 | volatile u32 mifr; |
| 362 | u8 res0[0x98]; |
| 363 | } i2c512x_t; |
| 364 | |
| 365 | /* |
| 366 | * AXE |
| 367 | */ |
| 368 | typedef struct axe512x { |
| 369 | u8 fixme[0x100]; |
| 370 | } axe512x_t; |
| 371 | |
| 372 | /* |
| 373 | * DIU |
| 374 | */ |
| 375 | typedef struct diu512x { |
| 376 | u8 fixme[0x100]; |
| 377 | } diu512x_t; |
| 378 | |
| 379 | /* |
| 380 | * CFM |
| 381 | */ |
| 382 | typedef struct cfm512x { |
| 383 | u8 fixme[0x100]; |
| 384 | } cfm512x_t; |
| 385 | |
| 386 | /* |
| 387 | * FEC |
| 388 | */ |
| 389 | typedef struct fec512x { |
Wolfgang Denk | 19dc7e1 | 2009-05-16 10:47:42 +0200 | [diff] [blame^] | 390 | u32 fec_id; /* FEC_ID register */ |
| 391 | u32 ievent; /* Interrupt event register */ |
| 392 | u32 imask; /* Interrupt mask register */ |
| 393 | u32 reserved_01; |
| 394 | u32 r_des_active; /* Receive ring updated flag */ |
| 395 | u32 x_des_active; /* Transmit ring updated flag */ |
| 396 | u32 reserved_02[3]; |
| 397 | u32 ecntrl; /* Ethernet control register */ |
| 398 | u32 reserved_03[6]; |
| 399 | u32 mii_data; /* MII data register */ |
| 400 | u32 mii_speed; /* MII speed register */ |
| 401 | u32 reserved_04[7]; |
| 402 | u32 mib_control; /* MIB control/status register */ |
| 403 | u32 reserved_05[7]; |
| 404 | u32 r_cntrl; /* Receive control register */ |
| 405 | u32 r_hash; /* Receive hash */ |
| 406 | u32 reserved_06[14]; |
| 407 | u32 x_cntrl; /* Transmit control register */ |
| 408 | u32 reserved_07[7]; |
| 409 | u32 paddr1; /* Physical address low */ |
| 410 | u32 paddr2; /* Physical address high + type field */ |
| 411 | u32 op_pause; /* Opcode + pause duration */ |
| 412 | u32 reserved_08[10]; |
| 413 | u32 iaddr1; /* Upper 32 bits of individual hash table */ |
| 414 | u32 iaddr2; /* Lower 32 bits of individual hash table */ |
| 415 | u32 gaddr1; /* Upper 32 bits of group hash table */ |
| 416 | u32 gaddr2; /* Lower 32 bits of group hash table */ |
| 417 | u32 reserved_09[7]; |
| 418 | u32 x_wmrk; /* Transmit FIFO watermark */ |
| 419 | u32 reserved_10; |
| 420 | u32 r_bound; /* End of RAM */ |
| 421 | u32 r_fstart; /* Receive FIFO start address */ |
| 422 | u32 reserved_11[11]; |
| 423 | u32 r_des_start; /* Beginning of receive descriptor ring */ |
| 424 | u32 x_des_start; /* Pointer to beginning of transmit descriptor ring */ |
| 425 | u32 r_buff_size; /* Receive buffer size */ |
| 426 | u32 reserved_12[26]; |
| 427 | u32 dma_control; /* DMA control for IP bus, AMBA IF + DMA revision */ |
| 428 | u32 reserved_13[2]; |
| 429 | |
| 430 | u32 mib[128]; /* MIB Block Counters */ |
| 431 | |
| 432 | u32 fifo[256]; /* used by FEC, can only be accessed by DMA */ |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 433 | } fec512x_t; |
| 434 | |
| 435 | /* |
| 436 | * ULPI |
| 437 | */ |
| 438 | typedef struct ulpi512x { |
| 439 | u8 fixme[0x600]; |
| 440 | } ulpi512x_t; |
| 441 | |
| 442 | /* |
| 443 | * UTMI |
| 444 | */ |
| 445 | typedef struct utmi512x { |
| 446 | u8 fixme[0x3000]; |
| 447 | } utmi512x_t; |
| 448 | |
| 449 | /* |
| 450 | * PCI DMA |
| 451 | */ |
| 452 | typedef struct pcidma512x { |
| 453 | u8 fixme[0x300]; |
| 454 | } pcidma512x_t; |
| 455 | |
| 456 | /* |
| 457 | * IO Control |
| 458 | */ |
| 459 | typedef struct ioctrl512x { |
Wolfgang Denk | 19dc7e1 | 2009-05-16 10:47:42 +0200 | [diff] [blame^] | 460 | u32 io_control_mem; /* MEM pad ctrl reg */ |
| 461 | u32 io_control_gp; /* GP pad ctrl reg */ |
| 462 | u32 io_control_lpc_clk; /* LPC_CLK pad ctrl reg */ |
| 463 | u32 io_control_lpc_oe; /* LPC_OE pad ctrl reg */ |
| 464 | u32 io_control_lpc_rw; /* LPC_R/W pad ctrl reg */ |
| 465 | u32 io_control_lpc_ack; /* LPC_ACK pad ctrl reg */ |
| 466 | u32 io_control_lpc_cs0; /* LPC_CS0 pad ctrl reg */ |
| 467 | u32 io_control_nfc_ce0; /* NFC_CE0 pad ctrl reg */ |
| 468 | u32 io_control_lpc_cs1; /* LPC_CS1 pad ctrl reg */ |
| 469 | u32 io_control_lpc_cs2; /* LPC_CS2 pad ctrl reg */ |
| 470 | u32 io_control_lpc_ax03; /* LPC_AX03 pad ctrl reg */ |
| 471 | u32 io_control_emb_ax02; /* EMB_AX02 pad ctrl reg */ |
| 472 | u32 io_control_emb_ax01; /* EMB_AX01 pad ctrl reg */ |
| 473 | u32 io_control_emb_ax00; /* EMB_AX00 pad ctrl reg */ |
| 474 | u32 io_control_emb_ad31; /* EMB_AD31 pad ctrl reg */ |
| 475 | u32 io_control_emb_ad30; /* EMB_AD30 pad ctrl reg */ |
| 476 | u32 io_control_emb_ad29; /* EMB_AD29 pad ctrl reg */ |
| 477 | u32 io_control_emb_ad28; /* EMB_AD28 pad ctrl reg */ |
| 478 | u32 io_control_emb_ad27; /* EMB_AD27 pad ctrl reg */ |
| 479 | u32 io_control_emb_ad26; /* EMB_AD26 pad ctrl reg */ |
| 480 | u32 io_control_emb_ad25; /* EMB_AD25 pad ctrl reg */ |
| 481 | u32 io_control_emb_ad24; /* EMB_AD24 pad ctrl reg */ |
| 482 | u32 io_control_emb_ad23; /* EMB_AD23 pad ctrl reg */ |
| 483 | u32 io_control_emb_ad22; /* EMB_AD22 pad ctrl reg */ |
| 484 | u32 io_control_emb_ad21; /* EMB_AD21 pad ctrl reg */ |
| 485 | u32 io_control_emb_ad20; /* EMB_AD20 pad ctrl reg */ |
| 486 | u32 io_control_emb_ad19; /* EMB_AD19 pad ctrl reg */ |
| 487 | u32 io_control_emb_ad18; /* EMB_AD18 pad ctrl reg */ |
| 488 | u32 io_control_emb_ad17; /* EMB_AD17 pad ctrl reg */ |
| 489 | u32 io_control_emb_ad16; /* EMB_AD16 pad ctrl reg */ |
| 490 | u32 io_control_emb_ad15; /* EMB_AD15 pad ctrl reg */ |
| 491 | u32 io_control_emb_ad14; /* EMB_AD14 pad ctrl reg */ |
| 492 | u32 io_control_emb_ad13; /* EMB_AD13 pad ctrl reg */ |
| 493 | u32 io_control_emb_ad12; /* EMB_AD12 pad ctrl reg */ |
| 494 | u32 io_control_emb_ad11; /* EMB_AD11 pad ctrl reg */ |
| 495 | u32 io_control_emb_ad10; /* EMB_AD10 pad ctrl reg */ |
| 496 | u32 io_control_emb_ad09; /* EMB_AD09 pad ctrl reg */ |
| 497 | u32 io_control_emb_ad08; /* EMB_AD08 pad ctrl reg */ |
| 498 | u32 io_control_emb_ad07; /* EMB_AD07 pad ctrl reg */ |
| 499 | u32 io_control_emb_ad06; /* EMB_AD06 pad ctrl reg */ |
| 500 | u32 io_control_emb_ad05; /* EMB_AD05 pad ctrl reg */ |
| 501 | u32 io_control_emb_ad04; /* EMB_AD04 pad ctrl reg */ |
| 502 | u32 io_control_emb_ad03; /* EMB_AD03 pad ctrl reg */ |
| 503 | u32 io_control_emb_ad02; /* EMB_AD02 pad ctrl reg */ |
| 504 | u32 io_control_emb_ad01; /* EMB_AD01 pad ctrl reg */ |
| 505 | u32 io_control_emb_ad00; /* EMB_AD00 pad ctrl reg */ |
| 506 | u32 io_control_pata_ce1; /* PATA_CE1 pad ctrl reg */ |
| 507 | u32 io_control_pata_ce2; /* PATA_CE2 pad ctrl reg */ |
| 508 | u32 io_control_pata_isolate; /* PATA_ISOLATE pad ctrl reg */ |
| 509 | u32 io_control_pata_ior; /* PATA_IOR pad ctrl reg */ |
| 510 | u32 io_control_pata_iow; /* PATA_IOW pad ctrl reg */ |
| 511 | u32 io_control_pata_iochrdy; /* PATA_IOCHRDY pad ctrl reg */ |
| 512 | u32 io_control_pata_intrq; /* PATA_INTRQ pad ctrl reg */ |
| 513 | u32 io_control_pata_drq; /* PATA_DRQ pad ctrl reg */ |
| 514 | u32 io_control_pata_dack; /* PATA_DACK pad ctrl reg */ |
| 515 | u32 io_control_nfc_wp; /* NFC_WP pad ctrl reg */ |
| 516 | u32 io_control_nfc_rb; /* NFC_RB pad ctrl reg */ |
| 517 | u32 io_control_nfc_ale; /* NFC_ALE pad ctrl reg */ |
| 518 | u32 io_control_nfc_cle; /* NFC_CLE pad ctrl reg */ |
| 519 | u32 io_control_nfc_we; /* NFC_WE pad ctrl reg */ |
| 520 | u32 io_control_nfc_re; /* NFC_RE pad ctrl reg */ |
| 521 | u32 io_control_pci_ad31; /* PCI_AD31 pad ctrl reg */ |
| 522 | u32 io_control_pci_ad30; /* PCI_AD30 pad ctrl reg */ |
| 523 | u32 io_control_pci_ad29; /* PCI_AD29 pad ctrl reg */ |
| 524 | u32 io_control_pci_ad28; /* PCI_AD28 pad ctrl reg */ |
| 525 | u32 io_control_pci_ad27; /* PCI_AD27 pad ctrl reg */ |
| 526 | u32 io_control_pci_ad26; /* PCI_AD26 pad ctrl reg */ |
| 527 | u32 io_control_pci_ad25; /* PCI_AD25 pad ctrl reg */ |
| 528 | u32 io_control_pci_ad24; /* PCI_AD24 pad ctrl reg */ |
| 529 | u32 io_control_pci_ad23; /* PCI_AD23 pad ctrl reg */ |
| 530 | u32 io_control_pci_ad22; /* PCI_AD22 pad ctrl reg */ |
| 531 | u32 io_control_pci_ad21; /* PCI_AD21 pad ctrl reg */ |
| 532 | u32 io_control_pci_ad20; /* PCI_AD20 pad ctrl reg */ |
| 533 | u32 io_control_pci_ad19; /* PCI_AD19 pad ctrl reg */ |
| 534 | u32 io_control_pci_ad18; /* PCI_AD18 pad ctrl reg */ |
| 535 | u32 io_control_pci_ad17; /* PCI_AD17 pad ctrl reg */ |
| 536 | u32 io_control_pci_ad16; /* PCI_AD16 pad ctrl reg */ |
| 537 | u32 io_control_pci_ad15; /* PCI_AD15 pad ctrl reg */ |
| 538 | u32 io_control_pci_ad14; /* PCI_AD14 pad ctrl reg */ |
| 539 | u32 io_control_pci_ad13; /* PCI_AD13 pad ctrl reg */ |
| 540 | u32 io_control_pci_ad12; /* PCI_AD12 pad ctrl reg */ |
| 541 | u32 io_control_pci_ad11; /* PCI_AD11 pad ctrl reg */ |
| 542 | u32 io_control_pci_ad10; /* PCI_AD10 pad ctrl reg */ |
| 543 | u32 io_control_pci_ad09; /* PCI_AD09 pad ctrl reg */ |
| 544 | u32 io_control_pci_ad08; /* PCI_AD08 pad ctrl reg */ |
| 545 | u32 io_control_pci_ad07; /* PCI_AD07 pad ctrl reg */ |
| 546 | u32 io_control_pci_ad06; /* PCI_AD06 pad ctrl reg */ |
| 547 | u32 io_control_pci_ad05; /* PCI_AD05 pad ctrl reg */ |
| 548 | u32 io_control_pci_ad04; /* PCI_AD04 pad ctrl reg */ |
| 549 | u32 io_control_pci_ad03; /* PCI_AD03 pad ctrl reg */ |
| 550 | u32 io_control_pci_ad02; /* PCI_AD02 pad ctrl reg */ |
| 551 | u32 io_control_pci_ad01; /* PCI_AD01 pad ctrl reg */ |
| 552 | u32 io_control_pci_ad00; /* PCI_AD00 pad ctrl reg */ |
| 553 | u32 io_control_pci_cbe0; /* PCI_CBE0 pad ctrl reg */ |
| 554 | u32 io_control_pci_cbe1; /* PCI_CBE1 pad ctrl reg */ |
| 555 | u32 io_control_pci_cbe2; /* PCI_CBE2 pad ctrl reg */ |
| 556 | u32 io_control_pci_cbe3; /* PCI_CBE3 pad ctrl reg */ |
| 557 | u32 io_control_pci_grant2; /* PCI_GRANT2 pad ctrl reg */ |
| 558 | u32 io_control_pci_req2; /* PCI_REQ2 pad ctrl reg */ |
| 559 | u32 io_control_pci_grant1; /* PCI_GRANT1 pad ctrl reg */ |
| 560 | u32 io_control_pci_req1; /* PCI_REQ1 pad ctrl reg */ |
| 561 | u32 io_control_pci_grant0; /* PCI_GRANT0 pad ctrl reg */ |
| 562 | u32 io_control_pci_req0; /* PCI_REQ0 pad ctrl reg */ |
| 563 | u32 io_control_pci_inta; /* PCI_INTA pad ctrl reg */ |
| 564 | u32 io_control_pci_clk; /* PCI_CLK pad ctrl reg */ |
| 565 | u32 io_control_pci_rst; /* PCI_RST- pad ctrl reg */ |
| 566 | u32 io_control_pci_frame; /* PCI_FRAME pad ctrl reg */ |
| 567 | u32 io_control_pci_idsel; /* PCI_IDSEL pad ctrl reg */ |
| 568 | u32 io_control_pci_devsel; /* PCI_DEVSEL pad ctrl reg */ |
| 569 | u32 io_control_pci_irdy; /* PCI_IRDY pad ctrl reg */ |
| 570 | u32 io_control_pci_trdy; /* PCI_TRDY pad ctrl reg */ |
| 571 | u32 io_control_pci_stop; /* PCI_STOP pad ctrl reg */ |
| 572 | u32 io_control_pci_par; /* PCI_PAR pad ctrl reg */ |
| 573 | u32 io_control_pci_perr; /* PCI_PERR pad ctrl reg */ |
| 574 | u32 io_control_pci_serr; /* PCI_SERR pad ctrl reg */ |
| 575 | u32 io_control_spdif_txclk; /* SPDIF_TXCLK pad ctrl reg */ |
| 576 | u32 io_control_spdif_tx; /* SPDIF_TX pad ctrl reg */ |
| 577 | u32 io_control_spdif_rx; /* SPDIF_RX pad ctrl reg */ |
| 578 | u32 io_control_i2c0_scl; /* I2C0_SCL pad ctrl reg */ |
| 579 | u32 io_control_i2c0_sda; /* I2C0_SDA pad ctrl reg */ |
| 580 | u32 io_control_i2c1_scl; /* I2C1_SCL pad ctrl reg */ |
| 581 | u32 io_control_i2c1_sda; /* I2C1_SDA pad ctrl reg */ |
| 582 | u32 io_control_i2c2_scl; /* I2C2_SCL pad ctrl reg */ |
| 583 | u32 io_control_i2c2_sda; /* I2C2_SDA pad ctrl reg */ |
| 584 | u32 io_control_irq0; /* IRQ0 pad ctrl reg */ |
| 585 | u32 io_control_irq1; /* IRQ1 pad ctrl reg */ |
| 586 | u32 io_control_can1_tx; /* CAN1_TX pad ctrl reg */ |
| 587 | u32 io_control_can2_tx; /* CAN2_TX pad ctrl reg */ |
| 588 | u32 io_control_j1850_tx; /* J1850_TX pad ctrl reg */ |
| 589 | u32 io_control_j1850_rx; /* J1850_RX pad ctrl reg */ |
| 590 | u32 io_control_psc_mclk_in; /* PSC_MCLK_IN pad ctrl reg */ |
| 591 | u32 io_control_psc0_0; /* PSC0_0 pad ctrl reg */ |
| 592 | u32 io_control_psc0_1; /* PSC0_1 pad ctrl reg */ |
| 593 | u32 io_control_psc0_2; /* PSC0_2 pad ctrl reg */ |
| 594 | u32 io_control_psc0_3; /* PSC0_3 pad ctrl reg */ |
| 595 | u32 io_control_psc0_4; /* PSC0_4 pad ctrl reg */ |
| 596 | u32 io_control_psc1_0; /* PSC1_0 pad ctrl reg */ |
| 597 | u32 io_control_psc1_1; /* PSC1_1 pad ctrl reg */ |
| 598 | u32 io_control_psc1_2; /* PSC1_2 pad ctrl reg */ |
| 599 | u32 io_control_psc1_3; /* PSC1_3 pad ctrl reg */ |
| 600 | u32 io_control_psc1_4; /* PSC1_4 pad ctrl reg */ |
| 601 | u32 io_control_psc2_0; /* PSC2_0 pad ctrl reg */ |
| 602 | u32 io_control_psc2_1; /* PSC2_1 pad ctrl reg */ |
| 603 | u32 io_control_psc2_2; /* PSC2_2 pad ctrl reg */ |
| 604 | u32 io_control_psc2_3; /* PSC2_3 pad ctrl reg */ |
| 605 | u32 io_control_psc2_4; /* PSC2_4 pad ctrl reg */ |
| 606 | u32 io_control_psc3_0; /* PSC3_0 pad ctrl reg */ |
| 607 | u32 io_control_psc3_1; /* PSC3_1 pad ctrl reg */ |
| 608 | u32 io_control_psc3_2; /* PSC3_2 pad ctrl reg */ |
| 609 | u32 io_control_psc3_3; /* PSC3_3 pad ctrl reg */ |
| 610 | u32 io_control_psc3_4; /* PSC3_4 pad ctrl reg */ |
| 611 | u32 io_control_psc4_0; /* PSC4_0 pad ctrl reg */ |
| 612 | u32 io_control_psc4_1; /* PSC4_1 pad ctrl reg */ |
| 613 | u32 io_control_psc4_2; /* PSC4_2 pad ctrl reg */ |
| 614 | u32 io_control_psc4_3; /* PSC4_3 pad ctrl reg */ |
| 615 | u32 io_control_psc4_4; /* PSC4_4 pad ctrl reg */ |
| 616 | u32 io_control_psc5_0; /* PSC5_0 pad ctrl reg */ |
| 617 | u32 io_control_psc5_1; /* PSC5_1 pad ctrl reg */ |
| 618 | u32 io_control_psc5_2; /* PSC5_2 pad ctrl reg */ |
| 619 | u32 io_control_psc5_3; /* PSC5_3 pad ctrl reg */ |
| 620 | u32 io_control_psc5_4; /* PSC5_4 pad ctrl reg */ |
| 621 | u32 io_control_psc6_0; /* PSC6_0 pad ctrl reg */ |
| 622 | u32 io_control_psc6_1; /* PSC6_1 pad ctrl reg */ |
| 623 | u32 io_control_psc6_2; /* PSC6_2 pad ctrl reg */ |
| 624 | u32 io_control_psc6_3; /* PSC6_3 pad ctrl reg */ |
| 625 | u32 io_control_psc6_4; /* PSC6_4 pad ctrl reg */ |
| 626 | u32 io_control_psc7_0; /* PSC7_0 pad ctrl reg */ |
| 627 | u32 io_control_psc7_1; /* PSC7_1 pad ctrl reg */ |
| 628 | u32 io_control_psc7_2; /* PSC7_2 pad ctrl reg */ |
| 629 | u32 io_control_psc7_3; /* PSC7_3 pad ctrl reg */ |
| 630 | u32 io_control_psc7_4; /* PSC7_4 pad ctrl reg */ |
| 631 | u32 io_control_psc8_0; /* PSC8_0 pad ctrl reg */ |
| 632 | u32 io_control_psc8_1; /* PSC8_1 pad ctrl reg */ |
| 633 | u32 io_control_psc8_2; /* PSC8_2 pad ctrl reg */ |
| 634 | u32 io_control_psc8_3; /* PSC8_3 pad ctrl reg */ |
| 635 | u32 io_control_psc8_4; /* PSC8_4 pad ctrl reg */ |
| 636 | u32 io_control_psc9_0; /* PSC9_0 pad ctrl reg */ |
| 637 | u32 io_control_psc9_1; /* PSC9_1 pad ctrl reg */ |
| 638 | u32 io_control_psc9_2; /* PSC9_2 pad ctrl reg */ |
| 639 | u32 io_control_psc9_3; /* PSC9_3 pad ctrl reg */ |
| 640 | u32 io_control_psc9_4; /* PSC9_4 pad ctrl reg */ |
| 641 | u32 io_control_psc10_0; /* PSC10_0 pad ctrl reg */ |
| 642 | u32 io_control_psc10_1; /* PSC10_1 pad ctrl reg */ |
| 643 | u32 io_control_psc10_2; /* PSC10_2 pad ctrl reg */ |
| 644 | u32 io_control_psc10_3; /* PSC10_3 pad ctrl reg */ |
| 645 | u32 io_control_psc10_4; /* PSC10_4 pad ctrl reg */ |
| 646 | u32 io_control_psc11_0; /* PSC11_0 pad ctrl reg */ |
| 647 | u32 io_control_psc11_1; /* PSC11_1 pad ctrl reg */ |
| 648 | u32 io_control_psc11_2; /* PSC11_2 pad ctrl reg */ |
| 649 | u32 io_control_psc11_3; /* PSC11_3 pad ctrl reg */ |
| 650 | u32 io_control_psc11_4; /* PSC11_4 pad ctrl reg */ |
| 651 | u32 io_control_ckstp_out; /* CKSTP_OUT pad ctrl reg */ |
| 652 | u32 io_control_usb_phy_drvvbus; /* USB2_DRVVBUS pad ctrl reg */ |
| 653 | u8 reserved[0x0cfc]; /* fill to 4096 bytes size */ |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 654 | } ioctrl512x_t; |
| 655 | |
| 656 | /* |
| 657 | * IIM |
| 658 | */ |
| 659 | typedef struct iim512x { |
Martha Marx | abfbd0ae | 2009-01-26 10:45:07 -0700 | [diff] [blame] | 660 | u32 stat; /* IIM status register */ |
| 661 | u32 statm; /* IIM status IRQ mask */ |
| 662 | u32 err; /* IIM errors register */ |
| 663 | u32 emask; /* IIM error IRQ mask */ |
| 664 | u32 fctl; /* IIM fuse control register */ |
| 665 | u32 ua; /* IIM upper address register */ |
| 666 | u32 la; /* IIM lower address register */ |
| 667 | u32 sdat; /* IIM explicit sense data */ |
| 668 | u8 res0[0x08]; |
| 669 | u32 prg_p; /* IIM program protection register */ |
| 670 | u8 res1[0x10]; |
| 671 | u32 divide; /* IIM divide factor register */ |
| 672 | u8 res2[0x7c0]; |
| 673 | u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ |
| 674 | u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ |
| 675 | u8 res3[0x380]; |
| 676 | u32 fbac1; /* IIM fuse bank 1 protection */ |
| 677 | u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ |
| 678 | u8 res4[0x380]; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 679 | } iim512x_t; |
| 680 | |
| 681 | /* |
| 682 | * LPC |
| 683 | */ |
| 684 | typedef struct lpc512x { |
| 685 | u32 cs_cfg[8]; /* Chip Select N Configuration Registers |
| 686 | No dedicated entry for CS Boot as == CS0 */ |
| 687 | u32 cs_cr; /* Chip Select Control Register */ |
| 688 | u32 cs_sr; /* Chip Select Status Register */ |
| 689 | u32 cs_bcr; /* Chip Select Burst Control Register */ |
| 690 | u32 cs_dccr; /* Chip Select Deadcycle Control Register */ |
| 691 | u32 cs_hccr; /* Chip Select Holdcycle Control Register */ |
Wolfgang Denk | 19dc7e1 | 2009-05-16 10:47:42 +0200 | [diff] [blame^] | 692 | u32 altr; /* Address Latch Timing Register */ |
| 693 | u8 res0[0xc8]; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 694 | u32 sclpc_psr; /* SCLPC Packet Size Register */ |
| 695 | u32 sclpc_sar; /* SCLPC Start Address Register */ |
| 696 | u32 sclpc_cr; /* SCLPC Control Register */ |
| 697 | u32 sclpc_er; /* SCLPC Enable Register */ |
| 698 | u32 sclpc_nar; /* SCLPC NextAddress Register */ |
| 699 | u32 sclpc_sr; /* SCLPC Status Register */ |
| 700 | u32 sclpc_bdr; /* SCLPC Bytes Done Register */ |
| 701 | u32 emb_scr; /* EMB Share Counter Register */ |
| 702 | u32 emb_pcr; /* EMB Pause Control Register */ |
| 703 | u8 res1[0x1c]; |
| 704 | u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */ |
| 705 | u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */ |
| 706 | u32 lpc_cr; /* LPC RX/TX FIFO Control Register */ |
| 707 | u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */ |
| 708 | u8 res2[0xb0]; |
| 709 | } lpc512x_t; |
| 710 | |
| 711 | /* |
| 712 | * PATA |
| 713 | */ |
| 714 | typedef struct pata512x { |
Ralph Kondziella | 70a4da4 | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 715 | /* LOCAL Registers */ |
| 716 | u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ |
| 717 | u32 pata_time2; /* Time register 2: PIO timing parameter */ |
| 718 | u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ |
| 719 | u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ |
| 720 | u32 pata_time5; /* Time register 5: UDMA timing parameter */ |
| 721 | u32 pata_time6; /* Time register 6: UDMA timing parameter */ |
| 722 | u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ |
| 723 | u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ |
| 724 | u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ |
| 725 | u32 pata_ata_control; /* ATA Interface control register */ |
| 726 | u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ |
| 727 | u32 pata_irq_enable; /* Interrupt enable register */ |
| 728 | u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ |
| 729 | u32 pata_fifo_alarm; /* fifo alarm threshold */ |
| 730 | u32 res1[0x1A]; |
| 731 | /* DRIVE Registers */ |
| 732 | u32 pata_drive_data; /* drive data register*/ |
| 733 | u32 pata_drive_features;/* drive features register */ |
| 734 | u32 pata_drive_sectcnt; /* drive sector count register */ |
| 735 | u32 pata_drive_sectnum; /* drive sector number register */ |
| 736 | u32 pata_drive_cyllow; /* drive cylinder low register */ |
| 737 | u32 pata_drive_cylhigh; /* drive cylinder high register */ |
| 738 | u32 pata_drive_dev_head;/* drive device head register */ |
| 739 | u32 pata_drive_command; /* write = drive command, read = drive status reg */ |
| 740 | u32 res2[0x06]; |
| 741 | u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ |
| 742 | u32 res3[0x09]; |
Rafal Jaworowski | 8993e54 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 743 | } pata512x_t; |
| 744 | |
| 745 | /* |
| 746 | * PSC |
| 747 | */ |
| 748 | typedef struct psc512x { |
| 749 | volatile u8 mode; /* PSC + 0x00 */ |
| 750 | volatile u8 res0[3]; |
| 751 | union { /* PSC + 0x04 */ |
| 752 | volatile u16 status; |
| 753 | volatile u16 clock_select; |
| 754 | } sr_csr; |
| 755 | #define psc_status sr_csr.status |
| 756 | #define psc_clock_select sr_csr.clock_select |
| 757 | volatile u16 res1; |
| 758 | volatile u8 command; /* PSC + 0x08 */ |
| 759 | volatile u8 res2[3]; |
| 760 | union { /* PSC + 0x0c */ |
| 761 | volatile u8 buffer_8; |
| 762 | volatile u16 buffer_16; |
| 763 | volatile u32 buffer_32; |
| 764 | } buffer; |
| 765 | #define psc_buffer_8 buffer.buffer_8 |
| 766 | #define psc_buffer_16 buffer.buffer_16 |
| 767 | #define psc_buffer_32 buffer.buffer_32 |
| 768 | union { /* PSC + 0x10 */ |
| 769 | volatile u8 ipcr; |
| 770 | volatile u8 acr; |
| 771 | } ipcr_acr; |
| 772 | #define psc_ipcr ipcr_acr.ipcr |
| 773 | #define psc_acr ipcr_acr.acr |
| 774 | volatile u8 res3[3]; |
| 775 | union { /* PSC + 0x14 */ |
| 776 | volatile u16 isr; |
| 777 | volatile u16 imr; |
| 778 | } isr_imr; |
| 779 | #define psc_isr isr_imr.isr |
| 780 | #define psc_imr isr_imr.imr |
| 781 | volatile u16 res4; |
| 782 | volatile u8 ctur; /* PSC + 0x18 */ |
| 783 | volatile u8 res5[3]; |
| 784 | volatile u8 ctlr; /* PSC + 0x1c */ |
| 785 | volatile u8 res6[3]; |
| 786 | volatile u32 ccr; /* PSC + 0x20 */ |
| 787 | volatile u8 res7[12]; |
| 788 | volatile u8 ivr; /* PSC + 0x30 */ |
| 789 | volatile u8 res8[3]; |
| 790 | volatile u8 ip; /* PSC + 0x34 */ |
| 791 | volatile u8 res9[3]; |
| 792 | volatile u8 op1; /* PSC + 0x38 */ |
| 793 | volatile u8 res10[3]; |
| 794 | volatile u8 op0; /* PSC + 0x3c */ |
| 795 | volatile u8 res11[3]; |
| 796 | volatile u32 sicr; /* PSC + 0x40 */ |
| 797 | volatile u8 res12[60]; |
| 798 | volatile u32 tfcmd; /* PSC + 0x80 */ |
| 799 | volatile u32 tfalarm; /* PSC + 0x84 */ |
| 800 | volatile u32 tfstat; /* PSC + 0x88 */ |
| 801 | volatile u32 tfintstat; /* PSC + 0x8C */ |
| 802 | volatile u32 tfintmask; /* PSC + 0x90 */ |
| 803 | volatile u32 tfcount; /* PSC + 0x94 */ |
| 804 | volatile u16 tfwptr; /* PSC + 0x98 */ |
| 805 | volatile u16 tfrptr; /* PSC + 0x9A */ |
| 806 | volatile u32 tfsize; /* PSC + 0x9C */ |
| 807 | volatile u8 res13[28]; |
| 808 | union { /* PSC + 0xBC */ |
| 809 | volatile u8 buffer_8; |
| 810 | volatile u16 buffer_16; |
| 811 | volatile u32 buffer_32; |
| 812 | } tfdata_buffer; |
| 813 | #define tfdata_8 tfdata_buffer.buffer_8 |
| 814 | #define tfdata_16 tfdata_buffer.buffer_16 |
| 815 | #define tfdata_32 tfdata_buffer.buffer_32 |
| 816 | |
| 817 | volatile u32 rfcmd; /* PSC + 0xC0 */ |
| 818 | volatile u32 rfalarm; /* PSC + 0xC4 */ |
| 819 | volatile u32 rfstat; /* PSC + 0xC8 */ |
| 820 | volatile u32 rfintstat; /* PSC + 0xCC */ |
| 821 | volatile u32 rfintmask; /* PSC + 0xD0 */ |
| 822 | volatile u32 rfcount; /* PSC + 0xD4 */ |
| 823 | volatile u16 rfwptr; /* PSC + 0xD8 */ |
| 824 | volatile u16 rfrptr; /* PSC + 0xDA */ |
| 825 | volatile u32 rfsize; /* PSC + 0xDC */ |
| 826 | volatile u8 res18[28]; |
| 827 | union { /* PSC + 0xFC */ |
| 828 | volatile u8 buffer_8; |
| 829 | volatile u16 buffer_16; |
| 830 | volatile u32 buffer_32; |
| 831 | } rfdata_buffer; |
| 832 | #define rfdata_8 rfdata_buffer.buffer_8 |
| 833 | #define rfdata_16 rfdata_buffer.buffer_16 |
| 834 | #define rfdata_32 rfdata_buffer.buffer_32 |
| 835 | } psc512x_t; |
| 836 | |
| 837 | /* |
| 838 | * FIFOC |
| 839 | */ |
| 840 | typedef struct fifoc512x { |
| 841 | u32 fifoc_cmd; |
| 842 | u32 fifoc_int; |
| 843 | u32 fifoc_dma; |
| 844 | u32 fifoc_axe; |
| 845 | u32 fifoc_debug; |
| 846 | u8 fixme[0xEC]; |
| 847 | } fifoc512x_t; |
| 848 | |
| 849 | /* |
| 850 | * SATA |
| 851 | */ |
| 852 | typedef struct sata512x { |
| 853 | u8 fixme[0x2000]; |
| 854 | } sata512x_t; |
| 855 | |
| 856 | typedef struct immap { |
| 857 | sysconf512x_t sysconf; /* System configuration */ |
| 858 | u8 res0[0x700]; |
| 859 | wdt512x_t wdt; /* Watch Dog Timer (WDT) */ |
| 860 | rtclk512x_t rtc; /* Real Time Clock Module */ |
| 861 | gpt512x_t gpt; /* General Purpose Timer */ |
| 862 | ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */ |
| 863 | arbiter512x_t arbiter; /* CSB Arbiter */ |
| 864 | reset512x_t reset; /* Reset Module */ |
| 865 | clk512x_t clk; /* Clock Module */ |
| 866 | pmc512x_t pmc; /* Power Management Control Module */ |
| 867 | gpio512x_t gpio; /* General purpose I/O module */ |
| 868 | u8 res1[0x100]; |
| 869 | mscan512x_t mscan; /* MSCAN */ |
| 870 | bdlc512x_t bdlc; /* BDLC */ |
| 871 | sdhc512x_t sdhc; /* SDHC */ |
| 872 | spdif512x_t spdif; /* SPDIF */ |
| 873 | i2c512x_t i2c; /* I2C Controllers */ |
| 874 | u8 res2[0x800]; |
| 875 | axe512x_t axe; /* AXE */ |
| 876 | diu512x_t diu; /* Display Interface Unit */ |
| 877 | cfm512x_t cfm; /* Clock Frequency Measurement */ |
| 878 | u8 res3[0x500]; |
| 879 | fec512x_t fec; /* Fast Ethernet Controller */ |
| 880 | ulpi512x_t ulpi; /* USB ULPI */ |
| 881 | u8 res4[0xa00]; |
| 882 | utmi512x_t utmi; /* USB UTMI */ |
| 883 | u8 res5[0x1000]; |
| 884 | pcidma512x_t pci_dma; /* PCI DMA */ |
| 885 | pciconf512x_t pci_conf; /* PCI Configuration */ |
| 886 | u8 res6[0x80]; |
| 887 | ios512x_t ios; /* PCI Sequencer */ |
| 888 | pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ |
| 889 | u8 res7[0xa00]; |
| 890 | ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ |
| 891 | ioctrl512x_t io_ctrl; /* IO Control */ |
| 892 | iim512x_t iim; /* IC Identification module */ |
| 893 | u8 res8[0x4000]; |
| 894 | lpc512x_t lpc; /* LocalPlus Controller */ |
| 895 | pata512x_t pata; /* Parallel ATA */ |
| 896 | u8 res9[0xd00]; |
| 897 | psc512x_t psc[12]; /* PSCs */ |
| 898 | u8 res10[0x300]; |
| 899 | fifoc512x_t fifoc; /* FIFO Controller */ |
| 900 | u8 res11[0x2000]; |
| 901 | dma512x_t dma; /* DMA */ |
| 902 | u8 res12[0xa800]; |
| 903 | sata512x_t sata; /* Serial ATA */ |
| 904 | u8 res13[0xde000]; |
| 905 | } immap_t; |
| 906 | #endif /* __IMMAP_512x__ */ |