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Amit Singh Tomara29710c2016-07-06 17:59:44 +05301/*
2 * (C) Copyright 2016
3 * Author: Amit Singh Tomar, amittomer25@gmail.com
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 *
7 * Ethernet driver for H3/A64/A83T based SoC's
8 *
9 * It is derived from the work done by
10 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
11 *
12*/
13
14#include <asm/io.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/gpio.h>
17#include <common.h>
18#include <dm.h>
19#include <fdt_support.h>
20#include <linux/err.h>
21#include <malloc.h>
22#include <miiphy.h>
23#include <net.h>
Andre Przywarac0341172018-04-04 01:31:15 +010024#include <dt-bindings/pinctrl/sun4i-a10.h>
Philipp Tomsich4d555ae2017-02-22 19:46:41 +010025#ifdef CONFIG_DM_GPIO
26#include <asm-generic/gpio.h>
27#endif
Amit Singh Tomara29710c2016-07-06 17:59:44 +053028
Amit Singh Tomara29710c2016-07-06 17:59:44 +053029#define MDIO_CMD_MII_BUSY BIT(0)
30#define MDIO_CMD_MII_WRITE BIT(1)
31
32#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
33#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
34#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
35#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
36
37#define CONFIG_TX_DESCR_NUM 32
38#define CONFIG_RX_DESCR_NUM 32
Hans de Goede40694372016-07-27 17:31:17 +020039#define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
40
41/*
42 * The datasheet says that each descriptor can transfers up to 4096 bytes
43 * But later, the register documentation reduces that value to 2048,
44 * using 2048 cause strange behaviours and even BSP driver use 2047
45 */
46#define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
Amit Singh Tomara29710c2016-07-06 17:59:44 +053047
48#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
49#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
50
51#define H3_EPHY_DEFAULT_VALUE 0x58000
52#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
53#define H3_EPHY_ADDR_SHIFT 20
54#define REG_PHY_ADDR_MASK GENMASK(4, 0)
55#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
56#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
57#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
58
59#define SC_RMII_EN BIT(13)
60#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
61#define SC_ETCS_MASK GENMASK(1, 0)
62#define SC_ETCS_EXT_GMII 0x1
63#define SC_ETCS_INT_GMII 0x2
64
65#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
66
67#define AHB_GATE_OFFSET_EPHY 0
68
Andre Przywara7b82a222017-02-16 01:20:27 +000069#if defined(CONFIG_MACH_SUNXI_H3_H5)
Amit Singh Tomara29710c2016-07-06 17:59:44 +053070#define SUN8I_GPD8_GMAC 2
71#else
72#define SUN8I_GPD8_GMAC 4
73#endif
74
75/* H3/A64 EMAC Register's offset */
76#define EMAC_CTL0 0x00
77#define EMAC_CTL1 0x04
78#define EMAC_INT_STA 0x08
79#define EMAC_INT_EN 0x0c
80#define EMAC_TX_CTL0 0x10
81#define EMAC_TX_CTL1 0x14
82#define EMAC_TX_FLOW_CTL 0x1c
83#define EMAC_TX_DMA_DESC 0x20
84#define EMAC_RX_CTL0 0x24
85#define EMAC_RX_CTL1 0x28
86#define EMAC_RX_DMA_DESC 0x34
87#define EMAC_MII_CMD 0x48
88#define EMAC_MII_DATA 0x4c
89#define EMAC_ADDR0_HIGH 0x50
90#define EMAC_ADDR0_LOW 0x54
91#define EMAC_TX_DMA_STA 0xb0
92#define EMAC_TX_CUR_DESC 0xb4
93#define EMAC_TX_CUR_BUF 0xb8
94#define EMAC_RX_DMA_STA 0xc0
95#define EMAC_RX_CUR_DESC 0xc4
96
97DECLARE_GLOBAL_DATA_PTR;
98
99enum emac_variant {
100 A83T_EMAC = 1,
101 H3_EMAC,
102 A64_EMAC,
103};
104
105struct emac_dma_desc {
106 u32 status;
107 u32 st;
108 u32 buf_addr;
109 u32 next;
110} __aligned(ARCH_DMA_MINALIGN);
111
112struct emac_eth_dev {
113 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
114 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
115 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
116 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
117
118 u32 interface;
119 u32 phyaddr;
120 u32 link;
121 u32 speed;
122 u32 duplex;
123 u32 phy_configured;
124 u32 tx_currdescnum;
125 u32 rx_currdescnum;
126 u32 addr;
127 u32 tx_slot;
128 bool use_internal_phy;
129
130 enum emac_variant variant;
131 void *mac_reg;
132 phys_addr_t sysctl_reg;
133 struct phy_device *phydev;
134 struct mii_dev *bus;
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100135#ifdef CONFIG_DM_GPIO
136 struct gpio_desc reset_gpio;
137#endif
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530138};
139
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100140
141struct sun8i_eth_pdata {
142 struct eth_pdata eth_pdata;
143 u32 reset_delays[3];
144};
145
146
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530147static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
148{
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100149 struct udevice *dev = bus->priv;
150 struct emac_eth_dev *priv = dev_get_priv(dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530151 ulong start;
152 u32 miiaddr = 0;
153 int timeout = CONFIG_MDIO_TIMEOUT;
154
155 miiaddr &= ~MDIO_CMD_MII_WRITE;
156 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
157 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
158 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
159
160 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
161
162 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
163 MDIO_CMD_MII_PHY_ADDR_MASK;
164
165 miiaddr |= MDIO_CMD_MII_BUSY;
166
167 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
168
169 start = get_timer(0);
170 while (get_timer(start) < timeout) {
171 if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
172 return readl(priv->mac_reg + EMAC_MII_DATA);
173 udelay(10);
174 };
175
176 return -1;
177}
178
179static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
180 u16 val)
181{
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100182 struct udevice *dev = bus->priv;
183 struct emac_eth_dev *priv = dev_get_priv(dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530184 ulong start;
185 u32 miiaddr = 0;
186 int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
187
188 miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
189 miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
190 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
191
192 miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
193 miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
194 MDIO_CMD_MII_PHY_ADDR_MASK;
195
196 miiaddr |= MDIO_CMD_MII_WRITE;
197 miiaddr |= MDIO_CMD_MII_BUSY;
198
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530199 writel(val, priv->mac_reg + EMAC_MII_DATA);
Philipp Tomsich1deeecb2016-11-16 01:40:27 +0000200 writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530201
202 start = get_timer(0);
203 while (get_timer(start) < timeout) {
204 if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
205 MDIO_CMD_MII_BUSY)) {
206 ret = 0;
207 break;
208 }
209 udelay(10);
210 };
211
212 return ret;
213}
214
215static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
216{
217 u32 macid_lo, macid_hi;
218
219 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
220 (mac_id[3] << 24);
221 macid_hi = mac_id[4] + (mac_id[5] << 8);
222
223 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
224 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
225
226 return 0;
227}
228
229static void sun8i_adjust_link(struct emac_eth_dev *priv,
230 struct phy_device *phydev)
231{
232 u32 v;
233
234 v = readl(priv->mac_reg + EMAC_CTL0);
235
236 if (phydev->duplex)
237 v |= BIT(0);
238 else
239 v &= ~BIT(0);
240
241 v &= ~0x0C;
242
243 switch (phydev->speed) {
244 case 1000:
245 break;
246 case 100:
247 v |= BIT(2);
248 v |= BIT(3);
249 break;
250 case 10:
251 v |= BIT(3);
252 break;
253 }
254 writel(v, priv->mac_reg + EMAC_CTL0);
255}
256
257static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
258{
259 if (priv->use_internal_phy) {
260 /* H3 based SoC's that has an Internal 100MBit PHY
261 * needs to be configured and powered up before use
262 */
263 *reg &= ~H3_EPHY_DEFAULT_MASK;
264 *reg |= H3_EPHY_DEFAULT_VALUE;
265 *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
266 *reg &= ~H3_EPHY_SHUTDOWN;
267 *reg |= H3_EPHY_SELECT;
268 } else
269 /* This is to select External Gigabit PHY on
270 * the boards with H3 SoC.
271 */
272 *reg &= ~H3_EPHY_SELECT;
273
274 return 0;
275}
276
277static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
278{
279 int ret;
280 u32 reg;
281
Andre Przywara12afd952018-04-04 01:31:16 +0100282 reg = readl(priv->sysctl_reg + 0x30);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530283
284 if (priv->variant == H3_EMAC) {
285 ret = sun8i_emac_set_syscon_ephy(priv, &reg);
286 if (ret)
287 return ret;
288 }
289
290 reg &= ~(SC_ETCS_MASK | SC_EPIT);
291 if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
292 reg &= ~SC_RMII_EN;
293
294 switch (priv->interface) {
295 case PHY_INTERFACE_MODE_MII:
296 /* default */
297 break;
298 case PHY_INTERFACE_MODE_RGMII:
299 reg |= SC_EPIT | SC_ETCS_INT_GMII;
300 break;
301 case PHY_INTERFACE_MODE_RMII:
302 if (priv->variant == H3_EMAC ||
303 priv->variant == A64_EMAC) {
304 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
305 break;
306 }
307 /* RMII not supported on A83T */
308 default:
309 debug("%s: Invalid PHY interface\n", __func__);
310 return -EINVAL;
311 }
312
Andre Przywara12afd952018-04-04 01:31:16 +0100313 writel(reg, priv->sysctl_reg + 0x30);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530314
315 return 0;
316}
317
318static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
319{
320 struct phy_device *phydev;
321
322 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
323 if (!phydev)
324 return -ENODEV;
325
326 phy_connect_dev(phydev, dev);
327
328 priv->phydev = phydev;
329 phy_config(priv->phydev);
330
331 return 0;
332}
333
334static void rx_descs_init(struct emac_eth_dev *priv)
335{
336 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
337 char *rxbuffs = &priv->rxbuffer[0];
338 struct emac_dma_desc *desc_p;
339 u32 idx;
340
341 /* flush Rx buffers */
342 flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
343 RX_TOTAL_BUFSIZE);
344
345 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
346 desc_p = &desc_table_p[idx];
347 desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
348 ;
349 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
Hans de Goede40694372016-07-27 17:31:17 +0200350 desc_p->st |= CONFIG_ETH_RXSIZE;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530351 desc_p->status = BIT(31);
352 }
353
354 /* Correcting the last pointer of the chain */
355 desc_p->next = (uintptr_t)&desc_table_p[0];
356
357 flush_dcache_range((uintptr_t)priv->rx_chain,
358 (uintptr_t)priv->rx_chain +
359 sizeof(priv->rx_chain));
360
361 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
362 priv->rx_currdescnum = 0;
363}
364
365static void tx_descs_init(struct emac_eth_dev *priv)
366{
367 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
368 char *txbuffs = &priv->txbuffer[0];
369 struct emac_dma_desc *desc_p;
370 u32 idx;
371
372 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
373 desc_p = &desc_table_p[idx];
374 desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
375 ;
376 desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
377 desc_p->status = (1 << 31);
378 desc_p->st = 0;
379 }
380
381 /* Correcting the last pointer of the chain */
382 desc_p->next = (uintptr_t)&desc_table_p[0];
383
384 /* Flush all Tx buffer descriptors */
385 flush_dcache_range((uintptr_t)priv->tx_chain,
386 (uintptr_t)priv->tx_chain +
387 sizeof(priv->tx_chain));
388
389 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
390 priv->tx_currdescnum = 0;
391}
392
393static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
394{
395 u32 reg, v;
396 int timeout = 100;
397
398 reg = readl((priv->mac_reg + EMAC_CTL1));
399
400 if (!(reg & 0x1)) {
401 /* Soft reset MAC */
402 setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
403 do {
404 reg = readl(priv->mac_reg + EMAC_CTL1);
405 } while ((reg & 0x01) != 0 && (--timeout));
406 if (!timeout) {
407 printf("%s: Timeout\n", __func__);
408 return -1;
409 }
410 }
411
412 /* Rewrite mac address after reset */
413 _sun8i_write_hwaddr(priv, enetaddr);
414
415 v = readl(priv->mac_reg + EMAC_TX_CTL1);
416 /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
417 v |= BIT(1);
418 writel(v, priv->mac_reg + EMAC_TX_CTL1);
419
420 v = readl(priv->mac_reg + EMAC_RX_CTL1);
421 /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
422 * complete frame has been written to RX DMA FIFO
423 */
424 v |= BIT(1);
425 writel(v, priv->mac_reg + EMAC_RX_CTL1);
426
427 /* DMA */
428 writel(8 << 24, priv->mac_reg + EMAC_CTL1);
429
430 /* Initialize rx/tx descriptors */
431 rx_descs_init(priv);
432 tx_descs_init(priv);
433
434 /* PHY Start Up */
Samuel Holland2d530182018-01-27 23:53:20 -0600435 phy_startup(priv->phydev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530436
437 sun8i_adjust_link(priv, priv->phydev);
438
439 /* Start RX DMA */
440 v = readl(priv->mac_reg + EMAC_RX_CTL1);
441 v |= BIT(30);
442 writel(v, priv->mac_reg + EMAC_RX_CTL1);
443 /* Start TX DMA */
444 v = readl(priv->mac_reg + EMAC_TX_CTL1);
445 v |= BIT(30);
446 writel(v, priv->mac_reg + EMAC_TX_CTL1);
447
448 /* Enable RX/TX */
449 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
450 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
451
452 return 0;
453}
454
455static int parse_phy_pins(struct udevice *dev)
456{
457 int offset;
458 const char *pin_name;
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100459 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530460
Simon Glasse160f7d2017-01-17 16:52:55 -0700461 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530462 "pinctrl-0");
463 if (offset < 0) {
464 printf("WARNING: emac: cannot find pinctrl-0 node\n");
465 return offset;
466 }
467
468 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
Andre Przywarac0341172018-04-04 01:31:15 +0100469 "drive-strength", ~0);
470 if (drive != ~0) {
471 if (drive <= 10)
472 drive = SUN4I_PINCTRL_10_MA;
473 else if (drive <= 20)
474 drive = SUN4I_PINCTRL_20_MA;
475 else if (drive <= 30)
476 drive = SUN4I_PINCTRL_30_MA;
477 else
478 drive = SUN4I_PINCTRL_40_MA;
Andre Przywarac0341172018-04-04 01:31:15 +0100479 }
480
481 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
482 pull = SUN4I_PINCTRL_PULL_UP;
Andre Przywarac0341172018-04-04 01:31:15 +0100483 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
484 pull = SUN4I_PINCTRL_PULL_DOWN;
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100485
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530486 for (i = 0; ; i++) {
487 int pin;
488
Simon Glassb02e4042016-10-02 17:59:28 -0600489 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100490 "pins", i, NULL);
491 if (!pin_name)
492 break;
Andre Przywarac0341172018-04-04 01:31:15 +0100493
494 pin = sunxi_name_to_gpio(pin_name);
495 if (pin < 0)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530496 continue;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530497
498 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
Andre Przywarac0341172018-04-04 01:31:15 +0100499 if (drive != ~0)
500 sunxi_gpio_set_drv(pin, drive);
501 if (pull != ~0)
502 sunxi_gpio_set_pull(pin, pull);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530503 }
504
505 if (!i) {
Andre Przywarac0341172018-04-04 01:31:15 +0100506 printf("WARNING: emac: cannot find pins property\n");
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530507 return -2;
508 }
509
510 return 0;
511}
512
513static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
514{
515 u32 status, desc_num = priv->rx_currdescnum;
516 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
517 int length = -EAGAIN;
518 int good_packet = 1;
519 uintptr_t desc_start = (uintptr_t)desc_p;
520 uintptr_t desc_end = desc_start +
521 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
522
523 ulong data_start = (uintptr_t)desc_p->buf_addr;
524 ulong data_end;
525
526 /* Invalidate entire buffer descriptor */
527 invalidate_dcache_range(desc_start, desc_end);
528
529 status = desc_p->status;
530
531 /* Check for DMA own bit */
532 if (!(status & BIT(31))) {
533 length = (desc_p->status >> 16) & 0x3FFF;
534
535 if (length < 0x40) {
536 good_packet = 0;
537 debug("RX: Bad Packet (runt)\n");
538 }
539
540 data_end = data_start + length;
541 /* Invalidate received data */
542 invalidate_dcache_range(rounddown(data_start,
543 ARCH_DMA_MINALIGN),
544 roundup(data_end,
545 ARCH_DMA_MINALIGN));
546 if (good_packet) {
Hans de Goede40694372016-07-27 17:31:17 +0200547 if (length > CONFIG_ETH_RXSIZE) {
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530548 printf("Received packet is too big (len=%d)\n",
549 length);
550 return -EMSGSIZE;
551 }
552 *packetp = (uchar *)(ulong)desc_p->buf_addr;
553 return length;
554 }
555 }
556
557 return length;
558}
559
560static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
561 int len)
562{
563 u32 v, desc_num = priv->tx_currdescnum;
564 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
565 uintptr_t desc_start = (uintptr_t)desc_p;
566 uintptr_t desc_end = desc_start +
567 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
568
569 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
570 uintptr_t data_end = data_start +
571 roundup(len, ARCH_DMA_MINALIGN);
572
573 /* Invalidate entire buffer descriptor */
574 invalidate_dcache_range(desc_start, desc_end);
575
576 desc_p->st = len;
577 /* Mandatory undocumented bit */
578 desc_p->st |= BIT(24);
579
580 memcpy((void *)data_start, packet, len);
581
582 /* Flush data to be sent */
583 flush_dcache_range(data_start, data_end);
584
585 /* frame end */
586 desc_p->st |= BIT(30);
587 desc_p->st |= BIT(31);
588
589 /*frame begin */
590 desc_p->st |= BIT(29);
591 desc_p->status = BIT(31);
592
593 /*Descriptors st and status field has changed, so FLUSH it */
594 flush_dcache_range(desc_start, desc_end);
595
596 /* Move to next Descriptor and wrap around */
597 if (++desc_num >= CONFIG_TX_DESCR_NUM)
598 desc_num = 0;
599 priv->tx_currdescnum = desc_num;
600
601 /* Start the DMA */
602 v = readl(priv->mac_reg + EMAC_TX_CTL1);
603 v |= BIT(31);/* mandatory */
604 v |= BIT(30);/* mandatory */
605 writel(v, priv->mac_reg + EMAC_TX_CTL1);
606
607 return 0;
608}
609
610static int sun8i_eth_write_hwaddr(struct udevice *dev)
611{
612 struct eth_pdata *pdata = dev_get_platdata(dev);
613 struct emac_eth_dev *priv = dev_get_priv(dev);
614
615 return _sun8i_write_hwaddr(priv, pdata->enetaddr);
616}
617
618static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
619{
620 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
621
Chen-Yu Tsai13ae2a42017-09-22 15:26:33 +0800622#ifdef CONFIG_MACH_SUNXI_H3_H5
623 /* Only H3/H5 have clock controls for internal EPHY */
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530624 if (priv->use_internal_phy) {
625 /* Set clock gating for ephy */
626 setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
627
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530628 /* Deassert EPHY */
629 setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
630 }
Chen-Yu Tsai13ae2a42017-09-22 15:26:33 +0800631#endif
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530632
633 /* Set clock gating for emac */
634 setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
635
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530636 /* De-assert EMAC */
637 setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
638}
639
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100640#if defined(CONFIG_DM_GPIO)
641static int sun8i_mdio_reset(struct mii_dev *bus)
642{
643 struct udevice *dev = bus->priv;
644 struct emac_eth_dev *priv = dev_get_priv(dev);
645 struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
646 int ret;
647
648 if (!dm_gpio_is_valid(&priv->reset_gpio))
649 return 0;
650
651 /* reset the phy */
652 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
653 if (ret)
654 return ret;
655
656 udelay(pdata->reset_delays[0]);
657
658 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
659 if (ret)
660 return ret;
661
662 udelay(pdata->reset_delays[1]);
663
664 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
665 if (ret)
666 return ret;
667
668 udelay(pdata->reset_delays[2]);
669
670 return 0;
671}
672#endif
673
674static int sun8i_mdio_init(const char *name, struct udevice *priv)
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530675{
676 struct mii_dev *bus = mdio_alloc();
677
678 if (!bus) {
679 debug("Failed to allocate MDIO bus\n");
680 return -ENOMEM;
681 }
682
683 bus->read = sun8i_mdio_read;
684 bus->write = sun8i_mdio_write;
685 snprintf(bus->name, sizeof(bus->name), name);
686 bus->priv = (void *)priv;
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100687#if defined(CONFIG_DM_GPIO)
688 bus->reset = sun8i_mdio_reset;
689#endif
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530690
691 return mdio_register(bus);
692}
693
694static int sun8i_emac_eth_start(struct udevice *dev)
695{
696 struct eth_pdata *pdata = dev_get_platdata(dev);
697
698 return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
699}
700
701static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
702{
703 struct emac_eth_dev *priv = dev_get_priv(dev);
704
705 return _sun8i_emac_eth_send(priv, packet, length);
706}
707
708static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
709{
710 struct emac_eth_dev *priv = dev_get_priv(dev);
711
712 return _sun8i_eth_recv(priv, packetp);
713}
714
715static int _sun8i_free_pkt(struct emac_eth_dev *priv)
716{
717 u32 desc_num = priv->rx_currdescnum;
718 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
719 uintptr_t desc_start = (uintptr_t)desc_p;
720 uintptr_t desc_end = desc_start +
721 roundup(sizeof(u32), ARCH_DMA_MINALIGN);
722
723 /* Make the current descriptor valid again */
724 desc_p->status |= BIT(31);
725
726 /* Flush Status field of descriptor */
727 flush_dcache_range(desc_start, desc_end);
728
729 /* Move to next desc and wrap-around condition. */
730 if (++desc_num >= CONFIG_RX_DESCR_NUM)
731 desc_num = 0;
732 priv->rx_currdescnum = desc_num;
733
734 return 0;
735}
736
737static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
738 int length)
739{
740 struct emac_eth_dev *priv = dev_get_priv(dev);
741
742 return _sun8i_free_pkt(priv);
743}
744
745static void sun8i_emac_eth_stop(struct udevice *dev)
746{
747 struct emac_eth_dev *priv = dev_get_priv(dev);
748
749 /* Stop Rx/Tx transmitter */
750 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
751 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
752
753 /* Stop TX DMA */
754 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
755
756 phy_shutdown(priv->phydev);
757}
758
759static int sun8i_emac_eth_probe(struct udevice *dev)
760{
761 struct eth_pdata *pdata = dev_get_platdata(dev);
762 struct emac_eth_dev *priv = dev_get_priv(dev);
763
764 priv->mac_reg = (void *)pdata->iobase;
765
766 sun8i_emac_board_setup(priv);
Chen-Yu Tsaia85ba872016-07-22 18:16:10 +0800767 sun8i_emac_set_syscon(priv);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530768
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100769 sun8i_mdio_init(dev->name, dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530770 priv->bus = miiphy_get_dev_by_name(dev->name);
771
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530772 return sun8i_phy_init(priv, dev);
773}
774
775static const struct eth_ops sun8i_emac_eth_ops = {
776 .start = sun8i_emac_eth_start,
777 .write_hwaddr = sun8i_eth_write_hwaddr,
778 .send = sun8i_emac_eth_send,
779 .recv = sun8i_emac_eth_recv,
780 .free_pkt = sun8i_eth_free_pkt,
781 .stop = sun8i_emac_eth_stop,
782};
783
784static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
785{
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100786 struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
787 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530788 struct emac_eth_dev *priv = dev_get_priv(dev);
789 const char *phy_mode;
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100790 const fdt32_t *reg;
Simon Glasse160f7d2017-01-17 16:52:55 -0700791 int node = dev_of_offset(dev);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530792 int offset = 0;
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100793#ifdef CONFIG_DM_GPIO
794 int reset_flags = GPIOD_IS_OUT;
795 int ret = 0;
796#endif
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530797
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100798 pdata->iobase = devfdt_get_addr(dev);
Andre Przywara12afd952018-04-04 01:31:16 +0100799 if (pdata->iobase == FDT_ADDR_T_NONE) {
800 debug("%s: Cannot find MAC base address\n", __func__);
801 return -EINVAL;
802 }
803
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100804 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
805 if (offset < 0) {
806 debug("%s: cannot find syscon node\n", __func__);
807 return -EINVAL;
Andre Przywara12afd952018-04-04 01:31:16 +0100808 }
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100809 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
810 if (!reg) {
811 debug("%s: cannot find reg property in syscon node\n",
812 __func__);
813 return -EINVAL;
814 }
815 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
816 offset, reg);
Andre Przywara12afd952018-04-04 01:31:16 +0100817 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
818 debug("%s: Cannot find syscon base address\n", __func__);
819 return -EINVAL;
820 }
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530821
822 pdata->phy_interface = -1;
823 priv->phyaddr = -1;
824 priv->use_internal_phy = false;
825
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100826 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
Andre Przywara12afd952018-04-04 01:31:16 +0100827 if (offset < 0) {
828 debug("%s: Cannot find PHY address\n", __func__);
829 return -EINVAL;
830 }
831 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530832
Simon Glasse160f7d2017-01-17 16:52:55 -0700833 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530834
835 if (phy_mode)
836 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
837 printf("phy interface%d\n", pdata->phy_interface);
838
839 if (pdata->phy_interface == -1) {
840 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
841 return -EINVAL;
842 }
843
844 priv->variant = dev_get_driver_data(dev);
845
846 if (!priv->variant) {
847 printf("%s: Missing variant '%s'\n", __func__,
848 (char *)priv->variant);
849 return -EINVAL;
850 }
851
852 if (priv->variant == H3_EMAC) {
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100853 int parent = fdt_parent_offset(gd->fdt_blob, offset);
Andre Przywara12afd952018-04-04 01:31:16 +0100854
Andre Przywaraecd0cec2018-04-04 01:31:20 +0100855 if (parent >= 0 &&
856 !fdt_node_check_compatible(gd->fdt_blob, parent,
857 "allwinner,sun8i-h3-mdio-internal"))
858 priv->use_internal_phy = true;
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530859 }
860
861 priv->interface = pdata->phy_interface;
862
863 if (!priv->use_internal_phy)
864 parse_phy_pins(dev);
865
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100866#ifdef CONFIG_DM_GPIO
Simon Glassda409cc2017-05-17 17:18:09 -0600867 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100868 "snps,reset-active-low"))
869 reset_flags |= GPIOD_ACTIVE_LOW;
870
871 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
872 &priv->reset_gpio, reset_flags);
873
874 if (ret == 0) {
Simon Glassda409cc2017-05-17 17:18:09 -0600875 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100876 "snps,reset-delays-us",
877 sun8i_pdata->reset_delays, 3);
878 } else if (ret == -ENOENT) {
879 ret = 0;
880 }
881#endif
882
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530883 return 0;
884}
885
886static const struct udevice_id sun8i_emac_eth_ids[] = {
887 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
888 {.compatible = "allwinner,sun50i-a64-emac",
889 .data = (uintptr_t)A64_EMAC },
890 {.compatible = "allwinner,sun8i-a83t-emac",
891 .data = (uintptr_t)A83T_EMAC },
892 { }
893};
894
895U_BOOT_DRIVER(eth_sun8i_emac) = {
896 .name = "eth_sun8i_emac",
897 .id = UCLASS_ETH,
898 .of_match = sun8i_emac_eth_ids,
899 .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
900 .probe = sun8i_emac_eth_probe,
901 .ops = &sun8i_emac_eth_ops,
902 .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
Philipp Tomsich4d555ae2017-02-22 19:46:41 +0100903 .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
Amit Singh Tomara29710c2016-07-06 17:59:44 +0530904 .flags = DM_FLAG_ALLOC_PRIV_DMA,
905};