Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | 23c5d25 | 2014-10-24 15:31:26 +0200 | [diff] [blame] | 2 | * (C) Copyright 2000-2014 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2006 |
| 6 | * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de |
| 7 | * |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | /* |
| 12 | * board/config.h - configuration options, board specific |
| 13 | */ |
| 14 | |
| 15 | #ifndef __CONFIG_H |
| 16 | #define __CONFIG_H |
| 17 | |
| 18 | /* |
| 19 | * High Level Configuration Options |
| 20 | * (easy to change) |
| 21 | */ |
| 22 | |
| 23 | #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ |
| 24 | #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ |
Wolfgang Denk | 23c5d25 | 2014-10-24 15:31:26 +0200 | [diff] [blame] | 25 | #define CONFIG_DISPLAY_BOARDINFO |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 26 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 27 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
| 28 | |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 29 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 30 | #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ |
| 31 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ |
Jens Gehrlein | 22d1a56 | 2007-09-26 17:55:54 +0200 | [diff] [blame] | 32 | #define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 33 | /* (it will be used if there is no */ |
| 34 | /* 'cpuclk' variable with valid value) */ |
| 35 | |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 36 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
Wolfgang Denk | 3cb7a48 | 2009-07-28 22:13:52 +0200 | [diff] [blame] | 37 | #define CONFIG_SYS_SMC_RXBUFLEN 128 |
| 38 | #define CONFIG_SYS_MAXIDLE 10 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 39 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ |
| 40 | |
| 41 | #define CONFIG_BOOTCOUNT_LIMIT |
| 42 | |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 43 | |
| 44 | #define CONFIG_BOARD_TYPES 1 /* support board types */ |
| 45 | |
| 46 | #define CONFIG_PREBOOT "echo;" \ |
Wolfgang Denk | 32bf3d1 | 2008-03-03 12:16:44 +0100 | [diff] [blame] | 47 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 48 | "echo" |
| 49 | |
| 50 | #undef CONFIG_BOOTARGS |
| 51 | |
| 52 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 53 | "netdev=eth0\0" \ |
| 54 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 55 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 56 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 57 | "addip=setenv bootargs ${bootargs} " \ |
| 58 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 59 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 60 | "flash_nfs=run nfsargs addip;" \ |
| 61 | "bootm ${kernel_addr}\0" \ |
| 62 | "flash_self=run ramargs addip;" \ |
| 63 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 64 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ |
| 65 | "rootpath=/opt/eldk/ppc_8xx\0" \ |
Martin Krause | 11d9eec | 2007-09-26 17:55:56 +0200 | [diff] [blame] | 66 | "bootfile=/tftpboot/TQM885D/uImage\0" \ |
| 67 | "fdt_addr=400C0000\0" \ |
| 68 | "kernel_addr=40100000\0" \ |
| 69 | "ramdisk_addr=40280000\0" \ |
| 70 | "load=tftp 200000 ${u-boot}\0" \ |
| 71 | "update=protect off 40000000 +${filesize};" \ |
| 72 | "erase 40000000 +${filesize};" \ |
| 73 | "cp.b 200000 40000000 ${filesize};" \ |
| 74 | "protect on 40000000 +${filesize}\0" \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 75 | "" |
| 76 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 77 | |
| 78 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 80 | |
| 81 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 82 | |
| 83 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
| 84 | |
| 85 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
| 86 | |
| 87 | /* enable I2C and select the hardware/software driver */ |
Heiko Schocher | ea818db | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 88 | #define CONFIG_SYS_I2C |
| 89 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
| 90 | #define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ |
| 91 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 92 | /* |
| 93 | * Software (bit-bang) I2C driver configuration |
| 94 | */ |
| 95 | #define PB_SCL 0x00000020 /* PB 26 */ |
| 96 | #define PB_SDA 0x00000010 /* PB 27 */ |
| 97 | |
| 98 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
| 99 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) |
| 100 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) |
| 101 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) |
| 102 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ |
| 103 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
| 104 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
| 105 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
| 106 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 107 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 108 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ |
| 109 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ |
| 110 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 |
| 111 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 112 | |
| 113 | # define CONFIG_RTC_DS1337 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 114 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 115 | |
Jon Loeliger | 37d4bb7 | 2007-07-09 21:38:02 -0500 | [diff] [blame] | 116 | /* |
| 117 | * BOOTP options |
| 118 | */ |
| 119 | #define CONFIG_BOOTP_SUBNETMASK |
| 120 | #define CONFIG_BOOTP_GATEWAY |
| 121 | #define CONFIG_BOOTP_HOSTNAME |
| 122 | #define CONFIG_BOOTP_BOOTPATH |
| 123 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 124 | |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 125 | #define CONFIG_MAC_PARTITION |
| 126 | #define CONFIG_DOS_PARTITION |
| 127 | |
Martin Krause | 11d9eec | 2007-09-26 17:55:56 +0200 | [diff] [blame] | 128 | #undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 129 | |
| 130 | #define CONFIG_TIMESTAMP /* but print image timestmps */ |
| 131 | |
Jon Loeliger | 2694690 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 132 | /* |
| 133 | * Command line configuration. |
| 134 | */ |
Jon Loeliger | 2694690 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 135 | #define CONFIG_CMD_DATE |
Jon Loeliger | 2694690 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 136 | #define CONFIG_CMD_EEPROM |
Jon Loeliger | 2694690 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 137 | #define CONFIG_CMD_IDE |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * Miscellaneous configurable options |
| 141 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 142 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 143 | |
Wolfgang Denk | 2751a95 | 2006-10-28 02:29:14 +0200 | [diff] [blame] | 144 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 145 | |
Jon Loeliger | 2694690 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 146 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 147 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 148 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 149 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 150 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 151 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 152 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 153 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 154 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 155 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
| 156 | #define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ |
| 157 | #define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 158 | memory test.*/ |
| 159 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 160 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 161 | |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 162 | /* |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 163 | * Low Level Configuration Settings |
| 164 | * (address mappings, register initial values, etc.) |
| 165 | * You should know what you are doing if you make changes here. |
| 166 | */ |
| 167 | /*----------------------------------------------------------------------- |
| 168 | * Internal Memory Mapped Register |
| 169 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_IMMR 0xFFF00000 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 171 | |
| 172 | /*----------------------------------------------------------------------- |
| 173 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 174 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 175 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 176 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 178 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 179 | |
| 180 | /*----------------------------------------------------------------------- |
| 181 | * Start addresses for the final memory configuration |
| 182 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 184 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 185 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 186 | #define CONFIG_SYS_FLASH_BASE 0x40000000 |
| 187 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 188 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
| 189 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 190 | |
| 191 | /* |
| 192 | * For booting Linux, the board info and command line data |
| 193 | * have to be in the first 8 MB of memory, since this is |
| 194 | * the maximum mapped by the Linux kernel during initialization. |
| 195 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 196 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 197 | |
| 198 | /*----------------------------------------------------------------------- |
| 199 | * FLASH organization |
| 200 | */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 201 | |
Martin Krause | e318d9e | 2007-09-27 11:10:08 +0200 | [diff] [blame] | 202 | /* use CFI flash driver */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 203 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 204 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 205 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 206 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 207 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
| 208 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 209 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 210 | |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 211 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 212 | #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ |
| 213 | #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ |
| 214 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 215 | |
| 216 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 217 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) |
| 218 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 219 | |
| 220 | /*----------------------------------------------------------------------- |
| 221 | * Hardware Information Block |
| 222 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
| 224 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
| 225 | #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 226 | |
| 227 | /*----------------------------------------------------------------------- |
| 228 | * Cache Configuration |
| 229 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 230 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
Jon Loeliger | 2694690 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 231 | #if defined(CONFIG_CMD_KGDB) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 232 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 233 | #endif |
| 234 | |
| 235 | /*----------------------------------------------------------------------- |
| 236 | * SYPCR - System Protection Control 11-9 |
| 237 | * SYPCR can only be written once after reset! |
| 238 | *----------------------------------------------------------------------- |
| 239 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
| 240 | */ |
| 241 | #if defined(CONFIG_WATCHDOG) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 242 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 243 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
| 244 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 245 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 246 | #endif |
| 247 | |
| 248 | /*----------------------------------------------------------------------- |
| 249 | * SIUMCR - SIU Module Configuration 11-6 |
| 250 | *----------------------------------------------------------------------- |
| 251 | * PCMCIA config., multi-function pin tri-state |
| 252 | */ |
| 253 | #ifndef CONFIG_CAN_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 254 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 255 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 256 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 257 | #endif /* CONFIG_CAN_DRIVER */ |
| 258 | |
| 259 | /*----------------------------------------------------------------------- |
| 260 | * TBSCR - Time Base Status and Control 11-26 |
| 261 | *----------------------------------------------------------------------- |
| 262 | * Clear Reference Interrupt Status, Timebase freezing enabled |
| 263 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 264 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 265 | |
| 266 | /*----------------------------------------------------------------------- |
| 267 | * PISCR - Periodic Interrupt Status and Control 11-31 |
| 268 | *----------------------------------------------------------------------- |
| 269 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
| 270 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 271 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 272 | |
| 273 | /*----------------------------------------------------------------------- |
| 274 | * SCCR - System Clock and reset Control Register 15-27 |
| 275 | *----------------------------------------------------------------------- |
| 276 | * Set clock output, timebase and RTC source and divider, |
| 277 | * power management and some other internal clocks |
| 278 | */ |
| 279 | #define SCCR_MASK SCCR_EBDF11 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 280 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 281 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
| 282 | SCCR_DFALCD00) |
| 283 | |
| 284 | /*----------------------------------------------------------------------- |
| 285 | * PCMCIA stuff |
| 286 | *----------------------------------------------------------------------- |
| 287 | * |
| 288 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 289 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
| 290 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) |
| 291 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) |
| 292 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) |
| 293 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) |
| 294 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
| 295 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) |
| 296 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 297 | |
| 298 | /*----------------------------------------------------------------------- |
| 299 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
| 300 | *----------------------------------------------------------------------- |
| 301 | */ |
| 302 | |
Pavel Herrmann | 8d1165e11a | 2012-10-09 07:01:56 +0000 | [diff] [blame] | 303 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 304 | #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ |
| 305 | |
| 306 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
| 307 | #undef CONFIG_IDE_LED /* LED for ide not supported */ |
| 308 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ |
| 309 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 310 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
| 311 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 312 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 313 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 314 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 315 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 316 | |
| 317 | /* Offset for data I/O */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 318 | #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 319 | |
| 320 | /* Offset for normal register accesses */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 321 | #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 322 | |
| 323 | /* Offset for alternate registers */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 324 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 325 | |
| 326 | /*----------------------------------------------------------------------- |
| 327 | * |
| 328 | *----------------------------------------------------------------------- |
| 329 | * |
| 330 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 331 | #define CONFIG_SYS_DER 0 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 332 | |
| 333 | /* |
| 334 | * Init Memory Controller: |
| 335 | * |
| 336 | * BR0/1 and OR0/1 (FLASH) |
| 337 | */ |
| 338 | |
| 339 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
| 340 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
| 341 | |
| 342 | /* used to re-map FLASH both when starting from SRAM or FLASH: |
| 343 | * restrict access enough to keep SRAM working (if any) |
| 344 | * but not too much to meddle with FLASH accesses |
| 345 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 346 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
| 347 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 348 | |
| 349 | /* |
| 350 | * FLASH timing: Default value of OR0 after reset |
| 351 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 352 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 353 | OR_SCY_6_CLK | OR_TRLX) |
| 354 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 355 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 356 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
| 357 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 358 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 359 | #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP |
| 360 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
| 361 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 362 | |
| 363 | /* |
| 364 | * BR2/3 and OR2/3 (SDRAM) |
| 365 | * |
| 366 | */ |
| 367 | #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ |
| 368 | #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ |
| 369 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ |
| 370 | |
| 371 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 372 | #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 373 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 374 | #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) |
| 375 | #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 376 | |
| 377 | #ifndef CONFIG_CAN_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 378 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
| 379 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 380 | #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 381 | #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ |
| 382 | #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ |
| 383 | #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) |
| 384 | #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 385 | BR_PS_8 | BR_MS_UPMB | BR_V ) |
| 386 | #endif /* CONFIG_CAN_DRIVER */ |
| 387 | |
| 388 | /* |
| 389 | * 4096 Rows from SDRAM example configuration |
| 390 | * 1000 factor s -> ms |
| 391 | * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration |
| 392 | * 4 Number of refresh cycles per period |
| 393 | * 64 Refresh cycle in ms per number of rows |
| 394 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 395 | #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 396 | |
| 397 | /* |
Jens Gehrlein | 492c704 | 2007-09-27 14:54:46 +0200 | [diff] [blame] | 398 | * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) |
| 399 | * |
| 400 | * CPUclock(MHz) * 31.2 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 401 | * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 |
Jens Gehrlein | 492c704 | 2007-09-27 14:54:46 +0200 | [diff] [blame] | 402 | * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 |
| 403 | * |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 404 | * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us |
| 405 | * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us |
| 406 | * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us |
| 407 | * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us |
Jens Gehrlein | 492c704 | 2007-09-27 14:54:46 +0200 | [diff] [blame] | 408 | * |
| 409 | * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will |
| 410 | * be met also in the default configuration, i.e. if environment variable |
| 411 | * 'cpuclk' is not set. |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 412 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 413 | #define CONFIG_SYS_MAMR_PTA 128 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 414 | |
| 415 | /* |
Jens Gehrlein | 492c704 | 2007-09-27 14:54:46 +0200 | [diff] [blame] | 416 | * Memory Periodic Timer Prescaler Register (MPTPR) values. |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 417 | */ |
Jens Gehrlein | 492c704 | 2007-09-27 14:54:46 +0200 | [diff] [blame] | 418 | /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 419 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 |
Jens Gehrlein | 492c704 | 2007-09-27 14:54:46 +0200 | [diff] [blame] | 420 | /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 421 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 422 | |
| 423 | /* |
| 424 | * MAMR settings for SDRAM |
| 425 | */ |
| 426 | |
| 427 | /* 8 column SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 428 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 429 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
| 430 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 431 | /* 9 column SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 432 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 433 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
| 434 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 435 | /* 10 column SDRAM */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 436 | #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 437 | MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ |
| 438 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) |
| 439 | |
| 440 | /* |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 441 | * Network configuration |
| 442 | */ |
| 443 | #define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ |
| 444 | #define CONFIG_FEC_ENET /* enable ethernet on FEC */ |
| 445 | #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ |
| 446 | #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ |
| 447 | |
Jon Loeliger | 2694690 | 2007-07-04 22:30:50 -0500 | [diff] [blame] | 448 | #if defined(CONFIG_CMD_MII) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 449 | #define CONFIG_SYS_DISCOVER_PHY |
TsiChung Liew | 0f3ba7e | 2008-03-30 01:22:13 -0500 | [diff] [blame] | 450 | #define CONFIG_MII_INIT 1 |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 451 | #endif |
| 452 | |
| 453 | #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before |
| 454 | switching to another netwok (if the |
| 455 | tried network is unreachable) */ |
| 456 | |
Heiko Schocher | 48690d8 | 2010-07-20 17:45:02 +0200 | [diff] [blame] | 457 | #define CONFIG_ETHPRIME "SCC" |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 458 | |
Heiko Schocher | 7026ead | 2010-02-09 15:50:27 +0100 | [diff] [blame] | 459 | #define CONFIG_HWCONFIG 1 |
| 460 | |
Markus Klotzbuecher | 090eb73 | 2006-07-12 15:26:01 +0200 | [diff] [blame] | 461 | #endif /* __CONFIG_H */ |