| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 1 | /* |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 2 | * SPDX-License-Identifier: GPL-2.0+ |
| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 3 | */ |
| 4 | |
| Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 5 | #include <asm-offsets.h> |
| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 6 | #include <ppc_asm.tmpl> |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 7 | #include <asm/mmu.h> |
| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 8 | #include <config.h> |
| 9 | |
| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 10 | /************************************************************************** |
| 11 | * TLB TABLE |
| 12 | * |
| 13 | * This table is used by the cpu boot code to setup the initial tlb |
| 14 | * entries. Rather than make broad assumptions in the cpu source tree, |
| 15 | * this table lets each board set things up however they like. |
| 16 | * |
| 17 | * Pointer to the table is returned in r1 |
| 18 | * |
| 19 | *************************************************************************/ |
| 20 | |
| 21 | .section .bootpg,"ax" |
| 22 | .globl tlbtab |
| 23 | |
| 24 | tlbtab: |
| 25 | tlbtab_start |
| Stefan Roese | 8428638 | 2005-08-11 18:03:14 +0200 | [diff] [blame] | 26 | |
| 27 | /* |
| 28 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the |
| 29 | * speed up boot process. It is patched after relocation to enable SA_I |
| 30 | */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 31 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/) |
| Stefan Roese | 8428638 | 2005-08-11 18:03:14 +0200 | [diff] [blame] | 32 | |
| 33 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 34 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
| Stefan Roese | 8428638 | 2005-08-11 18:03:14 +0200 | [diff] [blame] | 35 | |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 36 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) |
| 37 | tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG ) |
| 38 | tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I ) |
| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 39 | |
| 40 | /* PCI */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 41 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG ) |
| 42 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG ) |
| 43 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG ) |
| 44 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG ) |
| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 45 | |
| 46 | /* USB 2.0 Device */ |
| Stefan Roese | cf6eb6d | 2010-04-14 13:57:18 +0200 | [diff] [blame] | 47 | tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG ) |
| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 48 | |
| 49 | tlbtab_end |