blob: 8d88bc03c014f3141b2df2b167fb39207ae55d9d [file] [log] [blame]
TsiChungLiew1a33ce62007-08-05 04:31:18 -05001/*
2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Alison Wangaa0d99f2012-03-26 21:49:05 +00005 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiew1a33ce62007-08-05 04:31:18 -05006 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew1a33ce62007-08-05 04:31:18 -05009 */
10
11#include <config.h>
12#include <common.h>
13#include <asm/io.h>
14#include <asm/immap.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
TsiChungLiewab77bc52007-08-15 15:39:17 -050018#if defined(CONFIG_CMD_NAND)
TsiChungLiew1a33ce62007-08-05 04:31:18 -050019#include <nand.h>
20#include <linux/mtd/mtd.h>
21
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020022#define SET_CLE 0x10
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020023#define SET_ALE 0x08
TsiChungLiew1a33ce62007-08-05 04:31:18 -050024
TsiChung Liewe4f69d12008-10-24 12:59:12 +000025static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
TsiChungLiew1a33ce62007-08-05 04:31:18 -050026{
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020027 struct nand_chip *this = mtdinfo->priv;
TsiChung Liewe4f69d12008-10-24 12:59:12 +000028 volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
TsiChungLiew1a33ce62007-08-05 04:31:18 -050029
William Juulcfa460a2007-10-31 13:53:06 +010030 if (ctrl & NAND_CTRL_CHANGE) {
TsiChung Liewe4f69d12008-10-24 12:59:12 +000031 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
32
33 IO_ADDR_W &= ~(SET_ALE | SET_CLE);
TsiChung Liewe4f69d12008-10-24 12:59:12 +000034
35 if (ctrl & NAND_NCE)
TsiChung Liew9017d932009-03-02 19:16:45 +000036 *nCE &= 0xFFFB;
37 else
TsiChung Liewe4f69d12008-10-24 12:59:12 +000038 *nCE |= 0x0004;
TsiChung Liew9017d932009-03-02 19:16:45 +000039
TsiChung Liewe4f69d12008-10-24 12:59:12 +000040 if (ctrl & NAND_CLE)
41 IO_ADDR_W |= SET_CLE;
42 if (ctrl & NAND_ALE)
43 IO_ADDR_W |= SET_ALE;
44
45 this->IO_ADDR_W = (void *)IO_ADDR_W;
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020046 }
William Juulcfa460a2007-10-31 13:53:06 +010047
48 if (cmd != NAND_CMD_NONE)
49 writeb(cmd, this->IO_ADDR_W);
TsiChungLiew1a33ce62007-08-05 04:31:18 -050050}
51
TsiChungLiew1a33ce62007-08-05 04:31:18 -050052int board_nand_init(struct nand_chip *nand)
53{
Alison Wangaa0d99f2012-03-26 21:49:05 +000054 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
TsiChungLiew1a33ce62007-08-05 04:31:18 -050055
TsiChung Liewe4f69d12008-10-24 12:59:12 +000056 /*
57 * set up pin configuration - enabled 2nd output buffer's signals
58 * (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
59 * to use nCE signal
60 */
Alison Wangaa0d99f2012-03-26 21:49:05 +000061 clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
62 setbits_8(&gpio->pddr_timer, 0x08);
63 setbits_8(&gpio->ppd_timer, 0x08);
64 out_8(&gpio->pclrr_timer, 0);
65 out_8(&gpio->podr_timer, 0);
TsiChungLiew1a33ce62007-08-05 04:31:18 -050066
TsiChung Liew9017d932009-03-02 19:16:45 +000067 nand->chip_delay = 60;
William Juulcfa460a2007-10-31 13:53:06 +010068 nand->ecc.mode = NAND_ECC_SOFT;
69 nand->cmd_ctrl = nand_hwcontrol;
TsiChungLiew1a33ce62007-08-05 04:31:18 -050070
Stefan Roese3ba4c2d2007-08-08 09:54:26 +020071 return 0;
TsiChungLiew1a33ce62007-08-05 04:31:18 -050072}
73#endif