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Jason Liu938080d2011-05-13 01:58:55 +00001/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 * Jason Liu <r64343@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jason Liu938080d2011-05-13 01:58:55 +00006 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/imx-regs.h>
Jason Liu938080d2011-05-13 01:58:55 +000011#include <asm/arch/sys_proto.h>
12#include <asm/arch/crm_regs.h>
Stefano Babicf92e4e62012-02-22 00:24:41 +000013#include <asm/arch/clock.h>
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000014#include <asm/arch/iomux-mx53.h>
Jason Liu938080d2011-05-13 01:58:55 +000015#include <asm/arch/clock.h>
16#include <asm/errno.h>
Vikram Narayanan30ea4be2012-11-10 02:32:46 +000017#include <asm/imx-common/mx5_video.h>
Jason Liu938080d2011-05-13 01:58:55 +000018#include <netdev.h>
19#include <i2c.h>
20#include <mmc.h>
21#include <fsl_esdhc.h>
Stefano Babic50410072011-08-21 10:59:33 +020022#include <asm/gpio.h>
Łukasz Majewskic7336812012-11-13 03:21:55 +000023#include <power/pmic.h>
Fabio Estevame7e33722012-04-30 08:12:04 +000024#include <dialog_pmic.h>
Fabio Estevam5b547f32012-05-07 10:25:59 +000025#include <fsl_pmic.h>
Fabio Estevamf714b0a2012-05-10 15:07:35 +000026#include <linux/fb.h>
27#include <ipu_pixfmt.h>
28
Fabio Estevam3ef0a312012-08-21 10:01:56 +000029#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
Jason Liu938080d2011-05-13 01:58:55 +000030
31DECLARE_GLOBAL_DATA_PTR;
32
Jason Liu938080d2011-05-13 01:58:55 +000033int dram_init(void)
34{
35 u32 size1, size2;
36
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +000037 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
38 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
Jason Liu938080d2011-05-13 01:58:55 +000039
40 gd->ram_size = size1 + size2;
41
42 return 0;
43}
44void dram_init_banksize(void)
45{
46 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
47 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
48
49 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
50 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
51}
52
Fabio Estevam54cd1de2012-05-08 03:40:49 +000053u32 get_board_rev(void)
54{
55 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
56 struct fuse_bank *bank = &iim->bank[0];
57 struct fuse_bank0_regs *fuse =
58 (struct fuse_bank0_regs *)bank->fuse_regs;
59
60 int rev = readl(&fuse->gp[6]);
61
Fabio Estevameae08eb2012-05-29 05:54:39 +000062 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
63 rev = 0;
64
Fabio Estevam54cd1de2012-05-08 03:40:49 +000065 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
66}
67
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000068#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
69 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
70
Jason Liu938080d2011-05-13 01:58:55 +000071static void setup_iomux_uart(void)
72{
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000073 static const iomux_v3_cfg_t uart_pads[] = {
74 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
75 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
76 };
Jason Liu938080d2011-05-13 01:58:55 +000077
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000078 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
Jason Liu938080d2011-05-13 01:58:55 +000079}
80
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +010081#ifdef CONFIG_USB_EHCI_MX5
Anatolij Gustschin60bae5e2011-12-12 01:25:46 +000082int board_ehci_hcd_init(int port)
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +010083{
Fabio Estevam6ecaee82012-05-07 10:42:57 +000084 /* request VBUS power enable pin, GPIO7_8 */
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000085 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
86 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
Anatolij Gustschin60bae5e2011-12-12 01:25:46 +000087 return 0;
Wolfgang Grandegger45cf6ad2011-11-11 14:03:37 +010088}
89#endif
90
Jason Liu938080d2011-05-13 01:58:55 +000091static void setup_iomux_fec(void)
92{
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +000093 static const iomux_v3_cfg_t fec_pads[] = {
94 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
95 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
96 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
97 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
98 PAD_CTL_HYS | PAD_CTL_PKE),
99 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
100 PAD_CTL_HYS | PAD_CTL_PKE),
101 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
102 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
103 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
104 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
105 PAD_CTL_HYS | PAD_CTL_PKE),
106 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
107 PAD_CTL_HYS | PAD_CTL_PKE),
108 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
109 PAD_CTL_HYS | PAD_CTL_PKE),
110 };
Jason Liu938080d2011-05-13 01:58:55 +0000111
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000112 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
Jason Liu938080d2011-05-13 01:58:55 +0000113}
114
115#ifdef CONFIG_FSL_ESDHC
116struct fsl_esdhc_cfg esdhc_cfg[2] = {
Benoît Thébaudeau16e43f32012-08-13 07:28:16 +0000117 {MMC_SDHC1_BASE_ADDR},
118 {MMC_SDHC3_BASE_ADDR},
Jason Liu938080d2011-05-13 01:58:55 +0000119};
120
Thierry Reding314284b2012-01-02 01:15:36 +0000121int board_mmc_getcd(struct mmc *mmc)
Jason Liu938080d2011-05-13 01:58:55 +0000122{
123 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
Thierry Reding314284b2012-01-02 01:15:36 +0000124 int ret;
Jason Liu938080d2011-05-13 01:58:55 +0000125
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000126 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530127 gpio_direction_input(IMX_GPIO_NR(3, 11));
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000128 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530129 gpio_direction_input(IMX_GPIO_NR(3, 13));
Fabio Estevam73128aa2011-11-15 05:51:29 +0000130
Jason Liu938080d2011-05-13 01:58:55 +0000131 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530132 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
Jason Liu938080d2011-05-13 01:58:55 +0000133 else
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530134 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
Jason Liu938080d2011-05-13 01:58:55 +0000135
Thierry Reding314284b2012-01-02 01:15:36 +0000136 return ret;
Jason Liu938080d2011-05-13 01:58:55 +0000137}
138
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000139#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
140 PAD_CTL_PUS_100K_UP)
141#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
142 PAD_CTL_DSE_HIGH)
143
Jason Liu938080d2011-05-13 01:58:55 +0000144int board_mmc_init(bd_t *bis)
145{
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000146 static const iomux_v3_cfg_t sd1_pads[] = {
147 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
148 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
149 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
150 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
151 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
152 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
153 MX53_PAD_EIM_DA13__GPIO3_13,
154 };
155
156 static const iomux_v3_cfg_t sd2_pads[] = {
157 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
158 SD_CMD_PAD_CTRL),
159 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
160 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
161 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
162 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
163 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
164 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
165 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
166 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
167 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
168 MX53_PAD_EIM_DA11__GPIO3_11,
169 };
170
Jason Liu938080d2011-05-13 01:58:55 +0000171 u32 index;
172 s32 status = 0;
173
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000174 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
175 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
176
Jason Liu938080d2011-05-13 01:58:55 +0000177 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
178 switch (index) {
179 case 0:
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000180 imx_iomux_v3_setup_multiple_pads(sd1_pads,
181 ARRAY_SIZE(sd1_pads));
Jason Liu938080d2011-05-13 01:58:55 +0000182 break;
183 case 1:
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000184 imx_iomux_v3_setup_multiple_pads(sd2_pads,
185 ARRAY_SIZE(sd2_pads));
Jason Liu938080d2011-05-13 01:58:55 +0000186 break;
187 default:
188 printf("Warning: you configured more ESDHC controller"
189 "(%d) as supported by the board(2)\n",
190 CONFIG_SYS_FSL_ESDHC_NUM);
191 return status;
192 }
193 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
194 }
195
196 return status;
197}
198#endif
199
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000200#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
201 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
202
Fabio Estevame7e33722012-04-30 08:12:04 +0000203static void setup_iomux_i2c(void)
204{
Benoît Thébaudeau721d0b02013-05-03 10:32:34 +0000205 static const iomux_v3_cfg_t i2c1_pads[] = {
206 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
207 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
208 };
209
210 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
Fabio Estevame7e33722012-04-30 08:12:04 +0000211}
212
213static int power_init(void)
214{
Fabio Estevam5b547f32012-05-07 10:25:59 +0000215 unsigned int val;
Fabio Estevam085e7282012-12-28 04:05:29 +0000216 int ret;
Fabio Estevame7e33722012-04-30 08:12:04 +0000217 struct pmic *p;
218
Fabio Estevam5b547f32012-05-07 10:25:59 +0000219 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
Fabio Estevamd2292512012-12-28 04:05:28 +0000220 ret = pmic_dialog_init(I2C_PMIC);
221 if (ret)
222 return ret;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000223
224 p = pmic_get("DIALOG_PMIC");
225 if (!p)
226 return -ENODEV;
Fabio Estevame7e33722012-04-30 08:12:04 +0000227
Fabio Estevam5b547f32012-05-07 10:25:59 +0000228 /* Set VDDA to 1.25V */
229 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
230 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
Fabio Estevam085e7282012-12-28 04:05:29 +0000231 if (ret) {
232 printf("Writing to BUCKCORE_REG failed: %d\n", ret);
233 return ret;
234 }
Fabio Estevame7e33722012-04-30 08:12:04 +0000235
Fabio Estevam085e7282012-12-28 04:05:29 +0000236 pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
Fabio Estevam5b547f32012-05-07 10:25:59 +0000237 val |= DA9052_SUPPLY_VBCOREGO;
Fabio Estevam085e7282012-12-28 04:05:29 +0000238 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
239 if (ret) {
240 printf("Writing to SUPPLY_REG failed: %d\n", ret);
241 return ret;
242 }
Fabio Estevame7e33722012-04-30 08:12:04 +0000243
Fabio Estevam5b547f32012-05-07 10:25:59 +0000244 /* Set Vcc peripheral to 1.30V */
Fabio Estevam085e7282012-12-28 04:05:29 +0000245 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
246 if (ret) {
247 printf("Writing to BUCKPRO_REG failed: %d\n", ret);
248 return ret;
249 }
250
251 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
252 if (ret) {
253 printf("Writing to SUPPLY_REG failed: %d\n", ret);
254 return ret;
255 }
256
257 return ret;
Fabio Estevam5b547f32012-05-07 10:25:59 +0000258 }
259
260 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
Fabio Estevamd2292512012-12-28 04:05:28 +0000261 ret = pmic_init(I2C_PMIC);
262 if (ret)
263 return ret;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000264
Fabio Estevam89651122012-12-11 06:36:58 +0000265 p = pmic_get("FSL_PMIC");
Łukasz Majewskic7336812012-11-13 03:21:55 +0000266 if (!p)
267 return -ENODEV;
Fabio Estevam5b547f32012-05-07 10:25:59 +0000268
269 /* Set VDDGP to 1.25V for 1GHz on SW1 */
270 pmic_reg_read(p, REG_SW_0, &val);
271 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
272 ret = pmic_reg_write(p, REG_SW_0, val);
Fabio Estevam085e7282012-12-28 04:05:29 +0000273 if (ret) {
274 printf("Writing to REG_SW_0 failed: %d\n", ret);
275 return ret;
276 }
Fabio Estevam5b547f32012-05-07 10:25:59 +0000277
278 /* Set VCC as 1.30V on SW2 */
279 pmic_reg_read(p, REG_SW_1, &val);
280 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
Fabio Estevam085e7282012-12-28 04:05:29 +0000281 ret = pmic_reg_write(p, REG_SW_1, val);
282 if (ret) {
283 printf("Writing to REG_SW_1 failed: %d\n", ret);
284 return ret;
285 }
Fabio Estevam5b547f32012-05-07 10:25:59 +0000286
287 /* Set global reset timer to 4s */
288 pmic_reg_read(p, REG_POWER_CTL2, &val);
289 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
Fabio Estevam085e7282012-12-28 04:05:29 +0000290 ret = pmic_reg_write(p, REG_POWER_CTL2, val);
291 if (ret) {
292 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
293 return ret;
294 }
Fabio Estevam768a0592012-05-07 10:26:00 +0000295
296 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
297 pmic_reg_read(p, REG_MODE_0, &val);
298 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
Fabio Estevam085e7282012-12-28 04:05:29 +0000299 ret = pmic_reg_write(p, REG_MODE_0, val);
300 if (ret) {
301 printf("Writing to REG_MODE_0 failed: %d\n", ret);
302 return ret;
303 }
Fabio Estevam768a0592012-05-07 10:26:00 +0000304
305 /* Set SWBST to 5V in auto mode */
306 val = SWBST_AUTO;
Fabio Estevam085e7282012-12-28 04:05:29 +0000307 ret = pmic_reg_write(p, SWBST_CTRL, val);
308 if (ret) {
309 printf("Writing to SWBST_CTRL failed: %d\n", ret);
310 return ret;
311 }
312
313 return ret;
Fabio Estevam5b547f32012-05-07 10:25:59 +0000314 }
Fabio Estevame7e33722012-04-30 08:12:04 +0000315
Fabio Estevam085e7282012-12-28 04:05:29 +0000316 return -1;
Fabio Estevame7e33722012-04-30 08:12:04 +0000317}
318
319static void clock_1GHz(void)
320{
321 int ret;
Benoît Thébaudeau833b6432012-09-27 10:19:58 +0000322 u32 ref_clk = MXC_HCLK;
Fabio Estevame7e33722012-04-30 08:12:04 +0000323 /*
324 * After increasing voltage to 1.25V, we can switch
325 * CPU clock to 1GHz and DDR to 400MHz safely
326 */
327 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
328 if (ret)
329 printf("CPU: Switch CPU clock to 1GHZ failed\n");
330
331 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
332 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
333 if (ret)
334 printf("CPU: Switch DDR clock to 400MHz failed\n");
335}
336
Jason Liu938080d2011-05-13 01:58:55 +0000337int board_early_init_f(void)
338{
339 setup_iomux_uart();
340 setup_iomux_fec();
Vikram Narayanan30ea4be2012-11-10 02:32:46 +0000341 setup_iomux_lcd();
Jason Liu938080d2011-05-13 01:58:55 +0000342
343 return 0;
344}
345
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000346int print_cpuinfo(void)
347{
348 u32 cpurev;
349
350 cpurev = get_cpu_rev();
351 printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
352 (cpurev & 0xFF000) >> 12,
353 (cpurev & 0x000F0) >> 4,
354 (cpurev & 0x0000F) >> 0,
355 mxc_get_clock(MXC_ARM_CLK) / 1000000);
356 printf("Reset cause: %s\n", get_reset_cause());
357 return 0;
358}
359
Stefano Babic3e077372012-08-05 00:18:53 +0000360/*
361 * Do not overwrite the console
362 * Use always serial for U-Boot console
363 */
364int overwrite_console(void)
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000365{
Stefano Babic3e077372012-08-05 00:18:53 +0000366 return 1;
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000367}
Fabio Estevam1fc56f12012-04-30 08:12:03 +0000368
Jason Liu938080d2011-05-13 01:58:55 +0000369int board_init(void)
370{
Jason Liu938080d2011-05-13 01:58:55 +0000371 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
372
Stefano Babicf92e4e62012-02-22 00:24:41 +0000373 mxc_set_sata_internal_clock();
Fabio Estevameae08eb2012-05-29 05:54:39 +0000374 setup_iomux_i2c();
Fabio Estevam54bb8412012-12-26 05:50:20 +0000375
Fabio Estevam54bb8412012-12-26 05:50:20 +0000376 return 0;
377}
378
379int board_late_init(void)
380{
Fabio Estevameae08eb2012-05-29 05:54:39 +0000381 if (!power_init())
382 clock_1GHz();
383 print_cpuinfo();
Stefano Babicf92e4e62012-02-22 00:24:41 +0000384
Jason Liu938080d2011-05-13 01:58:55 +0000385 return 0;
386}
387
388int checkboard(void)
389{
390 puts("Board: MX53 LOCO\n");
391
392 return 0;
393}