Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame^] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <asm/arch/clock.h> |
| 10 | #include <asm/arch/iomux.h> |
| 11 | #include <asm/arch/imx-regs.h> |
| 12 | #include <asm/arch/mx6-pins.h> |
| 13 | #include <asm/arch/sys_proto.h> |
| 14 | #include <asm/gpio.h> |
| 15 | #include <asm/imx-common/iomux-v3.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <asm/sizes.h> |
| 18 | #include <common.h> |
| 19 | #include <fsl_esdhc.h> |
| 20 | #include <mmc.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Benoît Thébaudeau | 7e2173c | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 24 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 25 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 26 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 27 | |
Benoît Thébaudeau | 7e2173c | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 28 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ |
| 29 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 30 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 31 | |
| 32 | int dram_init(void) |
| 33 | { |
| 34 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
| 35 | |
| 36 | return 0; |
| 37 | } |
| 38 | |
| 39 | static iomux_v3_cfg_t const uart1_pads[] = { |
| 40 | MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 41 | MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 42 | }; |
| 43 | |
| 44 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
| 45 | MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 46 | MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 47 | MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 48 | MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 49 | MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 50 | MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 51 | }; |
| 52 | |
| 53 | static void setup_iomux_uart(void) |
| 54 | { |
| 55 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 56 | } |
| 57 | |
| 58 | static struct fsl_esdhc_cfg usdhc_cfg[1] = { |
| 59 | {USDHC2_BASE_ADDR}, |
| 60 | }; |
| 61 | |
| 62 | int board_mmc_getcd(struct mmc *mmc) |
| 63 | { |
| 64 | return 1; /* Assume boot SD always present */ |
| 65 | } |
| 66 | |
| 67 | int board_mmc_init(bd_t *bis) |
| 68 | { |
| 69 | imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 70 | |
| 71 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 72 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| 73 | } |
| 74 | |
| 75 | int board_early_init_f(void) |
| 76 | { |
| 77 | setup_iomux_uart(); |
| 78 | return 0; |
| 79 | } |
| 80 | |
| 81 | int board_init(void) |
| 82 | { |
| 83 | /* address of boot parameters */ |
| 84 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 85 | |
| 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | u32 get_board_rev(void) |
| 90 | { |
| 91 | return get_cpu_rev(); |
| 92 | } |
| 93 | |
| 94 | int checkboard(void) |
| 95 | { |
| 96 | puts("Board: MX6SLEVK\n"); |
| 97 | |
| 98 | return 0; |
| 99 | } |