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TsiChungLiew57a12722008-01-15 14:15:46 -06001/*
2 * Configuation settings for the Freescale MCF5475 board.
3 *
4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew57a12722008-01-15 14:15:46 -06008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5475EVB_H
15#define _M5475EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21#define CONFIG_MCF547x_8x /* define processor family */
22#define CONFIG_M547x /* define processor type */
23#define CONFIG_M5475 /* define processor type */
24
TsiChungLiew57a12722008-01-15 14:15:46 -060025#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew57a12722008-01-15 14:15:46 -060027#define CONFIG_BAUDRATE 115200
TsiChungLiew57a12722008-01-15 14:15:46 -060028
29#define CONFIG_HW_WATCHDOG
30#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
31
32/* Command line configuration */
33#include <config_cmd_default.h>
34
35#define CONFIG_CMD_CACHE
36#undef CONFIG_CMD_DATE
37#define CONFIG_CMD_ELF
38#define CONFIG_CMD_FLASH
39#define CONFIG_CMD_I2C
40#define CONFIG_CMD_MEMORY
41#define CONFIG_CMD_MISC
42#define CONFIG_CMD_MII
43#define CONFIG_CMD_NET
44#define CONFIG_CMD_PCI
45#define CONFIG_CMD_PING
46#define CONFIG_CMD_REGINFO
47#define CONFIG_CMD_USB
48
49#define CONFIG_SLTTMR
50
51#define CONFIG_FSLDMAFEC
52#ifdef CONFIG_FSLDMAFEC
TsiChungLiew57a12722008-01-15 14:15:46 -060053# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050054# define CONFIG_MII_INIT 1
TsiChungLiew57a12722008-01-15 14:15:46 -060055# define CONFIG_HAS_ETH1
56
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057# define CONFIG_SYS_DMA_USE_INTSRAM 1
58# define CONFIG_SYS_DISCOVER_PHY
59# define CONFIG_SYS_RX_ETH_BUFFER 32
60# define CONFIG_SYS_TX_ETH_BUFFER 48
61# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew57a12722008-01-15 14:15:46 -060062
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063# define CONFIG_SYS_FEC0_PINMUX 0
64# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
65# define CONFIG_SYS_FEC1_PINMUX 0
66# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChungLiew57a12722008-01-15 14:15:46 -060067
Wolfgang Denk53677ef2008-05-20 16:00:29 +020068# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
70# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew57a12722008-01-15 14:15:46 -060071# define FECDUPLEX FULL
72# define FECSPEED _100BASET
73# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
75# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew57a12722008-01-15 14:15:46 -060076# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew57a12722008-01-15 14:15:46 -060078
79# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
80# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
81# define CONFIG_IPADDR 192.162.1.2
82# define CONFIG_NETMASK 255.255.255.0
83# define CONFIG_SERVERIP 192.162.1.1
84# define CONFIG_GATEWAYIP 192.162.1.1
85# define CONFIG_OVERWRITE_ETHADDR_ONCE
86
87#endif
88
89#ifdef CONFIG_CMD_USB
90# define CONFIG_USB_OHCI_NEW
91# define CONFIG_USB_STORAGE
92
93# ifndef CONFIG_CMD_PCI
94# define CONFIG_CMD_PCI
95# endif
96# define CONFIG_PCI_OHCI
97# define CONFIG_DOS_PARTITION
98
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099# undef CONFIG_SYS_USB_OHCI_BOARD_INIT
100# undef CONFIG_SYS_USB_OHCI_CPU_INIT
101# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
102# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
103# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
TsiChungLiew57a12722008-01-15 14:15:46 -0600104#endif
105
106/* I2C */
107#define CONFIG_FSL_I2C
108#define CONFIG_HARD_I2C /* I2C with hw support */
109#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_I2C_SPEED 80000
111#define CONFIG_SYS_I2C_SLAVE 0x7F
112#define CONFIG_SYS_I2C_OFFSET 0x00008F00
113#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew57a12722008-01-15 14:15:46 -0600114
115/* PCI */
116#ifdef CONFIG_CMD_PCI
117#define CONFIG_PCI 1
118#define CONFIG_PCI_PNP 1
TsiChung Liewf33fca22008-03-30 01:19:06 -0500119#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
TsiChungLiew57a12722008-01-15 14:15:46 -0600120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
TsiChungLiew57a12722008-01-15 14:15:46 -0600122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
124#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
125#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_PCI_IO_BUS 0x71000000
128#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
129#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
132#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
133#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
TsiChungLiew57a12722008-01-15 14:15:46 -0600134#endif
135
136#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
137#define CONFIG_UDP_CHECKSUM
138
139#ifdef CONFIG_MCFFEC
140# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
141# define CONFIG_IPADDR 192.162.1.2
142# define CONFIG_NETMASK 255.255.255.0
143# define CONFIG_SERVERIP 192.162.1.1
144# define CONFIG_GATEWAYIP 192.162.1.1
145# define CONFIG_OVERWRITE_ETHADDR_ONCE
146#endif /* FEC_ENET */
147
148#define CONFIG_HOSTNAME M547xEVB
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "netdev=eth0\0" \
151 "loadaddr=10000\0" \
152 "u-boot=u-boot.bin\0" \
153 "load=tftp ${loadaddr) ${u-boot}\0" \
154 "upd=run load; run prog\0" \
155 "prog=prot off bank 1;" \
Jason Jin09933fb2011-08-19 10:10:40 +0800156 "era ff800000 ff83ffff;" \
TsiChungLiew57a12722008-01-15 14:15:46 -0600157 "cp.b ${loadaddr} ff800000 ${filesize};"\
158 "save\0" \
159 ""
160
161#define CONFIG_PRAM 512 /* 512 KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_PROMPT "-> "
163#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiew57a12722008-01-15 14:15:46 -0600164
165#ifdef CONFIG_CMD_KGDB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiew57a12722008-01-15 14:15:46 -0600167#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiew57a12722008-01-15 14:15:46 -0600169#endif
170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
172#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
173#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
174#define CONFIG_SYS_LOAD_ADDR 0x00010000
TsiChungLiew57a12722008-01-15 14:15:46 -0600175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_HZ 1000
177#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
178#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
TsiChungLiew57a12722008-01-15 14:15:46 -0600179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_MBAR 0xF0000000
181#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
182#define CONFIG_SYS_INTSRAMSZ 0x8000
TsiChungLiew57a12722008-01-15 14:15:46 -0600183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
TsiChungLiew57a12722008-01-15 14:15:46 -0600185
186/*
187 * Low Level Configuration Settings
188 * (address mappings, register initial values, etc.)
189 * You should know what you are doing if you make changes here.
190 */
191/*-----------------------------------------------------------------------
192 * Definitions for initial stack pointer and data area (in DPRAM)
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200195#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_INIT_RAM_CTRL 0x21
Wolfgang Denk553f0982010-10-26 13:32:32 +0200197#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
199#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200200#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiew57a12722008-01-15 14:15:46 -0600202
203/*-----------------------------------------------------------------------
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew57a12722008-01-15 14:15:46 -0600207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_SDRAM_BASE 0x00000000
209#define CONFIG_SYS_SDRAM_CFG1 0x73711630
210#define CONFIG_SYS_SDRAM_CFG2 0x46770000
211#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
212#define CONFIG_SYS_SDRAM_EMOD 0x40010000
213#define CONFIG_SYS_SDRAM_MODE 0x018D0000
214#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
215#ifdef CONFIG_SYS_DRAMSZ1
216# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
TsiChungLiew57a12722008-01-15 14:15:46 -0600217#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
TsiChungLiew57a12722008-01-15 14:15:46 -0600219#endif
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
222#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew57a12722008-01-15 14:15:46 -0600223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
225#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiew57a12722008-01-15 14:15:46 -0600226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
TsiChungLiew57a12722008-01-15 14:15:46 -0600228
Jason Jin09933fb2011-08-19 10:10:40 +0800229/* Reserve 256 kB for malloc() */
230#define CONFIG_SYS_MALLOC_LEN (256 << 10)
TsiChungLiew57a12722008-01-15 14:15:46 -0600231/*
232 * For booting Linux, the board info and command line data
233 * have to be in the first 8 MB of memory, since this is
234 * the maximum mapped by the Linux kernel during initialization ??
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChungLiew57a12722008-01-15 14:15:46 -0600237
238/*-----------------------------------------------------------------------
239 * FLASH organization
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_FLASH_CFI
242#ifdef CONFIG_SYS_FLASH_CFI
243# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200244# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
246# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
247# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
248# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
249#ifdef CONFIG_SYS_NOR1SZ
250# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
251# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
252# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
TsiChungLiew57a12722008-01-15 14:15:46 -0600253#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
255# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
TsiChungLiew57a12722008-01-15 14:15:46 -0600256#endif
257#endif
258
259/* Configuration for environment
Jason Jin09933fb2011-08-19 10:10:40 +0800260 * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
261 * First time runing may have env crc error warning if there is
262 * no correct environment on the flash.
TsiChungLiew57a12722008-01-15 14:15:46 -0600263 */
Jason Jin09933fb2011-08-19 10:10:40 +0800264#define CONFIG_ENV_OFFSET 0x40000
265#define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200266#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiew57a12722008-01-15 14:15:46 -0600267
268/*-----------------------------------------------------------------------
269 * Cache Configuration
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew57a12722008-01-15 14:15:46 -0600272
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600273#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200274 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600275#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200276 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600277#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
278 CF_CACR_IDCM)
279#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
280#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
281 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
282 CF_ACR_EN | CF_ACR_SM_ALL)
283#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
284 CF_CACR_IEC | CF_CACR_ICINVA)
285#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
286 CF_CACR_DEC | CF_CACR_DDCM_P | \
287 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
288
TsiChungLiew57a12722008-01-15 14:15:46 -0600289/*-----------------------------------------------------------------------
290 * Chipselect bank definitions
291 */
292/*
293 * CS0 - NOR Flash 1, 2, 4, or 8MB
294 * CS1 - NOR Flash
295 * CS2 - Available
296 * CS3 - Available
297 * CS4 - Available
298 * CS5 - Available
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_CS0_BASE 0xFF800000
301#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
302#define CONFIG_SYS_CS0_CTRL 0x00101980
TsiChungLiew57a12722008-01-15 14:15:46 -0600303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#ifdef CONFIG_SYS_NOR1SZ
305#define CONFIG_SYS_CS1_BASE 0xE0000000
306#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
307#define CONFIG_SYS_CS1_CTRL 0x00101D80
TsiChungLiew57a12722008-01-15 14:15:46 -0600308#endif
309
310#endif /* _M5475EVB_H */