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wdenkba91e262005-05-30 23:55:42 +00001/*
2 * (C) Copyright 2004
3 * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
4 *
5 * Support for the Elmeg VoVPN Gateway Module
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenkba91e262005-05-30 23:55:42 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* define cpu used */
14#define CONFIG_MPC8272 1
15
16/* define busmode: 8260 */
17#undef CONFIG_BUSMODE_60x
18
Wolfgang Denk2ae18242010-10-06 09:05:45 +020019#define CONFIG_SYS_TEXT_BASE 0xfff00000
20
wdenkba91e262005-05-30 23:55:42 +000021/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
22#ifdef CONFIG_CLKIN_66MHz
23#define CONFIG_8260_CLKIN 66666666 /* in Hz */
24#else
25#define CONFIG_8260_CLKIN 100000000 /* in Hz */
26#endif
27
28/* call board_early_init_f */
29#define CONFIG_BOARD_EARLY_INIT_F 1
30
31/* have misc_init_r() function */
32#define CONFIG_MISC_INIT_R 1
33
34/* have reset_phy_r() function */
35#define CONFIG_RESET_PHY_R 1
36
37/* have special reset function */
38#define CONFIG_HAVE_OWN_RESET 1
39
40/* allow serial and ethaddr to be overwritten */
41#define CONFIG_ENV_OVERWRITE
42
43/* watchdog disabled */
44#undef CONFIG_WATCHDOG
45
46/* include support for bzip2 compressed images */
47#undef CONFIG_BZIP2
48
49/* status led */
50#undef CONFIG_STATUS_LED /* XXX jse */
51
52/* vendor parameter protection */
53#define CONFIG_ENV_OVERWRITE
54
55/*
56 * select serial console configuration
57 *
58 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
59 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
60 * for SCC).
61 */
62#define CONFIG_CONS_ON_SMC
63#undef CONFIG_CONS_ON_SCC
64#undef CONFIG_CONS_NONE
65#define CONFIG_CONS_INDEX 1
66
67/* serial port default baudrate */
68#define CONFIG_BAUDRATE 115200
69
70/* echo on for serial download */
71#define CONFIG_LOADS_ECHO 1
72
73/* don't allow baudrate change */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#undef CONFIG_SYS_LOADS_BAUD_CHANGE
wdenkba91e262005-05-30 23:55:42 +000075
wdenkba91e262005-05-30 23:55:42 +000076/*
77 * select ethernet configuration
78 *
79 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
80 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
81 * for FCC)
82 *
83 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050084 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkba91e262005-05-30 23:55:42 +000085 */
86#undef CONFIG_ETHER_ON_SCC
87#define CONFIG_ETHER_ON_FCC
88#undef CONFIG_ETHER_NONE
89
90#ifdef CONFIG_ETHER_ON_FCC
91
92/* which SCC/FCC channel for ethernet */
93#define CONFIG_ETHER_INDEX 1
94
95/* Marvell Switch SMI base addr */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_PHY_ADDR 0x10
wdenkba91e262005-05-30 23:55:42 +000097
98/* FCC1 RMII REFCLK is CLK10 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
100#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK)
wdenkba91e262005-05-30 23:55:42 +0000101
102/* BDs and buffers on 60x bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_CPMFCR_RAMTYPE 0
wdenkba91e262005-05-30 23:55:42 +0000104
105/* Local Protect, Full duplex, Flowcontrol, RMII */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\
wdenkba91e262005-05-30 23:55:42 +0000107 FCC_PSMR_FCE|FCC_PSMR_RMII)
108
109/* bit-bang MII PHY management */
110#define CONFIG_BITBANGMII
111
112#define MDIO_PORT 1 /* Port B */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200113
114#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
115 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
116#define MDC_DECLARE MDIO_DECLARE
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */
119#define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */
120#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
121#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
122#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
123#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
124 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
125#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
126 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
wdenkba91e262005-05-30 23:55:42 +0000127#define MIIDELAY udelay(1)
128
129#endif
130
Jon Loeligera5562902007-07-08 15:31:57 -0500131/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500132 * BOOTP options
133 */
134#define CONFIG_BOOTP_BOOTFILESIZE
135#define CONFIG_BOOTP_BOOTPATH
136#define CONFIG_BOOTP_GATEWAY
137#define CONFIG_BOOTP_HOSTNAME
138
139
140/*
Jon Loeligera5562902007-07-08 15:31:57 -0500141 * Command line configuration.
142 */
wdenkba91e262005-05-30 23:55:42 +0000143
Jon Loeligera5562902007-07-08 15:31:57 -0500144#define CONFIG_CMD_BDI
145#define CONFIG_CMD_CONSOLE
146#define CONFIG_CMD_ECHO
Jon Loeligera5562902007-07-08 15:31:57 -0500147#define CONFIG_CMD_FLASH
148#define CONFIG_CMD_IMI
149#define CONFIG_CMD_IMLS
150#define CONFIG_CMD_LOADB
151#define CONFIG_CMD_MEMORY
152#define CONFIG_CMD_MISC
153#define CONFIG_CMD_NET
154#define CONFIG_CMD_PING
155#define CONFIG_CMD_RUN
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200156#define CONFIG_CMD_SAVEENV
157#define CONFIG_CMD_SOURCE
Jon Loeligera5562902007-07-08 15:31:57 -0500158
wdenkba91e262005-05-30 23:55:42 +0000159
160/*
161 * boot options & environment
162 */
163#define CONFIG_BOOTDELAY 3
164#define CONFIG_BOOTCOMMAND "run flash_self"
165#undef CONFIG_BOOTARGS
166#define CONFIG_EXTRA_ENV_SETTINGS \
167"clean_nv=erase fff20000 ffffffff\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100168"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
169"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
170"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
171"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
172"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
173"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
174"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
175"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
176"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
177"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
178"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
179"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
wdenkba91e262005-05-30 23:55:42 +0000180"fstype=cramfs\0" \
181"rootpath=/root_fs\0" \
182"uboot=PPC/u-boot.bin\0" \
183"kernel=PPC/uImage\0" \
184"kernel_addr=ffe00000\0" \
185"fs=PPC/root_fs\0" \
186"console=ttyS0\0" \
187"netdev=eth0\0" \
188"rootdev=31:3\0" \
189"ethaddr=00:09:4f:01:02:03\0" \
190"ipaddr=10.0.0.201\0" \
191"netmask=255.255.255.0\0" \
192"serverip=10.0.0.136\0" \
193"gatewayip=10.0.0.10\0" \
194"hostname=bastard\0" \
195""
196
197
198/*
199 * miscellaneous configurable options
200 */
201
202/* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_LONGHELP
wdenkba91e262005-05-30 23:55:42 +0000204
205/* monitor command prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_PROMPT "=> "
wdenkba91e262005-05-30 23:55:42 +0000207
208/* console i/o buffer size */
Jon Loeligera5562902007-07-08 15:31:57 -0500209#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_CBSIZE 1024
wdenkba91e262005-05-30 23:55:42 +0000211#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_CBSIZE 256
wdenkba91e262005-05-30 23:55:42 +0000213#endif
214
215/* print buffer size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenkba91e262005-05-30 23:55:42 +0000217
218/* max number of command args */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MAXARGS 16
wdenkba91e262005-05-30 23:55:42 +0000220
221/* boot argument buffer size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
wdenkba91e262005-05-30 23:55:42 +0000223
224/* memtest works on */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_MEMTEST_START 0x00100000
wdenkba91e262005-05-30 23:55:42 +0000226/* 1 ... 15 MB in DRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_MEMTEST_END 0x00f00000
wdenkba91e262005-05-30 23:55:42 +0000228/* full featured memtest */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_ALT_MEMTEST
wdenkba91e262005-05-30 23:55:42 +0000230
231/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_LOAD_ADDR 0x00100000
wdenkba91e262005-05-30 23:55:42 +0000233
234/* decrementer freq: 1 ms ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_HZ 1000
wdenkba91e262005-05-30 23:55:42 +0000236
237/* configure flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_FLASH_BASE 0xff800000
239#define CONFIG_SYS_MAX_FLASH_BANKS 1
240#define CONFIG_SYS_MAX_FLASH_SECT 64
241#define CONFIG_SYS_FLASH_SIZE 8
242#undef CONFIG_SYS_FLASH_16BIT
243#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
244#define CONFIG_SYS_FLASH_WRITE_TOUT 500
245#define CONFIG_SYS_FLASH_LOCK_TOUT 500
246#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
247#define CONFIG_SYS_FLASH_PROTECTION
wdenkba91e262005-05-30 23:55:42 +0000248
249/* monitor in flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_MONITOR_OFFSET 0x00700000
wdenkba91e262005-05-30 23:55:42 +0000251
252/* environment in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200253#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00020000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200255#define CONFIG_ENV_SIZE 0x00020000
256#define CONFIG_ENV_SECT_SIZE 0x00020000
wdenkba91e262005-05-30 23:55:42 +0000257
258/*
259 * Initial memory map for linux
260 * For booting Linux, the board info and command line data
261 * have to be in the first 8 MB of memory, since this is
262 * the maximum mapped by the Linux kernel during initialization.
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
wdenkba91e262005-05-30 23:55:42 +0000265
266/* hard reset configuration words */
267#ifdef CONFIG_CLKIN_66MHz
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_HRCW_MASTER 0x04643050
wdenkba91e262005-05-30 23:55:42 +0000269#else
270#error NO HRCW FOR 100MHZ SPECIFIED !!!
271#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_HRCW_SLAVE1 0x00000000
273#define CONFIG_SYS_HRCW_SLAVE2 0x00000000
274#define CONFIG_SYS_HRCW_SLAVE3 0x00000000
275#define CONFIG_SYS_HRCW_SLAVE4 0x00000000
276#define CONFIG_SYS_HRCW_SLAVE5 0x00000000
277#define CONFIG_SYS_HRCW_SLAVE6 0x00000000
278#define CONFIG_SYS_HRCW_SLAVE7 0x00000000
wdenkba91e262005-05-30 23:55:42 +0000279
280/* internal memory mapped register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_IMMR 0xF0000000
wdenkba91e262005-05-30 23:55:42 +0000282
283/* definitions for initial stack pointer and data area (in DPRAM) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200285#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200286#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkba91e262005-05-30 23:55:42 +0000288
289/*
290 * Start addresses for the final memory configuration
291 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkba91e262005-05-30 23:55:42 +0000293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_SDRAM_BASE 0x00000000
295#define CONFIG_SYS_SDRAM_SIZE (32*1024*1024)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200296#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_MONITOR_FLASH (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
298#define CONFIG_SYS_MONITOR_LEN 0x00020000
299#define CONFIG_SYS_MALLOC_LEN 0x00020000
wdenkba91e262005-05-30 23:55:42 +0000300
wdenkba91e262005-05-30 23:55:42 +0000301/* cache configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_CACHELINE_SIZE 32 /* for MPC8260 */
Jon Loeligera5562902007-07-08 15:31:57 -0500303#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of above */
wdenkba91e262005-05-30 23:55:42 +0000305#endif
306
307/*
308 * HIDx - Hardware Implementation-dependent Registers
309 *-----------------------------------------------------------------------
310 * HID0 also contains cache control - initially enable both caches and
311 * invalidate contents, then the final state leaves only the instruction
312 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
313 * but Soft reset does not.
314 *
315 * HID1 has only read-only information - nothing to set.
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|\
wdenkba91e262005-05-30 23:55:42 +0000318 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
320#define CONFIG_SYS_HID2 0
wdenkba91e262005-05-30 23:55:42 +0000321
322/* RMR - reset mode register - turn on checkstop reset enable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_RMR RMR_CSRE
wdenkba91e262005-05-30 23:55:42 +0000324
325/* BCR - bus configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_BCR 0x00000000
wdenkba91e262005-05-30 23:55:42 +0000327
328/* SIUMCR - siu module configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_SIUMCR 0x4905c000
wdenkba91e262005-05-30 23:55:42 +0000330
331/* SYPCR - system protection control */
332#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_SYPCR 0xffffff87
wdenkba91e262005-05-30 23:55:42 +0000334#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_SYPCR 0xffffff83
wdenkba91e262005-05-30 23:55:42 +0000336#endif
337
338/* TMCNTSC - time counter status and control */
339/* clear interrupts XXX jse */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340/*#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */
341#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\
wdenkba91e262005-05-30 23:55:42 +0000342 TMCNTSC_TCF|TMCNTSC_TCE)
343
344/* PISCR - periodic interrupt status and control */
345/* clear interrupts XXX jse */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346/*#define CONFIG_SYS_PISCR (PISCR_PS) */
347#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenkba91e262005-05-30 23:55:42 +0000348
349/* SCCR - system clock control */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_SCCR 0x000001a9
wdenkba91e262005-05-30 23:55:42 +0000351
352/* RCCR - risc controller configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_RCCR 0
wdenkba91e262005-05-30 23:55:42 +0000354
355/*
356 * MEMORY MAP
357 * ----------
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200358 * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
wdenkba91e262005-05-30 23:55:42 +0000359 * CS1 - SDRAM 32MB/64Bit base=0x00000000
360 * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
361 * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
362 * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
363 * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
364 * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
365 * x - IMMR 384KB base=0xf0000000
366 */
367/* XXX jse 100MHz TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_BR0_PRELIM 0xff800801
369#define CONFIG_SYS_OR0_PRELIM 0xff801e44
370#define CONFIG_SYS_BR1_PRELIM 0x00000041
371#define CONFIG_SYS_OR1_PRELIM 0xfe002ec0
wdenkba91e262005-05-30 23:55:42 +0000372#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_BR2_PRELIM 0xf0101001
374#define CONFIG_SYS_OR2_PRELIM 0xfff00ef4
375#define CONFIG_SYS_BR3_PRELIM 0xf0201001
376#define CONFIG_SYS_OR3_PRELIM 0xfff00ef4
377#define CONFIG_SYS_BR4_PRELIM 0xf0301001
378#define CONFIG_SYS_OR4_PRELIM 0xfff00ef4
379#define CONFIG_SYS_BR5_PRELIM 0xf0401001
380#define CONFIG_SYS_OR5_PRELIM 0xfff00ef4
wdenkba91e262005-05-30 23:55:42 +0000381#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_BR2_PRELIM 0xf0101081
383#define CONFIG_SYS_OR2_PRELIM 0xfff00104
384#define CONFIG_SYS_BR3_PRELIM 0xf0201081
385#define CONFIG_SYS_OR3_PRELIM 0xfff00104
386#define CONFIG_SYS_BR4_PRELIM 0xf0301081
387#define CONFIG_SYS_OR4_PRELIM 0xfff00104
388#define CONFIG_SYS_BR5_PRELIM 0xf0401081
389#define CONFIG_SYS_OR5_PRELIM 0xfff00104
wdenkba91e262005-05-30 23:55:42 +0000390#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_BR7_PRELIM 0xf0500881
392#define CONFIG_SYS_OR7_PRELIM 0xffff8104
393#define CONFIG_SYS_MPTPR 0x2700
394#define CONFIG_SYS_PSDMR 0x822a2452 /* optimal */
395/*#define CONFIG_SYS_PSDMR 0x822a48a3 */ /* relaxed */
396#define CONFIG_SYS_PSRT 0x1a
wdenkba91e262005-05-30 23:55:42 +0000397
398/* "bad" address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_RESET_ADDRESS 0x40000000
wdenkba91e262005-05-30 23:55:42 +0000400
401#endif /* __CONFIG_H */