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Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +02003 */
wdenkba56f622004-02-06 23:19:44 +00004/*-----------------------------------------------------------------------------+
5 *
Wolfgang Denk265817c2005-09-25 00:53:22 +02006 * File Name: enetemac.c
wdenkba56f622004-02-06 23:19:44 +00007 *
Wolfgang Denk265817c2005-09-25 00:53:22 +02008 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
wdenkba56f622004-02-06 23:19:44 +00009 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020010 * Author: Mark Wisner
wdenkba56f622004-02-06 23:19:44 +000011 *
12 * Change Activity-
13 *
Wolfgang Denk265817c2005-09-25 00:53:22 +020014 * Date Description of Change BY
15 * --------- --------------------- ---
16 * 05-May-99 Created MKW
17 * 27-Jun-99 Clean up JWB
18 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
19 * 29-Jul-99 Added Full duplex support MKW
20 * 06-Aug-99 Changed names for Mal CR reg MKW
21 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
22 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
23 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
24 * to avoid chaining maximum sized packets. Push starting
25 * RX descriptor address up to the next cache line boundary.
26 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
27 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
Niklaus Gigerddc922f2009-10-04 20:04:20 +020028 * EMAC0_RXM register. JWB
Wolfgang Denk265817c2005-09-25 00:53:22 +020029 * 12-Mar-01 anne-sophie.harnois@nextream.fr
30 * - Variables are compatible with those already defined in
31 * include/net.h
32 * - Receive buffer descriptor ring is used to send buffers
33 * to the user
34 * - Info print about send/received/handled packet number if
35 * INFO_405_ENET is set
36 * 17-Apr-01 stefan.roese@esd-electronics.com
37 * - MAL reset in "eth_halt" included
38 * - Enet speed and duplex output now in one line
39 * 08-May-01 stefan.roese@esd-electronics.com
40 * - MAL error handling added (eth_init called again)
41 * 13-Nov-01 stefan.roese@esd-electronics.com
Niklaus Gigerddc922f2009-10-04 20:04:20 +020042 * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
Wolfgang Denk265817c2005-09-25 00:53:22 +020043 * 04-Jan-02 stefan.roese@esd-electronics.com
44 * - Wait for PHY auto negotiation to complete added
45 * 06-Feb-02 stefan.roese@esd-electronics.com
46 * - Bug fixed in waiting for auto negotiation to complete
47 * 26-Feb-02 stefan.roese@esd-electronics.com
48 * - rx and tx buffer descriptors now allocated (no fixed address
49 * used anymore)
50 * 17-Jun-02 stefan.roese@esd-electronics.com
51 * - MAL error debug printf 'M' removed (rx de interrupt may
52 * occur upon many incoming packets with only 4 rx buffers).
wdenkba56f622004-02-06 23:19:44 +000053 *-----------------------------------------------------------------------------*
Wolfgang Denk265817c2005-09-25 00:53:22 +020054 * 17-Nov-03 travis.sawyer@sandburst.com
55 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
56 * in the 440GX. This port should work with the 440GP
57 * (2 EMACs) also
58 * 15-Aug-05 sr@denx.de
59 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
60 now handling all 4xx cpu's.
wdenkba56f622004-02-06 23:19:44 +000061 *-----------------------------------------------------------------------------*/
62
63#include <config.h>
wdenkba56f622004-02-06 23:19:44 +000064#include <common.h>
65#include <net.h>
66#include <asm/processor.h>
Stefan Roese2d834762007-10-23 14:03:17 +020067#include <asm/io.h>
Stefan Roeseff768cb2007-10-31 18:01:24 +010068#include <asm/cache.h>
69#include <asm/mmu.h>
wdenkba56f622004-02-06 23:19:44 +000070#include <commproc.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020071#include <asm/ppc4xx.h>
72#include <asm/ppc4xx-emac.h>
73#include <asm/ppc4xx-mal.h>
wdenkba56f622004-02-06 23:19:44 +000074#include <miiphy.h>
75#include <malloc.h>
Stefan Roesef0813ab2011-11-15 08:01:58 +000076#include <linux/compiler.h>
wdenkba56f622004-02-06 23:19:44 +000077
Jon Loeliger3a1ed1e2007-07-09 18:57:22 -050078#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
Stefan Roesed6c61aa2005-08-16 18:18:00 +020079#error "CONFIG_MII has to be defined!"
80#endif
wdenkba56f622004-02-06 23:19:44 +000081
Wolfgang Denk265817c2005-09-25 00:53:22 +020082#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
Stefan Roese1338e6a2007-10-23 14:05:08 +020083#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
wdenkba56f622004-02-06 23:19:44 +000084
wdenkba56f622004-02-06 23:19:44 +000085/* Ethernet Transmit and Receive Buffers */
86/* AS.HARNOIS
87 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
88 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
89 */
Wolfgang Denk265817c2005-09-25 00:53:22 +020090#define ENET_MAX_MTU PKTSIZE
wdenkba56f622004-02-06 23:19:44 +000091#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
92
wdenkba56f622004-02-06 23:19:44 +000093/*-----------------------------------------------------------------------------+
94 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
95 * Interrupt Controller).
96 *-----------------------------------------------------------------------------*/
Stefan Roesed1631fe2008-06-26 13:40:57 +020097#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
98
99#if defined(CONFIG_HAS_ETH3)
100#if !defined(CONFIG_440GX)
101#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
102 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
103#else
104/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
105#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
106#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
107#endif /* !defined(CONFIG_440GX) */
108#elif defined(CONFIG_HAS_ETH2)
109#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
110 UIC_MASK(ETH_IRQ_NUM(2)))
111#elif defined(CONFIG_HAS_ETH1)
112#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
113#else
114#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
115#endif
116
117/*
118 * Define a default version for UIC_ETHxB for non 440GX so that we can
119 * use common code for all 4xx variants
120 */
121#if !defined(UIC_ETHxB)
122#define UIC_ETHxB 0
123#endif
124
125#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
126#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
127#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
128#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
129#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
130
131#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
132#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
133
134/*
135 * We have 3 different interrupt types:
136 * - MAL interrupts indicating successful transfer
137 * - MAL error interrupts indicating MAL related errors
138 * - EMAC interrupts indicating EMAC related errors
139 *
140 * All those interrupts can be on different UIC's, but since
141 * now at least all interrupts from one type are on the same
142 * UIC. Only exception is 440GX where the EMAC interrupts are
143 * spread over two UIC's!
144 */
Stefan Roese5de85142008-06-26 17:36:39 +0200145#if defined(CONFIG_440GX)
146#define UIC_BASE_MAL UIC1_DCR_BASE
147#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
148#define UIC_BASE_EMAC UIC2_DCR_BASE
149#define UIC_BASE_EMAC_B UIC3_DCR_BASE
150#else
Stefan Roesed1631fe2008-06-26 13:40:57 +0200151#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
152#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
153#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
Stefan Roesed1631fe2008-06-26 13:40:57 +0200154#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
155#endif
wdenkba56f622004-02-06 23:19:44 +0000156
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200157#undef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +0000158
Wolfgang Denk265817c2005-09-25 00:53:22 +0200159#define BI_PHYMODE_NONE 0
160#define BI_PHYMODE_ZMII 1
wdenk3c74e322004-02-22 23:46:08 +0000161#define BI_PHYMODE_RGMII 2
Stefan Roese887e2ec2006-09-07 11:51:23 +0200162#define BI_PHYMODE_GMII 3
163#define BI_PHYMODE_RTBI 4
164#define BI_PHYMODE_TBI 5
Stefan Roesedbbd1252007-10-05 17:10:59 +0200165#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100166 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200167 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200168#define BI_PHYMODE_SMII 6
169#define BI_PHYMODE_MII 7
Stefan Roese8ac41e32008-03-11 15:05:26 +0100170#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
171#define BI_PHYMODE_RMII 8
172#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200173#endif
Victor Gallardo78d78232008-09-04 23:49:36 -0700174#define BI_PHYMODE_SGMII 9
wdenk3c74e322004-02-22 23:46:08 +0000175
Stefan Roese1941cce2007-10-05 17:35:10 +0200176#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200177 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100178 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200179 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200180#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
181#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200182
Stefan Roese8ac41e32008-03-11 15:05:26 +0100183#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
184#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
185#endif
186
187#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
188#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
189#else
190#define MAL_RX_CHAN_MUL 1
191#endif
192
Victor Gallardo78d78232008-09-04 23:49:36 -0700193/*--------------------------------------------------------------------+
194 * Fixed PHY (PHY-less) support for Ethernet Ports.
195 *--------------------------------------------------------------------*/
196
197/*
198 * Some boards do not have a PHY for each ethernet port. These ports
199 * are known as Fixed PHY (or PHY-less) ports. For such ports, set
200 * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201 * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
Victor Gallardo78d78232008-09-04 23:49:36 -0700202 * duplex should be for these ports in the board configuration
203 * file.
204 *
205 * For Example:
206 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
207 *
208 * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
209 * #define CONFIG_PHY1_ADDR 1
210 * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
211 * #define CONFIG_PHY3_ADDR 3
212 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
Victor Gallardo78d78232008-09-04 23:49:36 -0700214 * {devnum, speed, duplex},
215 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216 * #define CONFIG_SYS_FIXED_PHY_PORTS \
217 * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
218 * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
Victor Gallardo78d78232008-09-04 23:49:36 -0700219 */
220
221#ifndef CONFIG_FIXED_PHY
222#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
223#endif
224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#ifndef CONFIG_SYS_FIXED_PHY_PORTS
226#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
Victor Gallardo78d78232008-09-04 23:49:36 -0700227#endif
228
229struct fixed_phy_port {
230 unsigned int devnum; /* ethernet port */
231 unsigned int speed; /* specified speed 10,100 or 1000 */
232 unsigned int duplex; /* specified duplex FULL or HALF */
233};
234
235static const struct fixed_phy_port fixed_phy_port[] = {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
Victor Gallardo78d78232008-09-04 23:49:36 -0700237};
238
wdenkba56f622004-02-06 23:19:44 +0000239/*-----------------------------------------------------------------------------+
240 * Global variables. TX and RX descriptors and buffers.
241 *-----------------------------------------------------------------------------*/
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200242
Stefan Roese1e25f952005-10-20 16:34:28 +0200243/*
244 * Get count of EMAC devices (doesn't have to be the max. possible number
245 * supported by the cpu)
Stefan Roese353f2682007-10-23 10:10:08 +0200246 *
247 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
248 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
249 * 405EX/405EXr eval board, using the same binary.
Stefan Roese1e25f952005-10-20 16:34:28 +0200250 */
Stefan Roese353f2682007-10-23 10:10:08 +0200251#if defined(CONFIG_BOARD_EMAC_COUNT)
252#define LAST_EMAC_NUM board_emac_count()
253#else /* CONFIG_BOARD_EMAC_COUNT */
Stefan Roese1e25f952005-10-20 16:34:28 +0200254#if defined(CONFIG_HAS_ETH3)
255#define LAST_EMAC_NUM 4
256#elif defined(CONFIG_HAS_ETH2)
257#define LAST_EMAC_NUM 3
258#elif defined(CONFIG_HAS_ETH1)
259#define LAST_EMAC_NUM 2
260#else
261#define LAST_EMAC_NUM 1
262#endif
Stefan Roese353f2682007-10-23 10:10:08 +0200263#endif /* CONFIG_BOARD_EMAC_COUNT */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200264
Stefan Roese5fb692c2007-01-18 10:25:34 +0100265/* normal boards start with EMAC0 */
266#if !defined(CONFIG_EMAC_NR_START)
267#define CONFIG_EMAC_NR_START 0
268#endif
269
Stefan Roeseff768cb2007-10-31 18:01:24 +0100270#define MAL_RX_DESC_SIZE 2048
271#define MAL_TX_DESC_SIZE 2048
272#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
273
wdenkba56f622004-02-06 23:19:44 +0000274/*-----------------------------------------------------------------------------+
275 * Prototypes and externals.
276 *-----------------------------------------------------------------------------*/
277static void enet_rcv (struct eth_device *dev, unsigned long malisr);
278
279int enetInt (struct eth_device *dev);
280static void mal_err (struct eth_device *dev, unsigned long isr,
281 unsigned long uic, unsigned long maldef,
282 unsigned long mal_errr);
283static void emac_err (struct eth_device *dev, unsigned long isr);
284
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200285extern int phy_setup_aneg (char *devname, unsigned char addr);
Mike Frysinger5700bb62010-07-27 18:35:08 -0400286extern int emac4xx_miiphy_read (const char *devname, unsigned char addr,
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200287 unsigned char reg, unsigned short *value);
Mike Frysinger5700bb62010-07-27 18:35:08 -0400288extern int emac4xx_miiphy_write (const char *devname, unsigned char addr,
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200289 unsigned char reg, unsigned short value);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200290
Stefan Roese353f2682007-10-23 10:10:08 +0200291int board_emac_count(void);
292
Stefan Roese8ac41e32008-03-11 15:05:26 +0100293static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
294{
295#if defined(CONFIG_440SPE) || \
296 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
297 defined(CONFIG_405EX)
298 u32 val;
299
Stefan Roesed1c3b272009-09-09 16:25:29 +0200300 mfsdr(SDR0_MFR, val);
Stefan Roese8ac41e32008-03-11 15:05:26 +0100301 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200302 mtsdr(SDR0_MFR, val);
Stefan Roese8ac41e32008-03-11 15:05:26 +0100303#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
304 u32 val;
305
306 mfsdr(SDR0_ETH_CFG, val);
307 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
308 mtsdr(SDR0_ETH_CFG, val);
309#endif
310}
311
312static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
313{
314#if defined(CONFIG_440SPE) || \
315 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
316 defined(CONFIG_405EX)
317 u32 val;
318
Stefan Roesed1c3b272009-09-09 16:25:29 +0200319 mfsdr(SDR0_MFR, val);
Stefan Roese8ac41e32008-03-11 15:05:26 +0100320 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200321 mtsdr(SDR0_MFR, val);
Stefan Roese8ac41e32008-03-11 15:05:26 +0100322#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
323 u32 val;
324
325 mfsdr(SDR0_ETH_CFG, val);
326 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
327 mtsdr(SDR0_ETH_CFG, val);
328#endif
329}
330
wdenkba56f622004-02-06 23:19:44 +0000331/*-----------------------------------------------------------------------------+
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200332| ppc_4xx_eth_halt
wdenkba56f622004-02-06 23:19:44 +0000333| Disable MAL channel, and EMACn
wdenkba56f622004-02-06 23:19:44 +0000334+-----------------------------------------------------------------------------*/
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200335static void ppc_4xx_eth_halt (struct eth_device *dev)
wdenkba56f622004-02-06 23:19:44 +0000336{
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200337 EMAC_4XX_HW_PST hw_p = dev->priv;
Stefan Roese9ad31982008-03-19 16:35:12 +0100338 u32 val = 10000;
wdenkba56f622004-02-06 23:19:44 +0000339
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200340 out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
wdenkba56f622004-02-06 23:19:44 +0000341
342 /* 1st reset MAL channel */
343 /* Note: writing a 0 to a channel has no effect */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200344#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200345 mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200346#else
Stefan Roesed1c3b272009-09-09 16:25:29 +0200347 mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum));
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200348#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +0200349 mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum));
wdenkba56f622004-02-06 23:19:44 +0000350
351 /* wait for reset */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200352 while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) {
wdenkba56f622004-02-06 23:19:44 +0000353 udelay (1000); /* Delay 1 MS so as not to hammer the register */
Stefan Roese9ad31982008-03-19 16:35:12 +0100354 val--;
355 if (val == 0)
wdenkba56f622004-02-06 23:19:44 +0000356 break;
wdenkba56f622004-02-06 23:19:44 +0000357 }
358
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200359 /* provide clocks for EMAC internal loopback */
Stefan Roese8ac41e32008-03-11 15:05:26 +0100360 emac_loopback_enable(hw_p);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200361
Stefan Roese8ac41e32008-03-11 15:05:26 +0100362 /* EMAC RESET */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200363 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
wdenkba56f622004-02-06 23:19:44 +0000364
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200365 /* remove clocks for EMAC internal loopback */
Stefan Roese8ac41e32008-03-11 15:05:26 +0100366 emac_loopback_disable(hw_p);
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200367
Stefan Roesea93316c2005-10-18 19:17:12 +0200368#ifndef CONFIG_NETCONSOLE
Stefan Roesec157d8e2005-08-01 16:41:48 +0200369 hw_p->print_speed = 1; /* print speed message again next time */
Stefan Roesea93316c2005-10-18 19:17:12 +0200370#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200371
Stefan Roese4c9e8552008-03-19 16:20:49 +0100372#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
373 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
Stefan Roese9ad31982008-03-19 16:35:12 +0100374 mfsdr(SDR0_ETH_CFG, val);
375 val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
376 mtsdr(SDR0_ETH_CFG, val);
Stefan Roese4c9e8552008-03-19 16:20:49 +0100377#endif
378
wdenkba56f622004-02-06 23:19:44 +0000379 return;
380}
381
Stefan Roese846b0dd2005-08-08 12:42:22 +0200382#if defined (CONFIG_440GX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200383int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
wdenk855a4962004-03-14 18:23:55 +0000384{
385 unsigned long pfc1;
386 unsigned long zmiifer;
387 unsigned long rmiifer;
388
Stefan Roesed1c3b272009-09-09 16:25:29 +0200389 mfsdr(SDR0_PFC1, pfc1);
wdenk855a4962004-03-14 18:23:55 +0000390 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
391
392 zmiifer = 0;
393 rmiifer = 0;
394
395 switch (pfc1) {
396 case 1:
397 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
398 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
399 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
400 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
401 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
402 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
403 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
404 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
405 break;
406 case 2:
Stefan Roesef6e495f2006-11-27 17:43:25 +0100407 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
408 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
409 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
410 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
wdenk855a4962004-03-14 18:23:55 +0000411 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
412 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
413 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
414 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
415 break;
416 case 3:
417 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
418 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
419 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
420 bis->bi_phymode[1] = BI_PHYMODE_NONE;
421 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
422 bis->bi_phymode[3] = BI_PHYMODE_NONE;
423 break;
424 case 4:
425 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
426 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
427 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
428 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
429 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
430 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
431 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
432 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
433 break;
434 case 5:
435 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
436 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
437 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
438 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
439 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
440 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
441 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
442 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
443 break;
444 case 6:
445 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
446 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
447 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
wdenk855a4962004-03-14 18:23:55 +0000448 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
449 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
450 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
wdenk855a4962004-03-14 18:23:55 +0000451 break;
452 case 0:
453 default:
454 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
455 rmiifer = 0x0;
456 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
457 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
458 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
459 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
460 break;
461 }
462
463 /* Ensure we setup mdio for this devnum and ONLY this devnum */
464 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
465
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200466 out_be32((void *)ZMII0_FER, zmiifer);
Stefan Roeseff768cb2007-10-31 18:01:24 +0100467 out_be32((void *)RGMII_FER, rmiifer);
wdenk855a4962004-03-14 18:23:55 +0000468
469 return ((int)pfc1);
wdenk855a4962004-03-14 18:23:55 +0000470}
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200471#endif /* CONFIG_440_GX */
wdenk855a4962004-03-14 18:23:55 +0000472
Stefan Roese887e2ec2006-09-07 11:51:23 +0200473#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
474int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
475{
476 unsigned long zmiifer=0x0;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200477 unsigned long pfc1;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200478
Stefan Roesed1c3b272009-09-09 16:25:29 +0200479 mfsdr(SDR0_PFC1, pfc1);
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200480 pfc1 &= SDR0_PFC1_SELECT_MASK;
481
Wolfgang Denk2f152782007-05-05 18:23:11 +0200482 switch (pfc1) {
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200483 case SDR0_PFC1_SELECT_CONFIG_2:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200484 /* 1 x GMII port */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200485 out_be32((void *)ZMII0_FER, 0x00);
Stefan Roese2d834762007-10-23 14:03:17 +0200486 out_be32((void *)RGMII_FER, 0x00000037);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200487 bis->bi_phymode[0] = BI_PHYMODE_GMII;
488 bis->bi_phymode[1] = BI_PHYMODE_NONE;
489 break;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200490 case SDR0_PFC1_SELECT_CONFIG_4:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200491 /* 2 x RGMII ports */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200492 out_be32((void *)ZMII0_FER, 0x00);
Stefan Roese2d834762007-10-23 14:03:17 +0200493 out_be32((void *)RGMII_FER, 0x00000055);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200494 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
495 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
496 break;
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200497 case SDR0_PFC1_SELECT_CONFIG_6:
Stefan Roese887e2ec2006-09-07 11:51:23 +0200498 /* 2 x SMII ports */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200499 out_be32((void *)ZMII0_FER,
Stefan Roese2d834762007-10-23 14:03:17 +0200500 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
501 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
502 out_be32((void *)RGMII_FER, 0x00000000);
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200503 bis->bi_phymode[0] = BI_PHYMODE_SMII;
504 bis->bi_phymode[1] = BI_PHYMODE_SMII;
505 break;
506 case SDR0_PFC1_SELECT_CONFIG_1_2:
507 /* only 1 x MII supported */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200508 out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
Stefan Roese2d834762007-10-23 14:03:17 +0200509 out_be32((void *)RGMII_FER, 0x00000000);
Matthias Fuchs37ed6cd2007-04-24 14:03:45 +0200510 bis->bi_phymode[0] = BI_PHYMODE_MII;
511 bis->bi_phymode[1] = BI_PHYMODE_NONE;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200512 break;
513 default:
514 break;
515 }
516
517 /* Ensure we setup mdio for this devnum and ONLY this devnum */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200518 zmiifer = in_be32((void *)ZMII0_FER);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200519 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200520 out_be32((void *)ZMII0_FER, zmiifer);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200521
522 return ((int)0x0);
523}
524#endif /* CONFIG_440EPX */
525
Stefan Roesedbbd1252007-10-05 17:10:59 +0200526#if defined(CONFIG_405EX)
527int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
528{
Grant Erickson1740c1b2008-07-08 08:35:00 -0700529 u32 rgmiifer = 0;
Stefan Roesedbbd1252007-10-05 17:10:59 +0200530
531 /*
Grant Erickson1740c1b2008-07-08 08:35:00 -0700532 * The 405EX(r)'s RGMII bridge can operate in one of several
533 * modes, only one of which (2 x RGMII) allows the
534 * simultaneous use of both EMACs on the 405EX.
Stefan Roesedbbd1252007-10-05 17:10:59 +0200535 */
Grant Erickson1740c1b2008-07-08 08:35:00 -0700536
537 switch (CONFIG_EMAC_PHY_MODE) {
538
539 case EMAC_PHY_MODE_NONE:
540 /* No ports */
541 rgmiifer |= RGMII_FER_DIS << 0;
542 rgmiifer |= RGMII_FER_DIS << 4;
543 out_be32((void *)RGMII_FER, rgmiifer);
544 bis->bi_phymode[0] = BI_PHYMODE_NONE;
545 bis->bi_phymode[1] = BI_PHYMODE_NONE;
546 break;
547 case EMAC_PHY_MODE_NONE_RGMII:
548 /* 1 x RGMII port on channel 0 */
549 rgmiifer |= RGMII_FER_RGMII << 0;
550 rgmiifer |= RGMII_FER_DIS << 4;
551 out_be32((void *)RGMII_FER, rgmiifer);
552 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
553 bis->bi_phymode[1] = BI_PHYMODE_NONE;
554 break;
555 case EMAC_PHY_MODE_RGMII_NONE:
556 /* 1 x RGMII port on channel 1 */
557 rgmiifer |= RGMII_FER_DIS << 0;
558 rgmiifer |= RGMII_FER_RGMII << 4;
559 out_be32((void *)RGMII_FER, rgmiifer);
560 bis->bi_phymode[0] = BI_PHYMODE_NONE;
561 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
562 break;
563 case EMAC_PHY_MODE_RGMII_RGMII:
Stefan Roesedbbd1252007-10-05 17:10:59 +0200564 /* 2 x RGMII ports */
Grant Erickson1740c1b2008-07-08 08:35:00 -0700565 rgmiifer |= RGMII_FER_RGMII << 0;
566 rgmiifer |= RGMII_FER_RGMII << 4;
567 out_be32((void *)RGMII_FER, rgmiifer);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200568 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
569 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
570 break;
Grant Erickson1740c1b2008-07-08 08:35:00 -0700571 case EMAC_PHY_MODE_NONE_GMII:
572 /* 1 x GMII port on channel 0 */
573 rgmiifer |= RGMII_FER_GMII << 0;
574 rgmiifer |= RGMII_FER_DIS << 4;
575 out_be32((void *)RGMII_FER, rgmiifer);
576 bis->bi_phymode[0] = BI_PHYMODE_GMII;
577 bis->bi_phymode[1] = BI_PHYMODE_NONE;
578 break;
579 case EMAC_PHY_MODE_NONE_MII:
580 /* 1 x MII port on channel 0 */
581 rgmiifer |= RGMII_FER_MII << 0;
582 rgmiifer |= RGMII_FER_DIS << 4;
583 out_be32((void *)RGMII_FER, rgmiifer);
584 bis->bi_phymode[0] = BI_PHYMODE_MII;
585 bis->bi_phymode[1] = BI_PHYMODE_NONE;
586 break;
587 case EMAC_PHY_MODE_GMII_NONE:
588 /* 1 x GMII port on channel 1 */
589 rgmiifer |= RGMII_FER_DIS << 0;
590 rgmiifer |= RGMII_FER_GMII << 4;
591 out_be32((void *)RGMII_FER, rgmiifer);
592 bis->bi_phymode[0] = BI_PHYMODE_NONE;
593 bis->bi_phymode[1] = BI_PHYMODE_GMII;
594 break;
595 case EMAC_PHY_MODE_MII_NONE:
596 /* 1 x MII port on channel 1 */
597 rgmiifer |= RGMII_FER_DIS << 0;
598 rgmiifer |= RGMII_FER_MII << 4;
599 out_be32((void *)RGMII_FER, rgmiifer);
600 bis->bi_phymode[0] = BI_PHYMODE_NONE;
601 bis->bi_phymode[1] = BI_PHYMODE_MII;
Stefan Roesedbbd1252007-10-05 17:10:59 +0200602 break;
603 default:
604 break;
605 }
606
607 /* Ensure we setup mdio for this devnum and ONLY this devnum */
Grant Erickson1740c1b2008-07-08 08:35:00 -0700608 rgmiifer = in_be32((void *)RGMII_FER);
609 rgmiifer |= (1 << (19-devnum));
610 out_be32((void *)RGMII_FER, rgmiifer);
Stefan Roesedbbd1252007-10-05 17:10:59 +0200611
612 return ((int)0x0);
613}
614#endif /* CONFIG_405EX */
615
Stefan Roese8ac41e32008-03-11 15:05:26 +0100616#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
617int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
618{
619 u32 eth_cfg;
620 u32 zmiifer; /* ZMII0_FER reg. */
621 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
622 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100623 int mode;
Stefan Roese8ac41e32008-03-11 15:05:26 +0100624
625 zmiifer = 0;
626 rmiifer = 0;
627 rmiifer1 = 0;
628
Stefan Roese4c9e8552008-03-19 16:20:49 +0100629#if defined(CONFIG_460EX)
630 mode = 9;
Victor Gallardo78d78232008-09-04 23:49:36 -0700631 mfsdr(SDR0_ETH_CFG, eth_cfg);
632 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
633 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
634 mode = 11; /* config SGMII */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100635#else
636 mode = 10;
Victor Gallardo78d78232008-09-04 23:49:36 -0700637 mfsdr(SDR0_ETH_CFG, eth_cfg);
638 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
639 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
640 ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
641 mode = 12; /* config SGMII */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100642#endif
643
Stefan Roese8ac41e32008-03-11 15:05:26 +0100644 /* TODO:
645 * NOTE: 460GT has 2 RGMII bridge cores:
646 * emac0 ------ RGMII0_BASE
647 * |
648 * emac1 -----+
649 *
650 * emac2 ------ RGMII1_BASE
651 * |
652 * emac3 -----+
653 *
654 * 460EX has 1 RGMII bridge core:
655 * and RGMII1_BASE is disabled
656 * emac0 ------ RGMII0_BASE
657 * |
658 * emac1 -----+
659 */
660
661 /*
662 * Right now only 2*RGMII is supported. Please extend when needed.
663 * sr - 2008-02-19
Victor Gallardo78d78232008-09-04 23:49:36 -0700664 * Add SGMII support.
665 * vg - 2008-07-28
Stefan Roese8ac41e32008-03-11 15:05:26 +0100666 */
Stefan Roese4c9e8552008-03-19 16:20:49 +0100667 switch (mode) {
Stefan Roese8ac41e32008-03-11 15:05:26 +0100668 case 1:
669 /* 1 MII - 460EX */
670 /* GMC0 EMAC4_0, ZMII Bridge */
671 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
672 bis->bi_phymode[0] = BI_PHYMODE_MII;
673 bis->bi_phymode[1] = BI_PHYMODE_NONE;
674 bis->bi_phymode[2] = BI_PHYMODE_NONE;
675 bis->bi_phymode[3] = BI_PHYMODE_NONE;
676 break;
677 case 2:
678 /* 2 MII - 460GT */
679 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
680 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
681 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
682 bis->bi_phymode[0] = BI_PHYMODE_MII;
683 bis->bi_phymode[1] = BI_PHYMODE_NONE;
684 bis->bi_phymode[2] = BI_PHYMODE_MII;
685 bis->bi_phymode[3] = BI_PHYMODE_NONE;
686 break;
687 case 3:
688 /* 2 RMII - 460EX */
689 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
690 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
691 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
692 bis->bi_phymode[0] = BI_PHYMODE_RMII;
693 bis->bi_phymode[1] = BI_PHYMODE_RMII;
694 bis->bi_phymode[2] = BI_PHYMODE_NONE;
695 bis->bi_phymode[3] = BI_PHYMODE_NONE;
696 break;
697 case 4:
698 /* 4 RMII - 460GT */
699 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
700 /* ZMII Bridge */
701 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
702 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
703 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
704 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
705 bis->bi_phymode[0] = BI_PHYMODE_RMII;
706 bis->bi_phymode[1] = BI_PHYMODE_RMII;
707 bis->bi_phymode[2] = BI_PHYMODE_RMII;
708 bis->bi_phymode[3] = BI_PHYMODE_RMII;
709 break;
710 case 5:
711 /* 2 SMII - 460EX */
712 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
713 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
714 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
715 bis->bi_phymode[0] = BI_PHYMODE_SMII;
716 bis->bi_phymode[1] = BI_PHYMODE_SMII;
717 bis->bi_phymode[2] = BI_PHYMODE_NONE;
718 bis->bi_phymode[3] = BI_PHYMODE_NONE;
719 break;
720 case 6:
721 /* 4 SMII - 460GT */
722 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
723 /* ZMII Bridge */
724 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
725 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
726 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
727 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
728 bis->bi_phymode[0] = BI_PHYMODE_SMII;
729 bis->bi_phymode[1] = BI_PHYMODE_SMII;
730 bis->bi_phymode[2] = BI_PHYMODE_SMII;
731 bis->bi_phymode[3] = BI_PHYMODE_SMII;
732 break;
733 case 7:
734 /* This is the default mode that we want for board bringup - Maple */
735 /* 1 GMII - 460EX */
736 /* GMC0 EMAC4_0, RGMII Bridge 0 */
737 rmiifer |= RGMII_FER_MDIO(0);
738
739 if (devnum == 0) {
740 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
741 bis->bi_phymode[0] = BI_PHYMODE_GMII;
742 bis->bi_phymode[1] = BI_PHYMODE_NONE;
743 bis->bi_phymode[2] = BI_PHYMODE_NONE;
744 bis->bi_phymode[3] = BI_PHYMODE_NONE;
745 } else {
746 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
747 bis->bi_phymode[0] = BI_PHYMODE_NONE;
748 bis->bi_phymode[1] = BI_PHYMODE_GMII;
749 bis->bi_phymode[2] = BI_PHYMODE_NONE;
750 bis->bi_phymode[3] = BI_PHYMODE_NONE;
751 }
752 break;
753 case 8:
754 /* 2 GMII - 460GT */
755 /* GMC0 EMAC4_0, RGMII Bridge 0 */
756 /* GMC1 EMAC4_2, RGMII Bridge 1 */
757 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
758 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
759 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
760 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
761
762 bis->bi_phymode[0] = BI_PHYMODE_GMII;
763 bis->bi_phymode[1] = BI_PHYMODE_NONE;
764 bis->bi_phymode[2] = BI_PHYMODE_GMII;
765 bis->bi_phymode[3] = BI_PHYMODE_NONE;
766 break;
767 case 9:
768 /* 2 RGMII - 460EX */
769 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
770 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
771 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
772 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
773
774 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
775 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
776 bis->bi_phymode[2] = BI_PHYMODE_NONE;
777 bis->bi_phymode[3] = BI_PHYMODE_NONE;
778 break;
779 case 10:
780 /* 4 RGMII - 460GT */
781 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
782 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
783 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
784 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
785 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
786 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
787 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
788 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
789 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
790 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
791 break;
Victor Gallardo78d78232008-09-04 23:49:36 -0700792 case 11:
793 /* 2 SGMII - 460EX */
794 bis->bi_phymode[0] = BI_PHYMODE_SGMII;
795 bis->bi_phymode[1] = BI_PHYMODE_SGMII;
796 bis->bi_phymode[2] = BI_PHYMODE_NONE;
797 bis->bi_phymode[3] = BI_PHYMODE_NONE;
798 break;
799 case 12:
800 /* 3 SGMII - 460GT */
801 bis->bi_phymode[0] = BI_PHYMODE_SGMII;
802 bis->bi_phymode[1] = BI_PHYMODE_SGMII;
803 bis->bi_phymode[2] = BI_PHYMODE_SGMII;
804 bis->bi_phymode[3] = BI_PHYMODE_NONE;
805 break;
Stefan Roese8ac41e32008-03-11 15:05:26 +0100806 default:
807 break;
808 }
809
810 /* Set EMAC for MDIO */
811 mfsdr(SDR0_ETH_CFG, eth_cfg);
812 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
813 mtsdr(SDR0_ETH_CFG, eth_cfg);
814
815 out_be32((void *)RGMII_FER, rmiifer);
816#if defined(CONFIG_460GT)
817 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
818#endif
819
820 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
821 mfsdr(SDR0_ETH_CFG, eth_cfg);
822 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
823 mtsdr(SDR0_ETH_CFG, eth_cfg);
824
825 return 0;
826}
827#endif /* CONFIG_460EX || CONFIG_460GT */
828
Stefan Roeseff768cb2007-10-31 18:01:24 +0100829static inline void *malloc_aligned(u32 size, u32 align)
830{
831 return (void *)(((u32)malloc(size + align) + align - 1) &
832 ~(align - 1));
833}
834
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200835static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
wdenkba56f622004-02-06 23:19:44 +0000836{
Stefan Roeseff768cb2007-10-31 18:01:24 +0100837 int i;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200838 unsigned long reg = 0;
wdenkba56f622004-02-06 23:19:44 +0000839 unsigned long msr;
840 unsigned long speed;
841 unsigned long duplex;
842 unsigned long failsafe;
843 unsigned mode_reg;
844 unsigned short devnum;
845 unsigned short reg_short;
Stefan Roese887e2ec2006-09-07 11:51:23 +0200846#if defined(CONFIG_440GX) || \
847 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200848 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100849 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200850 defined(CONFIG_405EX)
Felix Radensky0c24dec2009-05-31 20:44:15 +0300851 u32 opbfreq;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200852 sys_info_t sysinfo;
Alessio Centazzo0544c632009-07-11 11:56:06 -0700853#if defined(CONFIG_440GX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200854 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100855 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200856 defined(CONFIG_405EX)
Stefan Roesef0813ab2011-11-15 08:01:58 +0000857 __maybe_unused int ethgroup = -1;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100858#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +0200859#endif
Stefan Roeseff768cb2007-10-31 18:01:24 +0100860 u32 bd_cached;
861 u32 bd_uncached = 0;
Anatolij Gustschin4fae35a2008-02-25 20:54:04 +0100862#ifdef CONFIG_4xx_DCACHE
863 static u32 last_used_ea = 0;
864#endif
Stefan Roesee54ec0f2008-04-03 14:50:34 +0200865#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
866 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
867 defined(CONFIG_405EX)
868 int rgmii_channel;
869#endif
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200870
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200871 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +0000872
873 /* before doing anything, figure out if we have a MAC address */
874 /* if not, bail */
Stefan Roese4f92ac32005-10-10 17:43:58 +0200875 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
876 printf("ERROR: ethaddr not set!\n");
wdenkba56f622004-02-06 23:19:44 +0000877 return -1;
Stefan Roese4f92ac32005-10-10 17:43:58 +0200878 }
wdenkba56f622004-02-06 23:19:44 +0000879
Stefan Roese887e2ec2006-09-07 11:51:23 +0200880#if defined(CONFIG_440GX) || \
881 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200882 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100883 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200884 defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +0000885 /* Need to get the OPB frequency so we can access the PHY */
886 get_sys_info (&sysinfo);
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200887#endif
wdenkba56f622004-02-06 23:19:44 +0000888
wdenkba56f622004-02-06 23:19:44 +0000889 msr = mfmsr ();
890 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
891
892 devnum = hw_p->devnum;
893
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200894#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +0000895 /* AS.HARNOIS
896 * We should have :
Wolfgang Denk265817c2005-09-25 00:53:22 +0200897 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
wdenkba56f622004-02-06 23:19:44 +0000898 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
899 * is possible that new packets (without relationship with
900 * current transfer) have got the time to arrived before
901 * netloop calls eth_halt
902 */
903 printf ("About preceeding transfer (eth%d):\n"
904 "- Sent packet number %d\n"
905 "- Received packet number %d\n"
906 "- Handled packet number %d\n",
907 hw_p->devnum,
908 hw_p->stats.pkts_tx,
909 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
910
911 hw_p->stats.pkts_tx = 0;
912 hw_p->stats.pkts_rx = 0;
913 hw_p->stats.pkts_handled = 0;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200914 hw_p->print_speed = 1; /* print speed message again next time */
wdenkba56f622004-02-06 23:19:44 +0000915#endif
916
Wolfgang Denk265817c2005-09-25 00:53:22 +0200917 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
918 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
wdenkba56f622004-02-06 23:19:44 +0000919
920 hw_p->rx_slot = 0; /* MAL Receive Slot */
921 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
922 hw_p->rx_u_index = 0; /* Receive User Queue Index */
923
924 hw_p->tx_slot = 0; /* MAL Transmit Slot */
925 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
926 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
927
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200928#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
wdenkba56f622004-02-06 23:19:44 +0000929 /* set RMII mode */
930 /* NOTE: 440GX spec states that mode is mutually exclusive */
931 /* NOTE: Therefore, disable all other EMACS, since we handle */
932 /* NOTE: only one emac at a time */
933 reg = 0;
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200934 out_be32((void *)ZMII0_FER, 0);
wdenkba56f622004-02-06 23:19:44 +0000935 udelay (100);
wdenkba56f622004-02-06 23:19:44 +0000936
Stefan Roese8ac41e32008-03-11 15:05:26 +0100937#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200938 out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
Stefan Roese8ac41e32008-03-11 15:05:26 +0100939#elif defined(CONFIG_440GX) || \
940 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
941 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200942 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
wdenk0e6d7982004-03-14 00:07:33 +0000943#endif
Stefan Roesec57c7982005-08-11 17:56:56 +0200944
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200945 out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100946#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
Stefan Roesedbbd1252007-10-05 17:10:59 +0200947#if defined(CONFIG_405EX)
948 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
949#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200950
Stefan Roese8ac41e32008-03-11 15:05:26 +0100951 sync();
wdenk0e6d7982004-03-14 00:07:33 +0000952
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200953 /* provide clocks for EMAC internal loopback */
Stefan Roese8ac41e32008-03-11 15:05:26 +0100954 emac_loopback_enable(hw_p);
wdenk0e6d7982004-03-14 00:07:33 +0000955
Stefan Roese8ac41e32008-03-11 15:05:26 +0100956 /* EMAC RESET */
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200957 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
wdenkba56f622004-02-06 23:19:44 +0000958
Stefan Roese8ac41e32008-03-11 15:05:26 +0100959 /* remove clocks for EMAC internal loopback */
960 emac_loopback_disable(hw_p);
961
wdenkba56f622004-02-06 23:19:44 +0000962 failsafe = 1000;
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200963 while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
wdenkba56f622004-02-06 23:19:44 +0000964 udelay (1000);
965 failsafe--;
966 }
Stefan Roese887e2ec2006-09-07 11:51:23 +0200967 if (failsafe <= 0)
968 printf("\nProblem resetting EMAC!\n");
wdenkba56f622004-02-06 23:19:44 +0000969
Stefan Roese887e2ec2006-09-07 11:51:23 +0200970#if defined(CONFIG_440GX) || \
971 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200972 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +0100973 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200974 defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +0000975 /* Whack the M1 register */
976 mode_reg = 0x0;
977 mode_reg &= ~0x00000038;
Felix Radensky0c24dec2009-05-31 20:44:15 +0300978 opbfreq = sysinfo.freqOPB / 1000000;
979 if (opbfreq <= 50);
980 else if (opbfreq <= 66)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200981 mode_reg |= EMAC_MR1_OBCI_66;
Felix Radensky0c24dec2009-05-31 20:44:15 +0300982 else if (opbfreq <= 83)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200983 mode_reg |= EMAC_MR1_OBCI_83;
Felix Radensky0c24dec2009-05-31 20:44:15 +0300984 else if (opbfreq <= 100)
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200985 mode_reg |= EMAC_MR1_OBCI_100;
wdenkba56f622004-02-06 23:19:44 +0000986 else
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200987 mode_reg |= EMAC_MR1_OBCI_GT100;
wdenkba56f622004-02-06 23:19:44 +0000988
Niklaus Gigerddc922f2009-10-04 20:04:20 +0200989 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100990#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
wdenkba56f622004-02-06 23:19:44 +0000991
Victor Gallardo78d78232008-09-04 23:49:36 -0700992#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
993 defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
994 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
995 /*
996 * In SGMII mode, GPCS access is needed for
997 * communication with the internal SGMII SerDes.
998 */
999 switch (devnum) {
1000#if defined(CONFIG_GPCS_PHY_ADDR)
1001 case 0:
1002 reg = CONFIG_GPCS_PHY_ADDR;
1003 break;
1004#endif
1005#if defined(CONFIG_GPCS_PHY1_ADDR)
1006 case 1:
1007 reg = CONFIG_GPCS_PHY1_ADDR;
1008 break;
1009#endif
1010#if defined(CONFIG_GPCS_PHY2_ADDR)
1011 case 2:
1012 reg = CONFIG_GPCS_PHY2_ADDR;
1013 break;
1014#endif
1015#if defined(CONFIG_GPCS_PHY3_ADDR)
1016 case 3:
1017 reg = CONFIG_GPCS_PHY3_ADDR;
1018 break;
1019#endif
1020 }
1021
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001022 mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
1023 mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
1024 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
Victor Gallardo78d78232008-09-04 23:49:36 -07001025
1026 /* Configure GPCS interface to recommended setting for SGMII */
1027 miiphy_reset(dev->name, reg);
1028 miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
1029 miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
1030 miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
1031 }
1032#endif /* defined(CONFIG_GPCS_PHY_ADDR) */
1033
wdenkba56f622004-02-06 23:19:44 +00001034 /* wait for PHY to complete auto negotiation */
1035 reg_short = 0;
wdenkba56f622004-02-06 23:19:44 +00001036 switch (devnum) {
1037 case 0:
1038 reg = CONFIG_PHY_ADDR;
1039 break;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001040#if defined (CONFIG_PHY1_ADDR)
wdenkba56f622004-02-06 23:19:44 +00001041 case 1:
1042 reg = CONFIG_PHY1_ADDR;
1043 break;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001044#endif
Stefan Roese4c9e8552008-03-19 16:20:49 +01001045#if defined (CONFIG_PHY2_ADDR)
wdenkba56f622004-02-06 23:19:44 +00001046 case 2:
1047 reg = CONFIG_PHY2_ADDR;
1048 break;
Stefan Roese4c9e8552008-03-19 16:20:49 +01001049#endif
1050#if defined (CONFIG_PHY3_ADDR)
wdenkba56f622004-02-06 23:19:44 +00001051 case 3:
1052 reg = CONFIG_PHY3_ADDR;
1053 break;
1054#endif
1055 default:
1056 reg = CONFIG_PHY_ADDR;
1057 break;
1058 }
1059
wdenk3c74e322004-02-22 23:46:08 +00001060 bis->bi_phynum[devnum] = reg;
1061
Victor Gallardo78d78232008-09-04 23:49:36 -07001062 if (reg == CONFIG_FIXED_PHY)
1063 goto get_speed;
1064
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001065#if defined(CONFIG_PHY_RESET)
wdenka06752e2004-09-29 22:43:59 +00001066 /*
1067 * Reset the phy, only if its the first time through
1068 * otherwise, just check the speeds & feeds
1069 */
1070 if (hw_p->first_init == 0) {
Stefan Roeseec0c2ec2006-11-27 14:46:06 +01001071#if defined(CONFIG_M88E1111_PHY)
Stefan Roese887e2ec2006-09-07 11:51:23 +02001072 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
1073 miiphy_write (dev->name, reg, 0x18, 0x4101);
1074 miiphy_write (dev->name, reg, 0x09, 0x0e00);
1075 miiphy_write (dev->name, reg, 0x04, 0x01e1);
Stefan Roeseca080542010-06-29 09:23:53 +02001076#if defined(CONFIG_M88E1111_DISABLE_FIBER)
1077 miiphy_read(dev->name, reg, 0x1b, &reg_short);
1078 reg_short |= 0x8000;
1079 miiphy_write(dev->name, reg, 0x1b, reg_short);
1080#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +02001081#endif
Victor Gallardo78d78232008-09-04 23:49:36 -07001082#if defined(CONFIG_M88E1112_PHY)
1083 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
1084 /*
1085 * Marvell 88E1112 PHY needs to have the SGMII MAC
1086 * interace (page 2) properly configured to
1087 * communicate with the 460EX/GT GPCS interface.
1088 */
1089
1090 /* Set access to Page 2 */
1091 miiphy_write(dev->name, reg, 0x16, 0x0002);
1092
1093 miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
1094 miiphy_read(dev->name, reg, 0x1a, &reg_short);
1095 reg_short |= 0x8000; /* bypass Auto-Negotiation */
1096 miiphy_write(dev->name, reg, 0x1a, reg_short);
1097 miiphy_reset(dev->name, reg); /* reset MAC interface */
1098
1099 /* Reset access to Page 0 */
1100 miiphy_write(dev->name, reg, 0x16, 0x0000);
1101 }
1102#endif /* defined(CONFIG_M88E1112_PHY) */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001103 miiphy_reset (dev->name, reg);
wdenkba56f622004-02-06 23:19:44 +00001104
Stefan Roese887e2ec2006-09-07 11:51:23 +02001105#if defined(CONFIG_440GX) || \
1106 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +01001107 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02001108 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +02001109
wdenk0e6d7982004-03-14 00:07:33 +00001110#if defined(CONFIG_CIS8201_PHY)
wdenkfc1cfcd2004-04-25 15:41:35 +00001111 /*
Stefan Roese17f50f222005-08-04 17:09:16 +02001112 * Cicada 8201 PHY needs to have an extended register whacked
1113 * for RGMII mode.
wdenkfc1cfcd2004-04-25 15:41:35 +00001114 */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001115 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
Stefan Roeseb79316f2005-08-15 12:31:23 +02001116#if defined(CONFIG_CIS8201_SHORT_ETCH)
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001117 miiphy_write (dev->name, reg, 23, 0x1300);
Stefan Roeseb79316f2005-08-15 12:31:23 +02001118#else
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001119 miiphy_write (dev->name, reg, 23, 0x1000);
Stefan Roeseb79316f2005-08-15 12:31:23 +02001120#endif
Stefan Roese17f50f222005-08-04 17:09:16 +02001121 /*
1122 * Vitesse VSC8201/Cicada CIS8201 errata:
1123 * Interoperability problem with Intel 82547EI phys
1124 * This work around (provided by Vitesse) changes
1125 * the default timer convergence from 8ms to 12ms
1126 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001127 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1128 miiphy_write (dev->name, reg, 0x08, 0x0200);
1129 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
1130 miiphy_write (dev->name, reg, 0x02, 0x0004);
1131 miiphy_write (dev->name, reg, 0x01, 0x0671);
1132 miiphy_write (dev->name, reg, 0x00, 0x8fae);
1133 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1134 miiphy_write (dev->name, reg, 0x08, 0x0000);
1135 miiphy_write (dev->name, reg, 0x1f, 0x0000);
Stefan Roese17f50f222005-08-04 17:09:16 +02001136 /* end Vitesse/Cicada errata */
1137 }
Stefan Roese6ca86462008-09-05 14:11:40 +02001138#endif /* defined(CONFIG_CIS8201_PHY) */
Stefan Roese5fb692c2007-01-18 10:25:34 +01001139
1140#if defined(CONFIG_ET1011C_PHY)
1141 /*
1142 * Agere ET1011c PHY needs to have an extended register whacked
1143 * for RGMII mode.
1144 */
1145 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
1146 miiphy_read (dev->name, reg, 0x16, &reg_short);
1147 reg_short &= ~(0x7);
1148 reg_short |= 0x6; /* RGMII DLL Delay*/
1149 miiphy_write (dev->name, reg, 0x16, reg_short);
1150
1151 miiphy_read (dev->name, reg, 0x17, &reg_short);
1152 reg_short &= ~(0x40);
1153 miiphy_write (dev->name, reg, 0x17, reg_short);
1154
1155 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
1156 }
Stefan Roese6ca86462008-09-05 14:11:40 +02001157#endif /* defined(CONFIG_ET1011C_PHY) */
Stefan Roese5fb692c2007-01-18 10:25:34 +01001158
Stefan Roese6ca86462008-09-05 14:11:40 +02001159#endif /* defined(CONFIG_440GX) ... */
wdenka06752e2004-09-29 22:43:59 +00001160 /* Start/Restart autonegotiation */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001161 phy_setup_aneg (dev->name, reg);
wdenka06752e2004-09-29 22:43:59 +00001162 udelay (1000);
1163 }
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001164#endif /* defined(CONFIG_PHY_RESET) */
wdenkba56f622004-02-06 23:19:44 +00001165
Mike Frysinger8ef583a2010-12-23 15:40:12 -05001166 miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
wdenkba56f622004-02-06 23:19:44 +00001167
1168 /*
wdenk0e6d7982004-03-14 00:07:33 +00001169 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
wdenkba56f622004-02-06 23:19:44 +00001170 */
Mike Frysinger8ef583a2010-12-23 15:40:12 -05001171 if ((reg_short & BMSR_ANEGCAPABLE)
1172 && !(reg_short & BMSR_ANEGCOMPLETE)) {
wdenkba56f622004-02-06 23:19:44 +00001173 puts ("Waiting for PHY auto negotiation to complete");
1174 i = 0;
Mike Frysinger8ef583a2010-12-23 15:40:12 -05001175 while (!(reg_short & BMSR_ANEGCOMPLETE)) {
wdenkba56f622004-02-06 23:19:44 +00001176 /*
1177 * Timeout reached ?
1178 */
1179 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
1180 puts (" TIMEOUT !\n");
1181 break;
1182 }
1183
1184 if ((i++ % 1000) == 0) {
1185 putc ('.');
1186 }
1187 udelay (1000); /* 1 ms */
Mike Frysinger8ef583a2010-12-23 15:40:12 -05001188 miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
wdenkba56f622004-02-06 23:19:44 +00001189 }
1190 puts (" done\n");
1191 udelay (500000); /* another 500 ms (results in faster booting) */
1192 }
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001193
Victor Gallardo78d78232008-09-04 23:49:36 -07001194get_speed:
1195 if (reg == CONFIG_FIXED_PHY) {
1196 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
1197 if (devnum == fixed_phy_port[i].devnum) {
1198 speed = fixed_phy_port[i].speed;
1199 duplex = fixed_phy_port[i].duplex;
1200 break;
1201 }
1202 }
1203
1204 if (i == ARRAY_SIZE(fixed_phy_port)) {
1205 printf("ERROR: PHY (%s) not configured correctly!\n",
1206 dev->name);
1207 return -1;
1208 }
1209 } else {
1210 speed = miiphy_speed(dev->name, reg);
1211 duplex = miiphy_duplex(dev->name, reg);
1212 }
wdenkba56f622004-02-06 23:19:44 +00001213
1214 if (hw_p->print_speed) {
1215 hw_p->print_speed = 0;
Stefan Roese5fb692c2007-01-18 10:25:34 +01001216 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
1217 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
1218 hw_p->devnum);
wdenkba56f622004-02-06 23:19:44 +00001219 }
1220
Stefan Roese8ac41e32008-03-11 15:05:26 +01001221#if defined(CONFIG_440) && \
1222 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
1223 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1224 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
Stefan Roese846b0dd2005-08-08 12:42:22 +02001225#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001226 mfsdr(SDR0_MFR, reg);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001227 if (speed == 100) {
1228 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
1229 } else {
1230 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1231 }
Stefan Roesed1c3b272009-09-09 16:25:29 +02001232 mtsdr(SDR0_MFR, reg);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001233#endif
Stefan Roesec57c7982005-08-11 17:56:56 +02001234
wdenkba56f622004-02-06 23:19:44 +00001235 /* Set ZMII/RGMII speed according to the phy link speed */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001236 reg = in_be32((void *)ZMII0_SSR);
wdenk855a4962004-03-14 18:23:55 +00001237 if ( (speed == 100) || (speed == 1000) )
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001238 out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
wdenkba56f622004-02-06 23:19:44 +00001239 else
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001240 out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
wdenkba56f622004-02-06 23:19:44 +00001241
1242 if ((devnum == 2) || (devnum == 3)) {
1243 if (speed == 1000)
1244 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1245 else if (speed == 100)
1246 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001247 else if (speed == 10)
wdenkba56f622004-02-06 23:19:44 +00001248 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001249 else {
1250 printf("Error in RGMII Speed\n");
1251 return -1;
1252 }
Stefan Roeseff768cb2007-10-31 18:01:24 +01001253 out_be32((void *)RGMII_SSR, reg);
wdenkba56f622004-02-06 23:19:44 +00001254 }
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001255#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
wdenkba56f622004-02-06 23:19:44 +00001256
Stefan Roesedbbd1252007-10-05 17:10:59 +02001257#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +01001258 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02001259 defined(CONFIG_405EX)
Stefan Roesee54ec0f2008-04-03 14:50:34 +02001260 if (devnum >= 2)
1261 rgmii_channel = devnum - 2;
1262 else
1263 rgmii_channel = devnum;
1264
Stefan Roese887e2ec2006-09-07 11:51:23 +02001265 if (speed == 1000)
Stefan Roesee54ec0f2008-04-03 14:50:34 +02001266 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001267 else if (speed == 100)
Stefan Roesee54ec0f2008-04-03 14:50:34 +02001268 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001269 else if (speed == 10)
Stefan Roesee54ec0f2008-04-03 14:50:34 +02001270 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
Stefan Roese887e2ec2006-09-07 11:51:23 +02001271 else {
1272 printf("Error in RGMII Speed\n");
1273 return -1;
1274 }
Stefan Roese2d834762007-10-23 14:03:17 +02001275 out_be32((void *)RGMII_SSR, reg);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001276#if defined(CONFIG_460GT)
1277 if ((devnum == 2) || (devnum == 3))
1278 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
1279#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +02001280#endif
1281
wdenkba56f622004-02-06 23:19:44 +00001282 /* set the Mal configuration reg */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001283#if defined(CONFIG_440GX) || \
1284 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02001285 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +01001286 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02001287 defined(CONFIG_405EX)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001288 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
Stefan Roese17f50f222005-08-04 17:09:16 +02001289 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
1290#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001291 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
wdenkba56f622004-02-06 23:19:44 +00001292 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
Stefan Roese17f50f222005-08-04 17:09:16 +02001293 if (get_pvr() == PVR_440GP_RB) {
Stefan Roesed1c3b272009-09-09 16:25:29 +02001294 mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
Stefan Roese17f50f222005-08-04 17:09:16 +02001295 }
1296#endif
wdenkba56f622004-02-06 23:19:44 +00001297
wdenkba56f622004-02-06 23:19:44 +00001298 /*
1299 * Malloc MAL buffer desciptors, make sure they are
1300 * aligned on cache line boundary size
1301 * (401/403/IOP480 = 16, 405 = 32)
1302 * and doesn't cross cache block boundaries.
1303 */
Stefan Roeseff768cb2007-10-31 18:01:24 +01001304 if (hw_p->first_init == 0) {
1305 debug("*** Allocating descriptor memory ***\n");
wdenkba56f622004-02-06 23:19:44 +00001306
Stefan Roeseff768cb2007-10-31 18:01:24 +01001307 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
1308 if (!bd_cached) {
Stefan Roeseb0021442008-07-10 09:58:06 +02001309 printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
Stefan Roeseff768cb2007-10-31 18:01:24 +01001310 return -1;
1311 }
Stefan Roeseb79316f2005-08-15 12:31:23 +02001312
Stefan Roeseff768cb2007-10-31 18:01:24 +01001313#ifdef CONFIG_4xx_DCACHE
Matthias Fuchsba79fde2007-12-14 11:19:56 +01001314 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
Anatolij Gustschin4fae35a2008-02-25 20:54:04 +01001315 if (!last_used_ea)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001316#if defined(CONFIG_SYS_MEM_TOP_HIDE)
1317 bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
Anatolij Gustschin5e3dca52008-04-17 18:18:00 +02001318#else
Anatolij Gustschin4fae35a2008-02-25 20:54:04 +01001319 bd_uncached = bis->bi_memsize;
Anatolij Gustschin5e3dca52008-04-17 18:18:00 +02001320#endif
Anatolij Gustschin4fae35a2008-02-25 20:54:04 +01001321 else
1322 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
1323
1324 last_used_ea = bd_uncached;
Stefan Roeseff768cb2007-10-31 18:01:24 +01001325 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
1326 TLB_WORD2_I_ENABLE);
1327#else
1328 bd_uncached = bd_cached;
1329#endif
1330 hw_p->tx_phys = bd_cached;
1331 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
1332 hw_p->tx = (mal_desc_t *)(bd_uncached);
1333 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
Marek Vasutc97e74a2011-10-21 14:17:13 +00001334 debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
wdenkba56f622004-02-06 23:19:44 +00001335 }
1336
1337 for (i = 0; i < NUM_TX_BUFF; i++) {
1338 hw_p->tx[i].ctrl = 0;
1339 hw_p->tx[i].data_len = 0;
Stefan Roeseff768cb2007-10-31 18:01:24 +01001340 if (hw_p->first_init == 0)
1341 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
1342 L1_CACHE_BYTES);
wdenkba56f622004-02-06 23:19:44 +00001343 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
1344 if ((NUM_TX_BUFF - 1) == i)
1345 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
1346 hw_p->tx_run[i] = -1;
Marek Vasutc97e74a2011-10-21 14:17:13 +00001347 debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
wdenkba56f622004-02-06 23:19:44 +00001348 }
1349
1350 for (i = 0; i < NUM_RX_BUFF; i++) {
1351 hw_p->rx[i].ctrl = 0;
1352 hw_p->rx[i].data_len = 0;
Stefan Roeseff768cb2007-10-31 18:01:24 +01001353 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
wdenkba56f622004-02-06 23:19:44 +00001354 if ((NUM_RX_BUFF - 1) == i)
1355 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
1356 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
1357 hw_p->rx_ready[i] = -1;
Marek Vasutc97e74a2011-10-21 14:17:13 +00001358 debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
wdenkba56f622004-02-06 23:19:44 +00001359 }
1360
1361 reg = 0x00000000;
1362
1363 reg |= dev->enetaddr[0]; /* set high address */
1364 reg = reg << 8;
1365 reg |= dev->enetaddr[1];
1366
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001367 out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
wdenkba56f622004-02-06 23:19:44 +00001368
1369 reg = 0x00000000;
1370 reg |= dev->enetaddr[2]; /* set low address */
1371 reg = reg << 8;
1372 reg |= dev->enetaddr[3];
1373 reg = reg << 8;
1374 reg |= dev->enetaddr[4];
1375 reg = reg << 8;
1376 reg |= dev->enetaddr[5];
1377
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001378 out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
wdenkba56f622004-02-06 23:19:44 +00001379
1380 switch (devnum) {
1381 case 1:
1382 /* setup MAL tx & rx channel pointers */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001383#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001384 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001385#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001386 mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001387#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001388#if defined(CONFIG_440)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001389 mtdcr (MAL0_TXBADDR, 0x0);
1390 mtdcr (MAL0_RXBADDR, 0x0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001391#endif
Stefan Roese8ac41e32008-03-11 15:05:26 +01001392
1393#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001394 mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001395 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001396 mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001397#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001398 mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +00001399 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001400 mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001401#endif
wdenkba56f622004-02-06 23:19:44 +00001402 break;
Stefan Roese846b0dd2005-08-08 12:42:22 +02001403#if defined (CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001404 case 2:
1405 /* setup MAL tx & rx channel pointers */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001406 mtdcr (MAL0_TXBADDR, 0x0);
1407 mtdcr (MAL0_RXBADDR, 0x0);
1408 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
1409 mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +00001410 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001411 mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
wdenkba56f622004-02-06 23:19:44 +00001412 break;
1413 case 3:
1414 /* setup MAL tx & rx channel pointers */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001415 mtdcr (MAL0_TXBADDR, 0x0);
1416 mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
1417 mtdcr (MAL0_RXBADDR, 0x0);
1418 mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +00001419 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001420 mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
wdenkba56f622004-02-06 23:19:44 +00001421 break;
Stefan Roesec57c7982005-08-11 17:56:56 +02001422#endif /* CONFIG_440GX */
Stefan Roese4c9e8552008-03-19 16:20:49 +01001423#if defined (CONFIG_460GT)
1424 case 2:
1425 /* setup MAL tx & rx channel pointers */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001426 mtdcr (MAL0_TXBADDR, 0x0);
1427 mtdcr (MAL0_RXBADDR, 0x0);
1428 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
1429 mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001430 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001431 mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001432 break;
1433 case 3:
1434 /* setup MAL tx & rx channel pointers */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001435 mtdcr (MAL0_TXBADDR, 0x0);
1436 mtdcr (MAL0_RXBADDR, 0x0);
1437 mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
1438 mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001439 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001440 mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001441 break;
1442#endif /* CONFIG_460GT */
wdenkba56f622004-02-06 23:19:44 +00001443 case 0:
1444 default:
1445 /* setup MAL tx & rx channel pointers */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001446#if defined(CONFIG_440)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001447 mtdcr (MAL0_TXBADDR, 0x0);
1448 mtdcr (MAL0_RXBADDR, 0x0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001449#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +02001450 mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
1451 mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
wdenkba56f622004-02-06 23:19:44 +00001452 /* set RX buffer size */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001453 mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
wdenkba56f622004-02-06 23:19:44 +00001454 break;
1455 }
1456
1457 /* Enable MAL transmit and receive channels */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001458#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesed1c3b272009-09-09 16:25:29 +02001459 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
Stefan Roesec157d8e2005-08-01 16:41:48 +02001460#else
Stefan Roesed1c3b272009-09-09 16:25:29 +02001461 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
Stefan Roesec157d8e2005-08-01 16:41:48 +02001462#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +02001463 mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
wdenkba56f622004-02-06 23:19:44 +00001464
1465 /* set transmit enable & receive enable */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001466 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
wdenkba56f622004-02-06 23:19:44 +00001467
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001468 mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
Stefan Roese76957cb2008-03-01 12:11:40 +01001469
1470 /* set rx-/tx-fifo size */
1471 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
wdenkba56f622004-02-06 23:19:44 +00001472
1473 /* set speed */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001474 if (speed == _1000BASET) {
Stefan Roese5e7abce2010-09-11 09:31:43 +02001475#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001476 unsigned long pfc1;
Stefan Roese887e2ec2006-09-07 11:51:23 +02001477
Stefan Roesed1c3b272009-09-09 16:25:29 +02001478 mfsdr (SDR0_PFC1, pfc1);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001479 pfc1 |= SDR0_PFC1_EM_1000;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001480 mtsdr (SDR0_PFC1, pfc1);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001481#endif
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001482 mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001483 } else if (speed == _100BASET)
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001484 mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
wdenkba56f622004-02-06 23:19:44 +00001485 else
1486 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1487 if (duplex == FULL)
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001488 mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
wdenkba56f622004-02-06 23:19:44 +00001489
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001490 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
wdenkba56f622004-02-06 23:19:44 +00001491
1492 /* Enable broadcast and indvidual address */
1493 /* TBS: enabling runts as some misbehaved nics will send runts */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001494 out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
wdenkba56f622004-02-06 23:19:44 +00001495
1496 /* we probably need to set the tx mode1 reg? maybe at tx time */
1497
1498 /* set transmit request threshold register */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001499 out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
wdenkba56f622004-02-06 23:19:44 +00001500
Wolfgang Denk265817c2005-09-25 00:53:22 +02001501 /* set receive low/high water mark register */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001502#if defined(CONFIG_440)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001503 /* 440s has a 64 byte burst length */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001504 out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001505#else
1506 /* 405s have a 16 byte burst length */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001507 out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001508#endif /* defined(CONFIG_440) */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001509 out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
wdenkba56f622004-02-06 23:19:44 +00001510
1511 /* Set fifo limit entry in tx mode 0 */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001512 out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
wdenkba56f622004-02-06 23:19:44 +00001513 /* Frame gap set */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001514 out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
wdenkba56f622004-02-06 23:19:44 +00001515
1516 /* Set EMAC IER */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001517 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
wdenkba56f622004-02-06 23:19:44 +00001518 if (speed == _100BASET)
1519 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1520
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001521 out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1522 out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
wdenkba56f622004-02-06 23:19:44 +00001523
1524 if (hw_p->first_init == 0) {
1525 /*
1526 * Connect interrupt service routines
1527 */
Stefan Roesedbbd1252007-10-05 17:10:59 +02001528 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1529 (interrupt_handler_t *) enetInt, dev);
wdenkba56f622004-02-06 23:19:44 +00001530 }
wdenkba56f622004-02-06 23:19:44 +00001531
1532 mtmsr (msr); /* enable interrupts again */
1533
1534 hw_p->bis = bis;
1535 hw_p->first_init = 1;
1536
Stefan Roese802b7692008-01-08 18:39:30 +01001537 return 0;
wdenkba56f622004-02-06 23:19:44 +00001538}
1539
1540
Anatolij Gustschin3f9eb612012-05-21 10:48:18 +00001541static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len)
wdenkba56f622004-02-06 23:19:44 +00001542{
1543 struct enet_frame *ef_ptr;
1544 ulong time_start, time_now;
1545 unsigned long temp_txm0;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001546 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001547
1548 ef_ptr = (struct enet_frame *) ptr;
1549
1550 /*-----------------------------------------------------------------------+
1551 * Copy in our address into the frame.
1552 *-----------------------------------------------------------------------*/
1553 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1554
1555 /*-----------------------------------------------------------------------+
1556 * If frame is too long or too short, modify length.
1557 *-----------------------------------------------------------------------*/
1558 /* TBS: where does the fragment go???? */
1559 if (len > ENET_MAX_MTU)
1560 len = ENET_MAX_MTU;
1561
1562 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1563 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
Matthias Fuchsba79fde2007-12-14 11:19:56 +01001564 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
wdenkba56f622004-02-06 23:19:44 +00001565
1566 /*-----------------------------------------------------------------------+
1567 * set TX Buffer busy, and send it
1568 *-----------------------------------------------------------------------*/
1569 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1570 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1571 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1572 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1573 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1574
1575 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1576 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1577
Stefan Roese8ac41e32008-03-11 15:05:26 +01001578 sync();
wdenkba56f622004-02-06 23:19:44 +00001579
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001580 out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
1581 in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001582#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001583 hw_p->stats.pkts_tx++;
1584#endif
1585
1586 /*-----------------------------------------------------------------------+
1587 * poll unitl the packet is sent and then make sure it is OK
1588 *-----------------------------------------------------------------------*/
1589 time_start = get_timer (0);
1590 while (1) {
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001591 temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
wdenkba56f622004-02-06 23:19:44 +00001592 /* loop until either TINT turns on or 3 seconds elapse */
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001593 if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
wdenkba56f622004-02-06 23:19:44 +00001594 /* transmit is done, so now check for errors
1595 * If there is an error, an interrupt should
1596 * happen when we return
1597 */
1598 time_now = get_timer (0);
1599 if ((time_now - time_start) > 3000) {
1600 return (-1);
1601 }
1602 } else {
1603 return (len);
1604 }
1605 }
1606}
1607
wdenkba56f622004-02-06 23:19:44 +00001608int enetInt (struct eth_device *dev)
1609{
1610 int serviced;
1611 int rc = -1; /* default to not us */
Stefan Roesed1631fe2008-06-26 13:40:57 +02001612 u32 mal_isr;
1613 u32 emac_isr = 0;
1614 u32 mal_eob;
1615 u32 uic_mal;
1616 u32 uic_mal_err;
1617 u32 uic_emac;
1618 u32 uic_emac_b;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001619 EMAC_4XX_HW_PST hw_p;
wdenkba56f622004-02-06 23:19:44 +00001620
1621 /*
1622 * Because the mal is generic, we need to get the current
1623 * eth device
1624 */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001625 dev = eth_get_dev();
wdenkba56f622004-02-06 23:19:44 +00001626
1627 hw_p = dev->priv;
1628
wdenkba56f622004-02-06 23:19:44 +00001629 /* enter loop that stays in interrupt code until nothing to service */
1630 do {
1631 serviced = 0;
1632
Stefan Roesed1631fe2008-06-26 13:40:57 +02001633 uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
1634 uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
1635 uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
1636 uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
Stefan Roese887e2ec2006-09-07 11:51:23 +02001637
Stefan Roesed1631fe2008-06-26 13:40:57 +02001638 if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
1639 && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
1640 && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
wdenkba56f622004-02-06 23:19:44 +00001641 /* not for us */
1642 return (rc);
1643 }
Stefan Roesed1631fe2008-06-26 13:40:57 +02001644
wdenkba56f622004-02-06 23:19:44 +00001645 /* get and clear controller status interrupts */
Stefan Roesed1631fe2008-06-26 13:40:57 +02001646 /* look at MAL and EMAC error interrupts */
1647 if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
1648 /* we have a MAL error interrupt */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001649 mal_isr = mfdcr(MAL0_ESR);
Stefan Roesed1631fe2008-06-26 13:40:57 +02001650 mal_err(dev, mal_isr, uic_mal_err,
1651 MAL_UIC_DEF, MAL_UIC_ERR);
1652
1653 /* clear MAL error interrupt status bits */
1654 mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
1655 UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
1656
1657 return -1;
wdenkba56f622004-02-06 23:19:44 +00001658 }
1659
Stefan Roesed1631fe2008-06-26 13:40:57 +02001660 /* look for EMAC errors */
1661 if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001662 emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
Stefan Roesed1631fe2008-06-26 13:40:57 +02001663 emac_err(dev, emac_isr);
wdenkba56f622004-02-06 23:19:44 +00001664
Stefan Roesed1631fe2008-06-26 13:40:57 +02001665 /* clear EMAC error interrupt status bits */
1666 mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
1667 mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
wdenkba56f622004-02-06 23:19:44 +00001668
Stefan Roesed1631fe2008-06-26 13:40:57 +02001669 return -1;
wdenkba56f622004-02-06 23:19:44 +00001670 }
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001671
wdenkba56f622004-02-06 23:19:44 +00001672 /* handle MAX TX EOB interrupt from a tx */
Stefan Roesed1631fe2008-06-26 13:40:57 +02001673 if (uic_mal & UIC_MAL_TXEOB) {
1674 /* clear MAL interrupt status bits */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001675 mal_eob = mfdcr(MAL0_TXEOBISR);
1676 mtdcr(MAL0_TXEOBISR, mal_eob);
Stefan Roesed1631fe2008-06-26 13:40:57 +02001677 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
1678
1679 /* indicate that we serviced an interrupt */
1680 serviced = 1;
1681 rc = 0;
wdenkba56f622004-02-06 23:19:44 +00001682 }
Stefan Roesed1631fe2008-06-26 13:40:57 +02001683
Mike Williams16263082011-07-22 04:01:30 +00001684 /* handle MAL RX EOB interrupt from a receive */
Stefan Roesed1631fe2008-06-26 13:40:57 +02001685 /* check for EOB on valid channels */
1686 if (uic_mal & UIC_MAL_RXEOB) {
Stefan Roesed1c3b272009-09-09 16:25:29 +02001687 mal_eob = mfdcr(MAL0_RXEOBISR);
Stefan Roesed1631fe2008-06-26 13:40:57 +02001688 if (mal_eob &
1689 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
1690 /* push packet to upper layer */
1691 enet_rcv(dev, emac_isr);
1692
1693 /* clear MAL interrupt status bits */
1694 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
1695
wdenkba56f622004-02-06 23:19:44 +00001696 /* indicate that we serviced an interrupt */
1697 serviced = 1;
1698 rc = 0;
1699 }
1700 }
James Cloughc0b46d82009-09-10 09:11:50 +02001701#if defined(CONFIG_405EZ)
1702 /*
1703 * On 405EZ the RX-/TX-interrupts are coalesced into
1704 * one IRQ bit in the UIC. We need to acknowledge the
1705 * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
1706 */
1707 mtsdr(SDR0_ICINTSTAT,
1708 SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1709#endif /* defined(CONFIG_405EZ) */
wdenkba56f622004-02-06 23:19:44 +00001710 } while (serviced);
1711
1712 return (rc);
1713}
1714
1715/*-----------------------------------------------------------------------------+
1716 * MAL Error Routine
1717 *-----------------------------------------------------------------------------*/
1718static void mal_err (struct eth_device *dev, unsigned long isr,
1719 unsigned long uic, unsigned long maldef,
1720 unsigned long mal_errr)
1721{
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001722 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001723
Stefan Roesed1c3b272009-09-09 16:25:29 +02001724 mtdcr (MAL0_ESR, isr); /* clear interrupt */
wdenkba56f622004-02-06 23:19:44 +00001725
1726 /* clear DE interrupt */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001727 mtdcr (MAL0_TXDEIR, 0xC0000000);
1728 mtdcr (MAL0_RXDEIR, 0x80000000);
wdenkba56f622004-02-06 23:19:44 +00001729
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001730#ifdef INFO_4XX_ENET
Wolfgang Denk265817c2005-09-25 00:53:22 +02001731 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
wdenkba56f622004-02-06 23:19:44 +00001732#endif
1733
1734 eth_init (hw_p->bis); /* start again... */
1735}
1736
1737/*-----------------------------------------------------------------------------+
1738 * EMAC Error Routine
1739 *-----------------------------------------------------------------------------*/
1740static void emac_err (struct eth_device *dev, unsigned long isr)
1741{
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001742 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001743
1744 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
Niklaus Gigerddc922f2009-10-04 20:04:20 +02001745 out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
wdenkba56f622004-02-06 23:19:44 +00001746}
1747
1748/*-----------------------------------------------------------------------------+
1749 * enet_rcv() handles the ethernet receive data
1750 *-----------------------------------------------------------------------------*/
1751static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1752{
wdenkba56f622004-02-06 23:19:44 +00001753 unsigned long data_len;
1754 unsigned long rx_eob_isr;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001755 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001756
1757 int handled = 0;
1758 int i;
1759 int loop_count = 0;
1760
Stefan Roesed1c3b272009-09-09 16:25:29 +02001761 rx_eob_isr = mfdcr (MAL0_RXEOBISR);
Stefan Roese8ac41e32008-03-11 15:05:26 +01001762 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
wdenkba56f622004-02-06 23:19:44 +00001763 /* clear EOB */
Stefan Roesed1c3b272009-09-09 16:25:29 +02001764 mtdcr (MAL0_RXEOBISR, rx_eob_isr);
wdenkba56f622004-02-06 23:19:44 +00001765
1766 /* EMAC RX done */
1767 while (1) { /* do all */
1768 i = hw_p->rx_slot;
1769
1770 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1771 || (loop_count >= NUM_RX_BUFF))
1772 break;
Stefan Roesea2e1c702007-07-12 16:32:08 +02001773
wdenkba56f622004-02-06 23:19:44 +00001774 loop_count++;
wdenkba56f622004-02-06 23:19:44 +00001775 handled++;
Stefan Roese8ac41e32008-03-11 15:05:26 +01001776 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
wdenkba56f622004-02-06 23:19:44 +00001777 if (data_len) {
1778 if (data_len > ENET_MAX_MTU) /* Check len */
1779 data_len = 0;
1780 else {
1781 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1782 data_len = 0;
1783 hw_p->stats.rx_err_log[hw_p->
1784 rx_err_index]
1785 = hw_p->rx[i].ctrl;
1786 hw_p->rx_err_index++;
1787 if (hw_p->rx_err_index ==
1788 MAX_ERR_LOG)
1789 hw_p->rx_err_index =
1790 0;
wdenkfc1cfcd2004-04-25 15:41:35 +00001791 } /* emac_erros */
wdenkba56f622004-02-06 23:19:44 +00001792 } /* data_len < max mtu */
wdenkfc1cfcd2004-04-25 15:41:35 +00001793 } /* if data_len */
wdenkba56f622004-02-06 23:19:44 +00001794 if (!data_len) { /* no data */
1795 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1796
1797 hw_p->stats.data_len_err++; /* Error at Rx */
1798 }
1799
1800 /* !data_len */
1801 /* AS.HARNOIS */
1802 /* Check if user has already eaten buffer */
1803 /* if not => ERROR */
1804 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1805 if (hw_p->is_receiving)
1806 printf ("ERROR : Receive buffers are full!\n");
1807 break;
1808 } else {
1809 hw_p->stats.rx_frames++;
1810 hw_p->stats.rx += data_len;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001811#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001812 hw_p->stats.pkts_rx++;
1813#endif
1814 /* AS.HARNOIS
1815 * use ring buffer
1816 */
1817 hw_p->rx_ready[hw_p->rx_i_index] = i;
1818 hw_p->rx_i_index++;
1819 if (NUM_RX_BUFF == hw_p->rx_i_index)
1820 hw_p->rx_i_index = 0;
1821
Stefan Roesea2e1c702007-07-12 16:32:08 +02001822 hw_p->rx_slot++;
1823 if (NUM_RX_BUFF == hw_p->rx_slot)
1824 hw_p->rx_slot = 0;
1825
wdenkba56f622004-02-06 23:19:44 +00001826 /* AS.HARNOIS
1827 * free receive buffer only when
1828 * buffer has been handled (eth_rx)
1829 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1830 */
1831 } /* if data_len */
1832 } /* while */
1833 } /* if EMACK_RXCHL */
1834}
1835
1836
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001837static int ppc_4xx_eth_rx (struct eth_device *dev)
wdenkba56f622004-02-06 23:19:44 +00001838{
1839 int length;
1840 int user_index;
1841 unsigned long msr;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001842 EMAC_4XX_HW_PST hw_p = dev->priv;
wdenkba56f622004-02-06 23:19:44 +00001843
Wolfgang Denk265817c2005-09-25 00:53:22 +02001844 hw_p->is_receiving = 1; /* tell driver */
wdenkba56f622004-02-06 23:19:44 +00001845
1846 for (;;) {
1847 /* AS.HARNOIS
1848 * use ring buffer and
1849 * get index from rx buffer desciptor queue
1850 */
1851 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1852 if (user_index == -1) {
1853 length = -1;
1854 break; /* nothing received - leave for() loop */
1855 }
1856
1857 msr = mfmsr ();
1858 mtmsr (msr & ~(MSR_EE));
1859
Stefan Roese8ac41e32008-03-11 15:05:26 +01001860 length = hw_p->rx[user_index].data_len & 0x0fff;
wdenkba56f622004-02-06 23:19:44 +00001861
1862 /* Pass the packet up to the protocol layers. */
Wolfgang Denk265817c2005-09-25 00:53:22 +02001863 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1864 /* NetReceive(NetRxPackets[i], length); */
Stefan Roeseff768cb2007-10-31 18:01:24 +01001865 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1866 (u32)hw_p->rx[user_index].data_ptr +
Matthias Fuchsba79fde2007-12-14 11:19:56 +01001867 length - 4);
wdenkba56f622004-02-06 23:19:44 +00001868 NetReceive (NetRxPackets[user_index], length - 4);
1869 /* Free Recv Buffer */
1870 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1871 /* Free rx buffer descriptor queue */
1872 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1873 hw_p->rx_u_index++;
1874 if (NUM_RX_BUFF == hw_p->rx_u_index)
1875 hw_p->rx_u_index = 0;
1876
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001877#ifdef INFO_4XX_ENET
wdenkba56f622004-02-06 23:19:44 +00001878 hw_p->stats.pkts_handled++;
1879#endif
1880
1881 mtmsr (msr); /* Enable IRQ's */
1882 }
1883
Wolfgang Denk265817c2005-09-25 00:53:22 +02001884 hw_p->is_receiving = 0; /* tell driver */
wdenkba56f622004-02-06 23:19:44 +00001885
1886 return length;
1887}
1888
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001889int ppc_4xx_eth_initialize (bd_t * bis)
wdenkba56f622004-02-06 23:19:44 +00001890{
1891 static int virgin = 0;
wdenkba56f622004-02-06 23:19:44 +00001892 struct eth_device *dev;
1893 int eth_num = 0;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001894 EMAC_4XX_HW_PST hw = NULL;
Stefan Roese5fb692c2007-01-18 10:25:34 +01001895 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1896 u32 hw_addr[4];
Stefan Roesed1631fe2008-06-26 13:40:57 +02001897 u32 mal_ier;
wdenkba56f622004-02-06 23:19:44 +00001898
Stefan Roese846b0dd2005-08-08 12:42:22 +02001899#if defined(CONFIG_440GX)
Stefan Roesec157d8e2005-08-01 16:41:48 +02001900 unsigned long pfc1;
1901
Stefan Roesed1c3b272009-09-09 16:25:29 +02001902 mfsdr (SDR0_PFC1, pfc1);
wdenkba56f622004-02-06 23:19:44 +00001903 pfc1 &= ~(0x01e00000);
1904 pfc1 |= 0x01200000;
Stefan Roesed1c3b272009-09-09 16:25:29 +02001905 mtsdr (SDR0_PFC1, pfc1);
Stefan Roesec157d8e2005-08-01 16:41:48 +02001906#endif
Stefan Roese5fb692c2007-01-18 10:25:34 +01001907
1908 /* first clear all mac-addresses */
1909 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1910 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1911
1912 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
Mike Frysingerd3f87142009-02-11 19:01:26 -05001913 int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
Stefan Roese5fb692c2007-01-18 10:25:34 +01001914 switch (eth_num) {
1915 default: /* fall through */
1916 case 0:
Mike Frysingerd3f87142009-02-11 19:01:26 -05001917 eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
Stefan Roese5fb692c2007-01-18 10:25:34 +01001918 hw_addr[eth_num] = 0x0;
1919 break;
1920#ifdef CONFIG_HAS_ETH1
1921 case 1:
Mike Frysingerd3f87142009-02-11 19:01:26 -05001922 eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
Stefan Roese5fb692c2007-01-18 10:25:34 +01001923 hw_addr[eth_num] = 0x100;
1924 break;
1925#endif
1926#ifdef CONFIG_HAS_ETH2
1927 case 2:
Mike Frysingerd3f87142009-02-11 19:01:26 -05001928 eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001929#if defined(CONFIG_460GT)
1930 hw_addr[eth_num] = 0x300;
1931#else
Stefan Roese5fb692c2007-01-18 10:25:34 +01001932 hw_addr[eth_num] = 0x400;
Stefan Roese4c9e8552008-03-19 16:20:49 +01001933#endif
Stefan Roese5fb692c2007-01-18 10:25:34 +01001934 break;
1935#endif
1936#ifdef CONFIG_HAS_ETH3
1937 case 3:
Mike Frysingerd3f87142009-02-11 19:01:26 -05001938 eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
Stefan Roese4c9e8552008-03-19 16:20:49 +01001939#if defined(CONFIG_460GT)
1940 hw_addr[eth_num] = 0x400;
1941#else
Stefan Roese5fb692c2007-01-18 10:25:34 +01001942 hw_addr[eth_num] = 0x600;
Stefan Roese4c9e8552008-03-19 16:20:49 +01001943#endif
Stefan Roese5fb692c2007-01-18 10:25:34 +01001944 break;
1945#endif
1946 }
1947 }
1948
wdenk3c74e322004-02-22 23:46:08 +00001949 /* set phy num and mode */
1950 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001951 bis->bi_phymode[0] = 0;
1952
Stefan Roesec157d8e2005-08-01 16:41:48 +02001953#if defined(CONFIG_PHY1_ADDR)
wdenk3c74e322004-02-22 23:46:08 +00001954 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001955 bis->bi_phymode[1] = 0;
Stefan Roesec157d8e2005-08-01 16:41:48 +02001956#endif
Stefan Roese846b0dd2005-08-08 12:42:22 +02001957#if defined(CONFIG_440GX)
wdenk3c74e322004-02-22 23:46:08 +00001958 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1959 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
wdenk3c74e322004-02-22 23:46:08 +00001960 bis->bi_phymode[2] = 2;
1961 bis->bi_phymode[3] = 2;
Stefan Roesedbbd1252007-10-05 17:10:59 +02001962#endif
wdenkba56f622004-02-06 23:19:44 +00001963
Stefan Roesedbbd1252007-10-05 17:10:59 +02001964#if defined(CONFIG_440GX) || \
1965 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1966 defined(CONFIG_405EX)
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001967 ppc_4xx_eth_setup_bridge(0, bis);
wdenka06752e2004-09-29 22:43:59 +00001968#endif
1969
Stefan Roese1e25f952005-10-20 16:34:28 +02001970 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
Stefan Roese5fb692c2007-01-18 10:25:34 +01001971 /*
1972 * See if we can actually bring up the interface,
1973 * otherwise, skip it
1974 */
1975 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1976 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1977 continue;
wdenkba56f622004-02-06 23:19:44 +00001978 }
1979
1980 /* Allocate device structure */
1981 dev = (struct eth_device *) malloc (sizeof (*dev));
1982 if (dev == NULL) {
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001983 printf ("ppc_4xx_eth_initialize: "
wdenk3f85ce22004-02-23 16:11:30 +00001984 "Cannot allocate eth_device %d\n", eth_num);
wdenkba56f622004-02-06 23:19:44 +00001985 return (-1);
1986 }
wdenkb2532ef2005-06-20 10:17:34 +00001987 memset(dev, 0, sizeof(*dev));
wdenkba56f622004-02-06 23:19:44 +00001988
1989 /* Allocate our private use data */
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001990 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
wdenkba56f622004-02-06 23:19:44 +00001991 if (hw == NULL) {
Stefan Roesed6c61aa2005-08-16 18:18:00 +02001992 printf ("ppc_4xx_eth_initialize: "
wdenk3f85ce22004-02-23 16:11:30 +00001993 "Cannot allocate private hw data for eth_device %d",
wdenkba56f622004-02-06 23:19:44 +00001994 eth_num);
1995 free (dev);
1996 return (-1);
1997 }
wdenkb2532ef2005-06-20 10:17:34 +00001998 memset(hw, 0, sizeof(*hw));
wdenkba56f622004-02-06 23:19:44 +00001999
Stefan Roese5fb692c2007-01-18 10:25:34 +01002000 hw->hw_addr = hw_addr[eth_num];
2001 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
wdenkba56f622004-02-06 23:19:44 +00002002 hw->devnum = eth_num;
Stefan Roesec157d8e2005-08-01 16:41:48 +02002003 hw->print_speed = 1;
wdenkba56f622004-02-06 23:19:44 +00002004
Stefan Roese5fb692c2007-01-18 10:25:34 +01002005 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
wdenkba56f622004-02-06 23:19:44 +00002006 dev->priv = (void *) hw;
Stefan Roesed6c61aa2005-08-16 18:18:00 +02002007 dev->init = ppc_4xx_eth_init;
2008 dev->halt = ppc_4xx_eth_halt;
2009 dev->send = ppc_4xx_eth_send;
2010 dev->recv = ppc_4xx_eth_rx;
wdenkba56f622004-02-06 23:19:44 +00002011
Stefan Roese3ce04d92011-07-12 13:26:47 +02002012 eth_register(dev);
2013
2014#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
2015 miiphy_register(dev->name,
2016 emac4xx_miiphy_read, emac4xx_miiphy_write);
2017#endif
2018
wdenkba56f622004-02-06 23:19:44 +00002019 if (0 == virgin) {
2020 /* set the MAL IER ??? names may change with new spec ??? */
Stefan Roesedbbd1252007-10-05 17:10:59 +02002021#if defined(CONFIG_440SPE) || \
2022 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese8ac41e32008-03-11 15:05:26 +01002023 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +02002024 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02002025 mal_ier =
2026 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
2027 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
2028#else
wdenkba56f622004-02-06 23:19:44 +00002029 mal_ier =
2030 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
2031 MAL_IER_OPBE | MAL_IER_PLBE;
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02002032#endif
Stefan Roesed1c3b272009-09-09 16:25:29 +02002033 mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */
2034 mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */
2035 mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */
2036 mtdcr (MAL0_IER, mal_ier);
wdenkba56f622004-02-06 23:19:44 +00002037
2038 /* install MAL interrupt handler */
Stefan Roesed1631fe2008-06-26 13:40:57 +02002039 irq_install_handler (VECNUM_MAL_SERR,
wdenkba56f622004-02-06 23:19:44 +00002040 (interrupt_handler_t *) enetInt,
2041 dev);
Stefan Roesed1631fe2008-06-26 13:40:57 +02002042 irq_install_handler (VECNUM_MAL_TXEOB,
wdenkba56f622004-02-06 23:19:44 +00002043 (interrupt_handler_t *) enetInt,
2044 dev);
Stefan Roesed1631fe2008-06-26 13:40:57 +02002045 irq_install_handler (VECNUM_MAL_RXEOB,
wdenkba56f622004-02-06 23:19:44 +00002046 (interrupt_handler_t *) enetInt,
2047 dev);
Stefan Roesed1631fe2008-06-26 13:40:57 +02002048 irq_install_handler (VECNUM_MAL_TXDE,
wdenkba56f622004-02-06 23:19:44 +00002049 (interrupt_handler_t *) enetInt,
2050 dev);
Stefan Roesed1631fe2008-06-26 13:40:57 +02002051 irq_install_handler (VECNUM_MAL_RXDE,
wdenkba56f622004-02-06 23:19:44 +00002052 (interrupt_handler_t *) enetInt,
2053 dev);
2054 virgin = 1;
2055 }
wdenkba56f622004-02-06 23:19:44 +00002056 } /* end for each supported device */
Stefan Roese802b7692008-01-08 18:39:30 +01002057
2058 return 0;
wdenkba56f622004-02-06 23:19:44 +00002059}