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Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +01001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2005-2007
6 * Modified for InterControl digsyMTC MPC5200 board by
7 * Frank Bodammer, GCD Hard- & Software GmbH,
8 * frank.bodammer@gcd-solutions.de
9 *
10 * (C) Copyright 2009 Semihalf
11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software\; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation\; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY\; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program\; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/*
36 * High Level Configuration Options
37 */
38
39#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
40#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
41#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
42
Wolfgang Denk2ae18242010-10-06 09:05:45 +020043/*
44 * Valid values for CONFIG_SYS_TEXT_BASE are:
45 * 0xFFF00000 boot high (standard configuration)
46 * 0xFE000000 boot low
47 * 0x00100000 boot from RAM (for testing only)
48 */
49#ifndef CONFIG_SYS_TEXT_BASE
50#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
51#endif
52
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010053#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
54
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010055#define CONFIG_SYS_CACHELINE_SIZE 32
56
57/*
58 * Serial console configuration
59 */
60#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
61#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
62#define CONFIG_SYS_BAUDRATE_TABLE \
63 { 9600, 19200, 38400, 57600, 115200, 230400 }
64
65/*
66 * PCI Mapping:
67 * 0x40000000 - 0x4fffffff - PCI Memory
68 * 0x50000000 - 0x50ffffff - PCI IO Space
69 */
70#define CONFIG_PCI 1
71#define CONFIG_PCI_PNP 1
72#define CONFIG_PCI_SCAN_SHOW 1
73
74#define CONFIG_PCI_MEM_BUS 0x40000000
75#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
76#define CONFIG_PCI_MEM_SIZE 0x10000000
77
78#define CONFIG_PCI_IO_BUS 0x50000000
79#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
80#define CONFIG_PCI_IO_SIZE 0x01000000
81
82/*
83 * Partitions
84 */
85#define CONFIG_DOS_PARTITION
86#define CONFIG_BZIP2
87
88/*
89 * Command line configuration.
90 */
91#include <config_cmd_default.h>
92
93#define CONFIG_CMD_DFL
94#define CONFIG_CMD_CACHE
95#define CONFIG_CMD_DATE
96#define CONFIG_CMD_DHCP
97#define CONFIG_CMD_DIAG
98#define CONFIG_CMD_EEPROM
99#define CONFIG_CMD_ELF
100#define CONFIG_CMD_EXT2
101#define CONFIG_CMD_FAT
102#define CONFIG_CMD_I2C
103#define CONFIG_CMD_IDE
104#define CONFIG_CMD_IRQ
105#define CONFIG_CMD_MII
106#define CONFIG_CMD_PCI
107#define CONFIG_CMD_PING
108#define CONFIG_CMD_REGINFO
109#define CONFIG_CMD_SAVES
Grzegorz Bernackif1f66ed2009-06-12 11:33:53 +0200110#define CONFIG_CMD_SPI
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100111#define CONFIG_CMD_USB
112
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200113#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100114#define CONFIG_SYS_LOWBOOT 1
115#endif
116
117/*
118 * Autobooting
119 */
120#define CONFIG_BOOTDELAY 1
121
122#undef CONFIG_BOOTARGS
123
Detlev Zundelff276502009-08-05 18:37:45 +0200124#define CONFIG_EXTRA_ENV_SETTINGS \
125 "fw_image=digsyMPC.img\0" \
126 "mtcb_start=mtc led diag orange; run mtcb_1\0" \
127 "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
128 "do mtc led $x; done\0" \
129 "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
130 "else run mtcb_fw; fi\0" \
131 "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
132 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
133 "mtcb_update=mtc led user1 orange;" \
134 "while mtc key; do ; done; run mtcb_2;\0" \
135 "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
136 "mtcb_usb1=if fatload usb 0 400000 script.img; " \
137 "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
138 "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
139 "then run mtcb_dousb; else run mtcb_ide; fi\0" \
140 "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
141 "run mtcb_wait_flickr mtcb_ds_1;\0" \
142 "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
143 "source 400000; else run mtcb_error; fi\0" \
144 "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
145 "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
146 "else run mtcb_error; fi\0" \
147 "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
148 "run mtcb_checkfw\0" \
149 "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
150 "else run mtcb_error; fi\0" \
151 "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
152 "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
153 "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
154 "mtcb_uledflckr=mtc led user1 orange 11\0" \
155 "mtcb_error=mtc led user1 red\0" \
156 "mtcb_clear=erase ff000000 ff0fffff\0" \
157 "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
158 "mtcb_success=mtc led user1 green\0" \
159 "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
160 "then run mtcb_doide; else run mtcb_error; fi\0" \
161 "mtcb_doide=mtc led user2 green 1;" \
162 "run mtcb_wait_flickr mtcb_di_1;\0" \
163 "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
164 "else run mtcb_error; fi\0" \
165 "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
166 "ramdisk_num_sector=16\0" \
167 "flash_base=ff000000\0" \
168 "flashdisk_size=e00000\0" \
169 "env_sector=fff60000\0" \
170 "flashdisk_start=ff100000\0" \
171 "load_cmd=tftp 400000 digsyMPC.img\0" \
172 "clear_cmd=erase ff000000 ff0fffff\0" \
173 "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
174 "update_cmd=run load_cmd; " \
175 "iminfo 400000; " \
176 "run clear_cmd flash_cmd; " \
177 "iminfo ff000000\0" \
178 "spi_driver=yes\0" \
179 "spi_watchdog=no\0" \
180 "ftps_start=yes\0" \
181 "ftps_user1=admin\0" \
182 "ftps_pass1=admin\0" \
183 "ftps_base1=/\0" \
184 "ftps_home1=/\0" \
185 "plc_sio_srv=no\0" \
186 "plc_sio_baud=57600\0" \
187 "plc_sio_parity=no\0" \
188 "plc_sio_stop=1\0" \
189 "plc_sio_com=2\0" \
190 "plc_eth_srv=yes\0" \
191 "plc_eth_port=1200\0" \
192 "plc_root=/ide/\0" \
193 "diag_level=0\0" \
194 "webvisu=no\0" \
195 "plc_can1_routing=no\0" \
196 "plc_can1_baudrate=250\0" \
197 "plc_can2_routing=no\0" \
198 "plc_can2_baudrate=250\0" \
199 "plc_can3_routing=no\0" \
200 "plc_can3_baudrate=250\0" \
201 "plc_can4_routing=no\0" \
202 "plc_can4_baudrate=250\0" \
203 "netdev=eth0\0" \
204 "console=ttyPSC0\0" \
205 "kernel_addr_r=400000\0" \
206 "fdt_addr_r=600000\0" \
207 "nfsargs=setenv bootargs root=/dev/nfs rw " \
208 "nfsroot=${serverip}:${rootpath}\0" \
209 "addip=setenv bootargs ${bootargs} " \
210 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
211 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100212 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
Detlev Zundelff276502009-08-05 18:37:45 +0200213 "rootpath=/opt/eldk/ppc_6xx\0" \
214 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
215 "tftp ${fdt_addr_r} ${fdt_file};" \
216 "run nfsargs addip addcons;" \
217 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
218 "load=tftp 200000 ${u-boot}\0" \
219 "update=protect off FFF00000 +${filesize};" \
220 "erase FFF00000 +${filesize};" \
221 "cp.b 200000 FFF00000 ${filesize};" \
222 "protect on FFF00000 +${filesize}\0" \
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100223 ""
224
Detlev Zundelff276502009-08-05 18:37:45 +0200225#define CONFIG_BOOTCOMMAND "run mtcb_start"
226
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100227/*
Grzegorz Bernackif1f66ed2009-06-12 11:33:53 +0200228 * SPI configuration
229 */
230#define CONFIG_HARD_SPI 1
231#define CONFIG_MPC52XX_SPI 1
232
233/*
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100234 * I2C configuration
235 */
236#define CONFIG_HARD_I2C 1
237#define CONFIG_SYS_I2C_MODULE 1
238#define CONFIG_SYS_I2C_SPEED 100000
239#define CONFIG_SYS_I2C_SLAVE 0x7F
240
241/*
242 * EEPROM configuration
243 */
244#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
245#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
246#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
247#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
248
249/*
250 * RTC configuration
251 */
Heiko Schocher466f0132011-01-13 08:25:00 +0100252#if defined(CONFIG_DIGSY_REV5)
253#define CONFIG_SYS_I2C_RTC_ADDR 0x56
254#define CONFIG_RTC_RV3029
Heiko Schochera01ebd92011-03-28 09:24:23 +0200255/* Enable 5k Ohm trickle charge resistor */
256#define CONFIG_SYS_RV3029_TCR 0x20
Heiko Schocher466f0132011-01-13 08:25:00 +0100257#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100258#define CONFIG_RTC_DS1337
259#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Werner Pfisterc569ad62009-09-21 14:49:56 +0200260#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
Heiko Schocher466f0132011-01-13 08:25:00 +0100261#endif
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100262
263/*
264 * Flash configuration
265 */
266#define CONFIG_SYS_FLASH_CFI 1
267#define CONFIG_FLASH_CFI_DRIVER 1
268
Heiko Schocher466f0132011-01-13 08:25:00 +0100269#if defined(CONFIG_DIGSY_REV5)
270#define CONFIG_SYS_FLASH_BASE 0xFE000000
271#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
272#define CONFIG_SYS_MAX_FLASH_BANKS 2
Heiko Schocher927d2ce2011-01-21 07:23:35 +0100273#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
274 CONFIG_SYS_FLASH_BASE_CS1}
Heiko Schocher466f0132011-01-13 08:25:00 +0100275#define CONFIG_SYS_UPDATE_FLASH_SIZE
276#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
277#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100278#define CONFIG_SYS_FLASH_BASE 0xFF000000
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100279#define CONFIG_SYS_MAX_FLASH_BANKS 1
Heiko Schocher466f0132011-01-13 08:25:00 +0100280#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
281#endif
282
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100283#define CONFIG_SYS_MAX_FLASH_SECT 256
284#define CONFIG_FLASH_16BIT
285#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Heiko Schocher466f0132011-01-13 08:25:00 +0100286#define CONFIG_SYS_FLASH_SIZE 0x01000000
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100287#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
288#define CONFIG_SYS_FLASH_WRITE_TOUT 500
289
290#define CONFIG_OF_LIBFDT 1
291#define CONFIG_OF_BOARD_SETUP 1
292
293#define OF_CPU "PowerPC,5200@0"
294#define OF_SOC "soc5200@f0000000"
295#define OF_TBCLK (bd->bi_busfreq / 4)
296
297#define CONFIG_BOARD_EARLY_INIT_R
298#define CONFIG_MISC_INIT_R
299
300/*
301 * Environment settings
302 */
303#define CONFIG_ENV_IS_IN_FLASH 1
304#if defined(CONFIG_LOWBOOT)
305#define CONFIG_ENV_ADDR 0xFF060000
306#else /* CONFIG_LOWBOOT */
307#define CONFIG_ENV_ADDR 0xFFF60000
308#endif /* CONFIG_LOWBOOT */
309#define CONFIG_ENV_SIZE 0x10000
310#define CONFIG_ENV_SECT_SIZE 0x20000
311#define CONFIG_ENV_OVERWRITE 1
312
313/*
314 * Memory map
315 */
316#define CONFIG_SYS_MBAR 0xF0000000
317#define CONFIG_SYS_SDRAM_BASE 0x00000000
318#if !defined(CONFIG_SYS_LOWBOOT)
319#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
320#else
321#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
322#endif
323
324/*
325 * Use SRAM until RAM will be available
326 */
327#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200328#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100329
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100330#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200331 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100332#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
333
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200334#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100335#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
336#define CONFIG_SYS_RAMBOOT 1
337#endif
338
339#define CONFIG_SYS_MONITOR_LEN (256 << 10)
340#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
341#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
342
343/*
344 * Ethernet configuration
345 */
346#define CONFIG_MPC5xxx_FEC 1
347#define CONFIG_MPC5xxx_FEC_MII100
Heiko Schocher1b414932011-04-03 20:10:20 +0000348#if defined(CONFIG_DIGSY_REV5)
349#define CONFIG_PHY_ADDR 0x01
350#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100351#define CONFIG_PHY_ADDR 0x00
Heiko Schocher1b414932011-04-03 20:10:20 +0000352#endif
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100353#define CONFIG_PHY_RESET_DELAY 1000
354
355#define CONFIG_NETCONSOLE /* include NetConsole support */
356
357/*
358 * GPIO configuration
Grzegorz Bernacki12602332009-06-12 11:33:55 +0200359 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
360 * Bit 0 (mask 0x80000000) : 0x1
361 * SPI on Tmr2/3/4/5 pins
362 * Bit 2:3 (mask 0x30000000) : 0x2
363 * ATA cs0/1 on csb_4/5
364 * Bit 6:7 (mask 0x03000000) : 0x2
365 * Ethernet 100Mbit with MD
366 * Bits 12:15 (mask 0x000f0000): 0x5
367 * USB - Two UARTs
368 * Bits 18:19 (mask 0x00003000) : 0x2
369 * PSC3 - USB2 on PSC3
370 * Bits 20:23 (mask 0x00000f00) : 0x1
371 * PSC2 - CAN1&2 on PSC2 pins
372 * Bits 25:27 (mask 0x00000070) : 0x1
373 * PSC1 - AC97 functionality
374 * Bits 29:31 (mask 0x00000007) : 0x2
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100375 */
376#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
377
378/*
379 * Miscellaneous configurable options
380 */
381#define CONFIG_SYS_LONGHELP
382#define CONFIG_AUTO_COMPLETE 1
Grzegorz Bernackia781de12009-06-17 16:20:14 +0200383#define CONFIG_CMDLINE_EDITING 1
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100384#define CONFIG_SYS_PROMPT "=> "
385#define CONFIG_SYS_HUSH_PARSER
386#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
387
388#define CONFIG_AUTOBOOT_KEYED
389#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
390#define CONFIG_AUTOBOOT_DELAY_STR " "
391
392#define CONFIG_LOOPW 1
393#define CONFIG_MX_CYCLIC 1
394#define CONFIG_ZERO_BOOTDELAY_CHECK
395
396#define CONFIG_SYS_CBSIZE 1024
397#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
398#define CONFIG_SYS_MAXARGS 32
399#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
400
401#define CONFIG_SYS_ALT_MEMTEST
402#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
403#define CONFIG_SYS_MEMTEST_START 0x00010000
404#define CONFIG_SYS_MEMTEST_END 0x019fffff
405
406#define CONFIG_SYS_LOAD_ADDR 0x00100000
407
408#define CONFIG_SYS_HZ 1000
409
410/*
411 * Various low-level settings
412 */
413#define CONFIG_SYS_SDRAM_CS1 1
414#define CONFIG_SYS_XLB_PIPELINING 1
415
416#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
417#define CONFIG_SYS_HID0_FINAL HID0_ICE
418
419#if defined(CONFIG_SYS_LOWBOOT)
420#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
421#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
422#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
423#endif
424
425#define CONFIG_SYS_CS4_START 0x60000000
426#define CONFIG_SYS_CS4_SIZE 0x1000
427#define CONFIG_SYS_CS4_CFG 0x0008FC00
428
429#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
430#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
431#define CONFIG_SYS_CS0_CFG 0x0002DD00
432
Heiko Schocher466f0132011-01-13 08:25:00 +0100433#if defined(CONFIG_DIGSY_REV5)
434#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
435#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
436#define CONFIG_SYS_CS1_CFG 0x0002DD00
437#endif
438
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100439#define CONFIG_SYS_CS_BURST 0x00000000
440#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
441
442#if !defined(CONFIG_SYS_LOWBOOT)
443#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
444#else
445#define CONFIG_SYS_RESET_ADDRESS 0xff000100
446#endif
447
448/*
449 * USB
450 */
451#define CONFIG_USB_OHCI_NEW
452#define CONFIG_SYS_OHCI_BE_CONTROLLER
453#define CONFIG_USB_STORAGE
454
455#define CONFIG_USB_CLOCK 0x00013333
456#define CONFIG_USB_CONFIG 0x00002000
457
458#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
459#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
460#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
461#define CONFIG_SYS_USB_OHCI_CPU_INIT
462
463/*
464 * IDE/ATA
465 */
466#define CONFIG_IDE_RESET
467#define CONFIG_IDE_PREINIT
468
469#define CONFIG_SYS_ATA_CS_ON_I2C2
470#define CONFIG_SYS_IDE_MAXBUS 1
471#define CONFIG_SYS_IDE_MAXDEVICE 1
472
473#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
474#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
475#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
476#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
477#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
478#define CONFIG_SYS_ATA_STRIDE 4
479
480#define CONFIG_ATAPI 1
481#define CONFIG_LBA48 1
482
483#endif /* __CONFIG_H */