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wdenk3c2b3d42005-04-05 23:32:21 +00001/*
2 * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
3 *
4 * Configuation settings for the TI OMAP VoiceBlue board.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#include <configs/omap1510.h>
28
wdenk3c2b3d42005-04-05 23:32:21 +000029#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
30#define CONFIG_OMAP 1 /* in a TI OMAP core */
31#define CONFIG_OMAP1510 1 /* which is in a 5910 */
32
33/* Input clock of PLL */
Ladislav Michla32c1e02010-02-17 21:29:39 -050034#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz */
35#define CONFIG_XTAL_FREQ 12000000 /* 12MHz */
wdenk3c2b3d42005-04-05 23:32:21 +000036
37#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38
39#define CONFIG_MISC_INIT_R /* There is nothing to really init */
40#define BOARD_LATE_INIT /* but we flash the LEDs here */
41
42#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
43#define CONFIG_SETUP_MEMORY_TAGS 1
44#define CONFIG_INITRD_TAG 1
45
Heiko Schochercb0fdf32006-05-03 08:34:03 +020046#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
47
wdenk3c2b3d42005-04-05 23:32:21 +000048/*
49 * Physical Memory Map
50 */
Ladislav Michla32c1e02010-02-17 21:29:39 -050051#define CONFIG_NR_DRAM_BANKS 1
52#define PHYS_SDRAM_1 0x10000000
53#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
54#define PHYS_FLASH_1 0x0000000
wdenk3c2b3d42005-04-05 23:32:21 +000055
Ladislav Michla32c1e02010-02-17 21:29:39 -050056#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
wdenk3c2b3d42005-04-05 23:32:21 +000058
59/*
60 * Environment settings
61 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020062#define CONFIG_ENV_IS_IN_FLASH
Ladislav Michla32c1e02010-02-17 21:29:39 -050063#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
64#define CONFIG_ENV_SIZE (8 * 1024)
65#define CONFIG_ENV_SECT_SIZE (64 * 1024)
66#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
67#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
wdenk3c2b3d42005-04-05 23:32:21 +000068
69#define CONFIG_ENV_OVERWRITE
70
wdenk3c2b3d42005-04-05 23:32:21 +000071/*
wdenkb77fad32005-04-07 22:36:40 +000072 * Size of malloc() pool and stack
wdenk3c2b3d42005-04-05 23:32:21 +000073 */
Ladislav Michla32c1e02010-02-17 21:29:39 -050074#define CONFIG_SYS_GBL_DATA_SIZE 128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
Ladislav Michla32c1e02010-02-17 21:29:39 -050076#define CONFIG_STACKSIZE (1 * 1024 * 1024)
wdenk3c2b3d42005-04-05 23:32:21 +000077
78/*
wdenk3c2b3d42005-04-05 23:32:21 +000079 * Hardware drivers
80 */
Ladislav Michla32c1e02010-02-17 21:29:39 -050081#define CONFIG_SYS_NS16550
82#define CONFIG_SYS_NS16550_SERIAL
83#define CONFIG_SYS_NS16550_REG_SIZE (-4)
84#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ)
85#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE
86
Ben Warren7194ab82009-10-04 22:37:03 -070087#define CONFIG_NET_MULTI
88#define CONFIG_SMC91111
Ladislav Michla32c1e02010-02-17 21:29:39 -050089#define CONFIG_SMC91111_BASE 0x08000300
90
91#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
92#define CONFIG_SYS_MAX_FLASH_BANKS 1
93#define CONFIG_SYS_MAX_FLASH_SECT 512
94
95#define CONFIG_SYS_FLASH_CFI
96#define CONFIG_FLASH_CFI_DRIVER
97#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
wdenk3c2b3d42005-04-05 23:32:21 +000098
Ladislav Michl4fedfdd2007-12-07 00:42:32 +010099#define CONFIG_HARD_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_I2C_SPEED 100000
101#define CONFIG_SYS_I2C_SLAVE 1
Ladislav Michl4fedfdd2007-12-07 00:42:32 +0100102#define CONFIG_DRIVER_OMAP1510_I2C
103
104#define CONFIG_RTC_DS1307
Ladislav Michla32c1e02010-02-17 21:29:39 -0500105#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Ladislav Michl4fedfdd2007-12-07 00:42:32 +0100106
wdenk3c2b3d42005-04-05 23:32:21 +0000107
Ladislav Michla32c1e02010-02-17 21:29:39 -0500108#define CONFIG_CONS_INDEX 1
109#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk3c2b3d42005-04-05 23:32:21 +0000111
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500112
113/*
Ladislav Michla32c1e02010-02-17 21:29:39 -0500114 * Command line configuration
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500115 */
116#include <config_cmd_default.h>
117
118#define CONFIG_CMD_BDI
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500119#define CONFIG_CMD_BOOTD
120#define CONFIG_CMD_DHCP
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500121#define CONFIG_CMD_SAVEENV
Ladislav Michl4fedfdd2007-12-07 00:42:32 +0100122#define CONFIG_CMD_FLASH
123#define CONFIG_CMD_IMI
124#define CONFIG_CMD_JFFS2
125#define CONFIG_CMD_LOADB
126#define CONFIG_CMD_MEMORY
127#define CONFIG_CMD_NET
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500128#define CONFIG_CMD_PING
129#define CONFIG_CMD_RUN
130
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500131/*
132 * BOOTP options
133 */
134#define CONFIG_BOOTP_SUBNETMASK
135#define CONFIG_BOOTP_GATEWAY
136#define CONFIG_BOOTP_HOSTNAME
137#define CONFIG_BOOTP_BOOTPATH
138
wdenk3c2b3d42005-04-05 23:32:21 +0000139#define CONFIG_LOOPW
140
wdenk3c2b3d42005-04-05 23:32:21 +0000141#define CONFIG_BOOTDELAY 3
Ladislav Michl4fedfdd2007-12-07 00:42:32 +0100142#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
Ladislav Michla32c1e02010-02-17 21:29:39 -0500143#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
144#define CONFIG_SYS_AUTOLOAD "n"
wdenk3c2b3d42005-04-05 23:32:21 +0000145#define CONFIG_BOOTCOMMAND "run nboot"
146#define CONFIG_PREBOOT "run setup"
Ladislav Michla32c1e02010-02-17 21:29:39 -0500147#define CONFIG_EXTRA_ENV_SETTINGS \
148 "silent=1\0" \
149 "ospart=0\0" \
150 "bootfile=/boot/uImage\0" \
151 "setpart=" \
152 "if test -n $swapos; then " \
153 "setenv swapos; saveenv; " \
154 "if test $ospart -eq 0; then " \
155 "setenv ospart 1; " \
156 "else " \
157 "setenv ospart 0; " \
158 "fi; " \
159 "fi\0" \
160 "setup=setenv bootargs console=ttyS0,$baudrate " \
161 "mtdparts=$mtdparts\0" \
162 "nfsargs=setenv bootargs $bootargs " \
Heiko Schochercb0fdf32006-05-03 08:34:03 +0200163 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
Ladislav Michla32c1e02010-02-17 21:29:39 -0500164 "nfsroot=$rootpath root=/dev/nfs\0" \
165 "flashargs=run setpart; setenv bootargs $bootargs " \
166 "root=mtd:data$ospart ro " \
167 "rootfstype=jffs2\0" \
168 "initrdargs=setenv bootargs $bootargs " \
Heiko Schochercb0fdf32006-05-03 08:34:03 +0200169 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
Ladislav Michla32c1e02010-02-17 21:29:39 -0500170 "fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \
171 "mboot=bootp; run initrdargs; tftp; bootm\0" \
Heiko Schochercb0fdf32006-05-03 08:34:03 +0200172 "nboot=bootp; run nfsargs; tftp; bootm\0"
wdenk3c2b3d42005-04-05 23:32:21 +0000173
Heiko Schochercb0fdf32006-05-03 08:34:03 +0200174#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
175
176#if 1 /* feel free to disable for development */
177#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
178#define CONFIG_AUTOBOOT_PROMPT "\nVoiceBlue Enterprise - booting...\n"
179#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
180#endif
181
182/*
Ladislav Michla32c1e02010-02-17 21:29:39 -0500183 * Partitions (mtdparts command line support)
Heiko Schochercb0fdf32006-05-03 08:34:03 +0200184 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100185#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200186#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
187#define CONFIG_FLASH_CFI_MTD
Ladislav Michla32c1e02010-02-17 21:29:39 -0500188#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
189#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
190 "256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
wdenk3c2b3d42005-04-05 23:32:21 +0000191
192/*
193 * Miscellaneous configurable options
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_HUSH_PARSER
196#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk3c2b3d42005-04-05 23:32:21 +0000197#define CONFIG_AUTO_COMPLETE
Ladislav Michla32c1e02010-02-17 21:29:39 -0500198#define CONFIG_SYS_LONGHELP
199#define CONFIG_SYS_PROMPT "# "
200#define CONFIG_SYS_CBSIZE 256
201#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
202 sizeof(CONFIG_SYS_PROMPT) + 16)
203#define CONFIG_SYS_MAXARGS 16
204#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
wdenk3c2b3d42005-04-05 23:32:21 +0000205
Ladislav Michla32c1e02010-02-17 21:29:39 -0500206#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1)
207#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
208 (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE))
209#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000)
wdenk3c2b3d42005-04-05 23:32:21 +0000210
Ladislav Michla32c1e02010-02-17 21:29:39 -0500211/*
212 * The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
wdenk3c2b3d42005-04-05 23:32:21 +0000213 * This time is further subdivided by a local divisor.
214 */
Ladislav Michla32c1e02010-02-17 21:29:39 -0500215#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
216#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
217#define CONFIG_SYS_HZ 1000
wdenk3c2b3d42005-04-05 23:32:21 +0000218
Ladislav Michla32c1e02010-02-17 21:29:39 -0500219#define OMAP5910_DPLL_DIV 1
220#define OMAP5910_DPLL_MUL \
221 ((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
wdenk3c2b3d42005-04-05 23:32:21 +0000222
223#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
224#define OMAP5910_LCD_DIV 2 /* CKL/4 */
225#define OMAP5910_ARM_DIV 0 /* CKL/1 */
226#define OMAP5910_DSP_DIV 0 /* CKL/1 */
227#define OMAP5910_TC_DIV 1 /* CKL/2 */
228#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
229#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
230
231#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
232#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
233 (OMAP5910_LCD_DIV << 2) | \
234 (OMAP5910_ARM_DIV << 4) | \
235 (OMAP5910_DSP_DIV << 6) | \
236 (OMAP5910_TC_DIV << 8) | \
237 (OMAP5910_DSP_MMU_DIV << 10) | \
238 (OMAP5910_ARM_TIM_SEL << 12))
239
240#define VOICEBLUE_LED_REG 0x04030000
241
wdenk3c2b3d42005-04-05 23:32:21 +0000242#endif /* __CONFIG_H */