blob: 342b78c0c4ba566518284fe04d5e64468e921c72 [file] [log] [blame]
Simon Glassff3e0772015-03-05 12:25:25 -07001/*
2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <fdtdec.h>
12#include <inttypes.h>
13#include <pci.h>
Simon Glass21d1fe72015-11-29 13:18:03 -070014#include <asm/io.h>
Simon Glassff3e0772015-03-05 12:25:25 -070015#include <dm/lists.h>
Simon Glassff3e0772015-03-05 12:25:25 -070016#include <dm/device-internal.h>
Bin Meng348b7442015-08-20 06:40:23 -070017#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18#include <asm/fsp/fsp_support.h>
19#endif
Simon Glass5e23b8b2015-11-29 13:17:49 -070020#include "pci_internal.h"
Simon Glassff3e0772015-03-05 12:25:25 -070021
22DECLARE_GLOBAL_DATA_PTR;
23
Simon Glassa6eb93b2016-01-18 20:19:14 -070024int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass983c6ba22015-08-31 18:55:35 -060025{
26 int ret;
27
28 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
29
30 /* Since buses may not be numbered yet try a little harder with bus 0 */
31 if (ret == -ENODEV) {
Simon Glass3f603cb2016-02-11 13:23:26 -070032 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass983c6ba22015-08-31 18:55:35 -060033 if (ret)
34 return ret;
Simon Glass983c6ba22015-08-31 18:55:35 -060035 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
36 }
37
38 return ret;
39}
40
Simon Glass9f60fb02015-11-19 20:27:00 -070041struct udevice *pci_get_controller(struct udevice *dev)
42{
43 while (device_is_on_pci_bus(dev))
44 dev = dev->parent;
45
46 return dev;
47}
48
Simon Glass21ccce12015-11-29 13:17:47 -070049pci_dev_t dm_pci_get_bdf(struct udevice *dev)
Simon Glass4b515e42015-07-06 16:47:46 -060050{
51 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
52 struct udevice *bus = dev->parent;
53
54 return PCI_ADD_BUS(bus->seq, pplat->devfn);
55}
56
Simon Glassff3e0772015-03-05 12:25:25 -070057/**
58 * pci_get_bus_max() - returns the bus number of the last active bus
59 *
60 * @return last bus number, or -1 if no active buses
61 */
62static int pci_get_bus_max(void)
63{
64 struct udevice *bus;
65 struct uclass *uc;
66 int ret = -1;
67
68 ret = uclass_get(UCLASS_PCI, &uc);
69 uclass_foreach_dev(bus, uc) {
70 if (bus->seq > ret)
71 ret = bus->seq;
72 }
73
74 debug("%s: ret=%d\n", __func__, ret);
75
76 return ret;
77}
78
79int pci_last_busno(void)
80{
Bin Meng069155c2015-10-01 00:36:01 -070081 return pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -070082}
83
84int pci_get_ff(enum pci_size_t size)
85{
86 switch (size) {
87 case PCI_SIZE_8:
88 return 0xff;
89 case PCI_SIZE_16:
90 return 0xffff;
91 default:
92 return 0xffffffff;
93 }
94}
95
96int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
97 struct udevice **devp)
98{
99 struct udevice *dev;
100
101 for (device_find_first_child(bus, &dev);
102 dev;
103 device_find_next_child(&dev)) {
104 struct pci_child_platdata *pplat;
105
106 pplat = dev_get_parent_platdata(dev);
107 if (pplat && pplat->devfn == find_devfn) {
108 *devp = dev;
109 return 0;
110 }
111 }
112
113 return -ENODEV;
114}
115
Simon Glassf3f1fae2015-11-29 13:17:48 -0700116int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassff3e0772015-03-05 12:25:25 -0700117{
118 struct udevice *bus;
119 int ret;
120
Simon Glass983c6ba22015-08-31 18:55:35 -0600121 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700122 if (ret)
123 return ret;
124 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
125}
126
127static int pci_device_matches_ids(struct udevice *dev,
128 struct pci_device_id *ids)
129{
130 struct pci_child_platdata *pplat;
131 int i;
132
133 pplat = dev_get_parent_platdata(dev);
134 if (!pplat)
135 return -EINVAL;
136 for (i = 0; ids[i].vendor != 0; i++) {
137 if (pplat->vendor == ids[i].vendor &&
138 pplat->device == ids[i].device)
139 return i;
140 }
141
142 return -EINVAL;
143}
144
145int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
146 int *indexp, struct udevice **devp)
147{
148 struct udevice *dev;
149
150 /* Scan all devices on this bus */
151 for (device_find_first_child(bus, &dev);
152 dev;
153 device_find_next_child(&dev)) {
154 if (pci_device_matches_ids(dev, ids) >= 0) {
155 if ((*indexp)-- <= 0) {
156 *devp = dev;
157 return 0;
158 }
159 }
160 }
161
162 return -ENODEV;
163}
164
165int pci_find_device_id(struct pci_device_id *ids, int index,
166 struct udevice **devp)
167{
168 struct udevice *bus;
169
170 /* Scan all known buses */
171 for (uclass_first_device(UCLASS_PCI, &bus);
172 bus;
173 uclass_next_device(&bus)) {
174 if (!pci_bus_find_devices(bus, ids, &index, devp))
175 return 0;
176 }
177 *devp = NULL;
178
179 return -ENODEV;
180}
181
Simon Glass5c0bf642015-11-29 13:17:50 -0700182static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
183 unsigned int device, int *indexp,
184 struct udevice **devp)
185{
186 struct pci_child_platdata *pplat;
187 struct udevice *dev;
188
189 for (device_find_first_child(bus, &dev);
190 dev;
191 device_find_next_child(&dev)) {
192 pplat = dev_get_parent_platdata(dev);
193 if (pplat->vendor == vendor && pplat->device == device) {
194 if (!(*indexp)--) {
195 *devp = dev;
196 return 0;
197 }
198 }
199 }
200
201 return -ENODEV;
202}
203
204int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
205 struct udevice **devp)
206{
207 struct udevice *bus;
208
209 /* Scan all known buses */
210 for (uclass_first_device(UCLASS_PCI, &bus);
211 bus;
212 uclass_next_device(&bus)) {
213 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
214 return device_probe(*devp);
215 }
216 *devp = NULL;
217
218 return -ENODEV;
219}
220
Simon Glassa0eb8352015-11-29 13:17:52 -0700221int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
222{
223 struct udevice *dev;
224
225 /* Scan all known buses */
226 for (pci_find_first_device(&dev);
227 dev;
228 pci_find_next_device(&dev)) {
229 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
230
231 if (pplat->class == find_class && !index--) {
232 *devp = dev;
233 return device_probe(*devp);
234 }
235 }
236 *devp = NULL;
237
238 return -ENODEV;
239}
240
Simon Glassff3e0772015-03-05 12:25:25 -0700241int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
242 unsigned long value, enum pci_size_t size)
243{
244 struct dm_pci_ops *ops;
245
246 ops = pci_get_ops(bus);
247 if (!ops->write_config)
248 return -ENOSYS;
249 return ops->write_config(bus, bdf, offset, value, size);
250}
251
Simon Glass319dba12016-03-06 19:27:52 -0700252int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
253 u32 clr, u32 set)
254{
255 ulong val;
256 int ret;
257
258 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
259 if (ret)
260 return ret;
261 val &= ~clr;
262 val |= set;
263
264 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
265}
266
Simon Glassff3e0772015-03-05 12:25:25 -0700267int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
268 enum pci_size_t size)
269{
270 struct udevice *bus;
271 int ret;
272
Simon Glass983c6ba22015-08-31 18:55:35 -0600273 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700274 if (ret)
275 return ret;
276
Bin Meng4d8615c2015-07-19 00:20:04 +0800277 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700278}
279
Simon Glass66afb4e2015-08-10 07:05:03 -0600280int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
281 enum pci_size_t size)
282{
283 struct udevice *bus;
284
Bin Meng1e0f2262015-09-11 03:24:34 -0700285 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600286 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700287 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
288 size);
Simon Glass66afb4e2015-08-10 07:05:03 -0600289}
290
Simon Glassff3e0772015-03-05 12:25:25 -0700291int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
292{
293 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
294}
295
296int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
297{
298 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
299}
300
301int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
302{
303 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
304}
305
Simon Glass66afb4e2015-08-10 07:05:03 -0600306int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
307{
308 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
309}
310
311int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
312{
313 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
314}
315
316int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
317{
318 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
319}
320
Simon Glassff3e0772015-03-05 12:25:25 -0700321int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
322 unsigned long *valuep, enum pci_size_t size)
323{
324 struct dm_pci_ops *ops;
325
326 ops = pci_get_ops(bus);
327 if (!ops->read_config)
328 return -ENOSYS;
329 return ops->read_config(bus, bdf, offset, valuep, size);
330}
331
332int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
333 enum pci_size_t size)
334{
335 struct udevice *bus;
336 int ret;
337
Simon Glass983c6ba22015-08-31 18:55:35 -0600338 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700339 if (ret)
340 return ret;
341
Bin Meng4d8615c2015-07-19 00:20:04 +0800342 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700343}
344
Simon Glass66afb4e2015-08-10 07:05:03 -0600345int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
346 enum pci_size_t size)
347{
348 struct udevice *bus;
349
Bin Meng1e0f2262015-09-11 03:24:34 -0700350 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600351 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700352 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass66afb4e2015-08-10 07:05:03 -0600353 size);
354}
355
Simon Glassff3e0772015-03-05 12:25:25 -0700356int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
357{
358 unsigned long value;
359 int ret;
360
361 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
362 if (ret)
363 return ret;
364 *valuep = value;
365
366 return 0;
367}
368
369int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
370{
371 unsigned long value;
372 int ret;
373
374 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
375 if (ret)
376 return ret;
377 *valuep = value;
378
379 return 0;
380}
381
382int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
383{
384 unsigned long value;
385 int ret;
386
387 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
388 if (ret)
389 return ret;
390 *valuep = value;
391
392 return 0;
393}
394
Simon Glass66afb4e2015-08-10 07:05:03 -0600395int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
396{
397 unsigned long value;
398 int ret;
399
400 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
401 if (ret)
402 return ret;
403 *valuep = value;
404
405 return 0;
406}
407
408int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
409{
410 unsigned long value;
411 int ret;
412
413 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
414 if (ret)
415 return ret;
416 *valuep = value;
417
418 return 0;
419}
420
421int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
422{
423 unsigned long value;
424 int ret;
425
426 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
427 if (ret)
428 return ret;
429 *valuep = value;
430
431 return 0;
432}
433
Simon Glass319dba12016-03-06 19:27:52 -0700434int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
435{
436 u8 val;
437 int ret;
438
439 ret = dm_pci_read_config8(dev, offset, &val);
440 if (ret)
441 return ret;
442 val &= ~clr;
443 val |= set;
444
445 return dm_pci_write_config8(dev, offset, val);
446}
447
448int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
449{
450 u16 val;
451 int ret;
452
453 ret = dm_pci_read_config16(dev, offset, &val);
454 if (ret)
455 return ret;
456 val &= ~clr;
457 val |= set;
458
459 return dm_pci_write_config16(dev, offset, val);
460}
461
462int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
463{
464 u32 val;
465 int ret;
466
467 ret = dm_pci_read_config32(dev, offset, &val);
468 if (ret)
469 return ret;
470 val &= ~clr;
471 val |= set;
472
473 return dm_pci_write_config32(dev, offset, val);
474}
475
Bin Mengbbbcb522015-10-01 00:36:02 -0700476static void set_vga_bridge_bits(struct udevice *dev)
477{
478 struct udevice *parent = dev->parent;
479 u16 bc;
480
481 while (parent->seq != 0) {
482 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
483 bc |= PCI_BRIDGE_CTL_VGA;
484 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
485 parent = parent->parent;
486 }
487}
488
Simon Glassff3e0772015-03-05 12:25:25 -0700489int pci_auto_config_devices(struct udevice *bus)
490{
491 struct pci_controller *hose = bus->uclass_priv;
Bin Mengbbbcb522015-10-01 00:36:02 -0700492 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -0700493 unsigned int sub_bus;
494 struct udevice *dev;
495 int ret;
496
497 sub_bus = bus->seq;
498 debug("%s: start\n", __func__);
499 pciauto_config_init(hose);
500 for (ret = device_find_first_child(bus, &dev);
501 !ret && dev;
502 ret = device_find_next_child(&dev)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700503 unsigned int max_bus;
Simon Glass4d214552015-09-08 17:52:47 -0600504 int ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700505
Simon Glassff3e0772015-03-05 12:25:25 -0700506 debug("%s: device %s\n", __func__, dev->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700507 ret = dm_pciauto_config_device(dev);
Simon Glass4d214552015-09-08 17:52:47 -0600508 if (ret < 0)
509 return ret;
510 max_bus = ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700511 sub_bus = max(sub_bus, max_bus);
Bin Mengbbbcb522015-10-01 00:36:02 -0700512
513 pplat = dev_get_parent_platdata(dev);
514 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
515 set_vga_bridge_bits(dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700516 }
517 debug("%s: done\n", __func__);
518
519 return sub_bus;
520}
521
Simon Glass5e23b8b2015-11-29 13:17:49 -0700522int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassff3e0772015-03-05 12:25:25 -0700523{
Simon Glassff3e0772015-03-05 12:25:25 -0700524 int sub_bus;
525 int ret;
526
527 debug("%s\n", __func__);
Simon Glassff3e0772015-03-05 12:25:25 -0700528
529 sub_bus = pci_get_bus_max() + 1;
530 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700531 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700532
533 ret = device_probe(bus);
534 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600535 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassff3e0772015-03-05 12:25:25 -0700536 ret);
537 return ret;
538 }
539 if (sub_bus != bus->seq) {
540 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
541 __func__, bus->name, bus->seq, sub_bus);
542 return -EPIPE;
543 }
544 sub_bus = pci_get_bus_max();
Simon Glass5e23b8b2015-11-29 13:17:49 -0700545 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700546
547 return sub_bus;
548}
549
Simon Glassaba92962015-07-06 16:47:44 -0600550/**
551 * pci_match_one_device - Tell if a PCI device structure has a matching
552 * PCI device id structure
553 * @id: single PCI device id structure to match
554 * @dev: the PCI device structure to match against
555 *
556 * Returns the matching pci_device_id structure or %NULL if there is no match.
557 */
558static bool pci_match_one_id(const struct pci_device_id *id,
559 const struct pci_device_id *find)
560{
561 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
562 (id->device == PCI_ANY_ID || id->device == find->device) &&
563 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
564 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
565 !((id->class ^ find->class) & id->class_mask))
566 return true;
567
568 return false;
569}
570
571/**
572 * pci_find_and_bind_driver() - Find and bind the right PCI driver
573 *
574 * This only looks at certain fields in the descriptor.
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600575 *
576 * @parent: Parent bus
577 * @find_id: Specification of the driver to find
578 * @bdf: Bus/device/function addreess - see PCI_BDF()
579 * @devp: Returns a pointer to the device created
580 * @return 0 if OK, -EPERM if the device is not needed before relocation and
581 * therefore was not created, other -ve value on error
Simon Glassaba92962015-07-06 16:47:44 -0600582 */
583static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600584 struct pci_device_id *find_id,
585 pci_dev_t bdf, struct udevice **devp)
Simon Glassaba92962015-07-06 16:47:44 -0600586{
587 struct pci_driver_entry *start, *entry;
588 const char *drv;
589 int n_ents;
590 int ret;
591 char name[30], *str;
Bin Meng08fc7b82015-08-20 06:40:17 -0700592 bool bridge;
Simon Glassaba92962015-07-06 16:47:44 -0600593
594 *devp = NULL;
595
596 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
597 find_id->vendor, find_id->device);
598 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
599 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
600 for (entry = start; entry != start + n_ents; entry++) {
601 const struct pci_device_id *id;
602 struct udevice *dev;
603 const struct driver *drv;
604
605 for (id = entry->match;
606 id->vendor || id->subvendor || id->class_mask;
607 id++) {
608 if (!pci_match_one_id(id, find_id))
609 continue;
610
611 drv = entry->driver;
Bin Meng08fc7b82015-08-20 06:40:17 -0700612
613 /*
614 * In the pre-relocation phase, we only bind devices
615 * whose driver has the DM_FLAG_PRE_RELOC set, to save
616 * precious memory space as on some platforms as that
617 * space is pretty limited (ie: using Cache As RAM).
618 */
619 if (!(gd->flags & GD_FLG_RELOC) &&
620 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600621 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700622
Simon Glassaba92962015-07-06 16:47:44 -0600623 /*
624 * We could pass the descriptor to the driver as
625 * platdata (instead of NULL) and allow its bind()
626 * method to return -ENOENT if it doesn't support this
627 * device. That way we could continue the search to
628 * find another driver. For now this doesn't seem
629 * necesssary, so just bind the first match.
630 */
631 ret = device_bind(parent, drv, drv->name, NULL, -1,
632 &dev);
633 if (ret)
634 goto error;
635 debug("%s: Match found: %s\n", __func__, drv->name);
636 dev->driver_data = find_id->driver_data;
637 *devp = dev;
638 return 0;
639 }
640 }
641
Bin Meng08fc7b82015-08-20 06:40:17 -0700642 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
643 /*
644 * In the pre-relocation phase, we only bind bridge devices to save
645 * precious memory space as on some platforms as that space is pretty
646 * limited (ie: using Cache As RAM).
647 */
648 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600649 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700650
Simon Glassaba92962015-07-06 16:47:44 -0600651 /* Bind a generic driver so that the device can be used */
Bin Meng4d8615c2015-07-19 00:20:04 +0800652 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
653 PCI_FUNC(bdf));
Simon Glassaba92962015-07-06 16:47:44 -0600654 str = strdup(name);
655 if (!str)
656 return -ENOMEM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700657 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
658
Simon Glassaba92962015-07-06 16:47:44 -0600659 ret = device_bind_driver(parent, drv, str, devp);
660 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600661 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
Simon Glassaba92962015-07-06 16:47:44 -0600662 return ret;
663 }
664 debug("%s: No match found: bound generic driver instead\n", __func__);
665
666 return 0;
667
668error:
669 debug("%s: No match found: error %d\n", __func__, ret);
670 return ret;
671}
672
Simon Glassff3e0772015-03-05 12:25:25 -0700673int pci_bind_bus_devices(struct udevice *bus)
674{
675 ulong vendor, device;
676 ulong header_type;
Bin Meng4d8615c2015-07-19 00:20:04 +0800677 pci_dev_t bdf, end;
Simon Glassff3e0772015-03-05 12:25:25 -0700678 bool found_multi;
679 int ret;
680
681 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800682 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
683 PCI_MAX_PCI_FUNCTIONS - 1);
Yoshinori Sato6d9f5b02016-04-25 15:41:01 +0900684 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
Bin Meng4d8615c2015-07-19 00:20:04 +0800685 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700686 struct pci_child_platdata *pplat;
687 struct udevice *dev;
688 ulong class;
689
Bin Meng4d8615c2015-07-19 00:20:04 +0800690 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassff3e0772015-03-05 12:25:25 -0700691 continue;
692 /* Check only the first access, we don't expect problems */
Bin Meng4d8615c2015-07-19 00:20:04 +0800693 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
Simon Glassff3e0772015-03-05 12:25:25 -0700694 &header_type, PCI_SIZE_8);
695 if (ret)
696 goto error;
Bin Meng4d8615c2015-07-19 00:20:04 +0800697 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
Simon Glassff3e0772015-03-05 12:25:25 -0700698 PCI_SIZE_16);
699 if (vendor == 0xffff || vendor == 0x0000)
700 continue;
701
Bin Meng4d8615c2015-07-19 00:20:04 +0800702 if (!PCI_FUNC(bdf))
Simon Glassff3e0772015-03-05 12:25:25 -0700703 found_multi = header_type & 0x80;
704
705 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
Bin Meng4d8615c2015-07-19 00:20:04 +0800706 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
707 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassff3e0772015-03-05 12:25:25 -0700708 PCI_SIZE_16);
Bin Meng4d8615c2015-07-19 00:20:04 +0800709 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glassaba92962015-07-06 16:47:44 -0600710 PCI_SIZE_32);
711 class >>= 8;
Simon Glassff3e0772015-03-05 12:25:25 -0700712
713 /* Find this device in the device tree */
Bin Meng4d8615c2015-07-19 00:20:04 +0800714 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700715
Simon Glass8bd42522015-11-29 13:18:09 -0700716 /* If nothing in the device tree, bind a device */
Simon Glassff3e0772015-03-05 12:25:25 -0700717 if (ret == -ENODEV) {
Simon Glassaba92962015-07-06 16:47:44 -0600718 struct pci_device_id find_id;
719 ulong val;
Simon Glassff3e0772015-03-05 12:25:25 -0700720
Simon Glassaba92962015-07-06 16:47:44 -0600721 memset(&find_id, '\0', sizeof(find_id));
722 find_id.vendor = vendor;
723 find_id.device = device;
724 find_id.class = class;
725 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng4d8615c2015-07-19 00:20:04 +0800726 pci_bus_read_config(bus, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600727 PCI_SUBSYSTEM_VENDOR_ID,
728 &val, PCI_SIZE_32);
729 find_id.subvendor = val & 0xffff;
730 find_id.subdevice = val >> 16;
731 }
Bin Meng4d8615c2015-07-19 00:20:04 +0800732 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600733 &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700734 }
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600735 if (ret == -EPERM)
736 continue;
737 else if (ret)
Simon Glassff3e0772015-03-05 12:25:25 -0700738 return ret;
739
740 /* Update the platform data */
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600741 pplat = dev_get_parent_platdata(dev);
742 pplat->devfn = PCI_MASK_BUS(bdf);
743 pplat->vendor = vendor;
744 pplat->device = device;
745 pplat->class = class;
Simon Glassff3e0772015-03-05 12:25:25 -0700746 }
747
748 return 0;
749error:
750 printf("Cannot read bus configuration: %d\n", ret);
751
752 return ret;
753}
754
Simon Glassff3e0772015-03-05 12:25:25 -0700755static int decode_regions(struct pci_controller *hose, const void *blob,
756 int parent_node, int node)
757{
758 int pci_addr_cells, addr_cells, size_cells;
Simon Glass2084c5a2015-11-19 20:26:57 -0700759 phys_addr_t base = 0, size;
Simon Glassff3e0772015-03-05 12:25:25 -0700760 int cells_per_record;
761 const u32 *prop;
762 int len;
763 int i;
764
765 prop = fdt_getprop(blob, node, "ranges", &len);
766 if (!prop)
767 return -EINVAL;
768 pci_addr_cells = fdt_address_cells(blob, node);
769 addr_cells = fdt_address_cells(blob, parent_node);
770 size_cells = fdt_size_cells(blob, node);
771
772 /* PCI addresses are always 3-cells */
773 len /= sizeof(u32);
774 cells_per_record = pci_addr_cells + addr_cells + size_cells;
775 hose->region_count = 0;
776 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
777 cells_per_record);
778 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
779 u64 pci_addr, addr, size;
780 int space_code;
781 u32 flags;
782 int type;
Simon Glass9526d832015-11-19 20:26:58 -0700783 int pos;
Simon Glassff3e0772015-03-05 12:25:25 -0700784
785 if (len < cells_per_record)
786 break;
787 flags = fdt32_to_cpu(prop[0]);
788 space_code = (flags >> 24) & 3;
789 pci_addr = fdtdec_get_number(prop + 1, 2);
790 prop += pci_addr_cells;
791 addr = fdtdec_get_number(prop, addr_cells);
792 prop += addr_cells;
793 size = fdtdec_get_number(prop, size_cells);
794 prop += size_cells;
795 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
796 ", size=%" PRIx64 ", space_code=%d\n", __func__,
797 hose->region_count, pci_addr, addr, size, space_code);
798 if (space_code & 2) {
799 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
800 PCI_REGION_MEM;
801 } else if (space_code & 1) {
802 type = PCI_REGION_IO;
803 } else {
804 continue;
805 }
Simon Glass9526d832015-11-19 20:26:58 -0700806 pos = -1;
807 for (i = 0; i < hose->region_count; i++) {
808 if (hose->regions[i].flags == type)
809 pos = i;
810 }
811 if (pos == -1)
812 pos = hose->region_count++;
813 debug(" - type=%d, pos=%d\n", type, pos);
814 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassff3e0772015-03-05 12:25:25 -0700815 }
816
817 /* Add a region for our local memory */
Simon Glass2084c5a2015-11-19 20:26:57 -0700818 size = gd->ram_size;
819#ifdef CONFIG_SYS_SDRAM_BASE
820 base = CONFIG_SYS_SDRAM_BASE;
821#endif
822 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
823 size = gd->pci_ram_top - base;
824 pci_set_region(hose->regions + hose->region_count++, base, base,
825 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Simon Glassff3e0772015-03-05 12:25:25 -0700826
827 return 0;
828}
829
830static int pci_uclass_pre_probe(struct udevice *bus)
831{
832 struct pci_controller *hose;
833 int ret;
834
835 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
836 bus->parent->name);
837 hose = bus->uclass_priv;
838
839 /* For bridges, use the top-level PCI controller */
840 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
841 hose->ctlr = bus;
842 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
843 bus->of_offset);
844 if (ret) {
845 debug("%s: Cannot decode regions\n", __func__);
846 return ret;
847 }
848 } else {
849 struct pci_controller *parent_hose;
850
851 parent_hose = dev_get_uclass_priv(bus->parent);
852 hose->ctlr = parent_hose->bus;
853 }
854 hose->bus = bus;
855 hose->first_busno = bus->seq;
856 hose->last_busno = bus->seq;
857
858 return 0;
859}
860
861static int pci_uclass_post_probe(struct udevice *bus)
862{
863 int ret;
864
Simon Glassff3e0772015-03-05 12:25:25 -0700865 debug("%s: probing bus %d\n", __func__, bus->seq);
866 ret = pci_bind_bus_devices(bus);
867 if (ret)
868 return ret;
869
870#ifdef CONFIG_PCI_PNP
871 ret = pci_auto_config_devices(bus);
Simon Glass4d214552015-09-08 17:52:47 -0600872 if (ret < 0)
873 return ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700874#endif
875
Bin Meng348b7442015-08-20 06:40:23 -0700876#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
877 /*
878 * Per Intel FSP specification, we should call FSP notify API to
879 * inform FSP that PCI enumeration has been done so that FSP will
880 * do any necessary initialization as required by the chipset's
881 * BIOS Writer's Guide (BWG).
882 *
883 * Unfortunately we have to put this call here as with driver model,
884 * the enumeration is all done on a lazy basis as needed, so until
885 * something is touched on PCI it won't happen.
886 *
887 * Note we only call this 1) after U-Boot is relocated, and 2)
888 * root bus has finished probing.
889 */
Simon Glass4d214552015-09-08 17:52:47 -0600890 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
Bin Meng348b7442015-08-20 06:40:23 -0700891 ret = fsp_init_phase_pci();
Simon Glass4d214552015-09-08 17:52:47 -0600892 if (ret)
893 return ret;
894 }
Bin Meng348b7442015-08-20 06:40:23 -0700895#endif
896
Simon Glass4d214552015-09-08 17:52:47 -0600897 return 0;
Simon Glassff3e0772015-03-05 12:25:25 -0700898}
899
900static int pci_uclass_child_post_bind(struct udevice *dev)
901{
902 struct pci_child_platdata *pplat;
903 struct fdt_pci_addr addr;
904 int ret;
905
906 if (dev->of_offset == -1)
907 return 0;
908
909 /*
910 * We could read vendor, device, class if available. But for now we
911 * just check the address.
912 */
913 pplat = dev_get_parent_platdata(dev);
914 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
915 FDT_PCI_SPACE_CONFIG, "reg", &addr);
916
917 if (ret) {
918 if (ret != -ENOENT)
919 return -EINVAL;
920 } else {
Bin Mengdce54dd2015-08-20 06:40:26 -0700921 /* extract the devfn from fdt_pci_addr */
922 pplat->devfn = addr.phys_hi & 0xff00;
Simon Glassff3e0772015-03-05 12:25:25 -0700923 }
924
925 return 0;
926}
927
Bin Meng4d8615c2015-07-19 00:20:04 +0800928static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
929 uint offset, ulong *valuep,
930 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -0700931{
932 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -0700933
934 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
935}
936
Bin Meng4d8615c2015-07-19 00:20:04 +0800937static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
938 uint offset, ulong value,
939 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -0700940{
941 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -0700942
943 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
944}
945
Simon Glass76c3fbc2015-08-10 07:05:04 -0600946static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
947{
948 struct udevice *dev;
949 int ret = 0;
950
951 /*
952 * Scan through all the PCI controllers. On x86 there will only be one
953 * but that is not necessarily true on other hardware.
954 */
955 do {
956 device_find_first_child(bus, &dev);
957 if (dev) {
958 *devp = dev;
959 return 0;
960 }
961 ret = uclass_next_device(&bus);
962 if (ret)
963 return ret;
964 } while (bus);
965
966 return 0;
967}
968
969int pci_find_next_device(struct udevice **devp)
970{
971 struct udevice *child = *devp;
972 struct udevice *bus = child->parent;
973 int ret;
974
975 /* First try all the siblings */
976 *devp = NULL;
977 while (child) {
978 device_find_next_child(&child);
979 if (child) {
980 *devp = child;
981 return 0;
982 }
983 }
984
985 /* We ran out of siblings. Try the next bus */
986 ret = uclass_next_device(&bus);
987 if (ret)
988 return ret;
989
990 return bus ? skip_to_next_device(bus, devp) : 0;
991}
992
993int pci_find_first_device(struct udevice **devp)
994{
995 struct udevice *bus;
996 int ret;
997
998 *devp = NULL;
999 ret = uclass_first_device(UCLASS_PCI, &bus);
1000 if (ret)
1001 return ret;
1002
1003 return skip_to_next_device(bus, devp);
1004}
1005
Simon Glass9289db62015-11-19 20:26:59 -07001006ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1007{
1008 switch (size) {
1009 case PCI_SIZE_8:
1010 return (value >> ((offset & 3) * 8)) & 0xff;
1011 case PCI_SIZE_16:
1012 return (value >> ((offset & 2) * 8)) & 0xffff;
1013 default:
1014 return value;
1015 }
1016}
1017
1018ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1019 enum pci_size_t size)
1020{
1021 uint off_mask;
1022 uint val_mask, shift;
1023 ulong ldata, mask;
1024
1025 switch (size) {
1026 case PCI_SIZE_8:
1027 off_mask = 3;
1028 val_mask = 0xff;
1029 break;
1030 case PCI_SIZE_16:
1031 off_mask = 2;
1032 val_mask = 0xffff;
1033 break;
1034 default:
1035 return value;
1036 }
1037 shift = (offset & off_mask) * 8;
1038 ldata = (value & val_mask) << shift;
1039 mask = val_mask << shift;
1040 value = (old & ~mask) | ldata;
1041
1042 return value;
1043}
1044
Simon Glassf9260332015-11-19 20:27:01 -07001045int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1046 struct pci_region **memp, struct pci_region **prefp)
1047{
1048 struct udevice *bus = pci_get_controller(dev);
1049 struct pci_controller *hose = dev_get_uclass_priv(bus);
1050 int i;
1051
1052 *iop = NULL;
1053 *memp = NULL;
1054 *prefp = NULL;
1055 for (i = 0; i < hose->region_count; i++) {
1056 switch (hose->regions[i].flags) {
1057 case PCI_REGION_IO:
1058 if (!*iop || (*iop)->size < hose->regions[i].size)
1059 *iop = hose->regions + i;
1060 break;
1061 case PCI_REGION_MEM:
1062 if (!*memp || (*memp)->size < hose->regions[i].size)
1063 *memp = hose->regions + i;
1064 break;
1065 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1066 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1067 *prefp = hose->regions + i;
1068 break;
1069 }
1070 }
1071
1072 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1073}
1074
Simon Glassbab17cf2015-11-29 13:17:53 -07001075u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1076{
1077 u32 addr;
1078 int bar;
1079
1080 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1081 dm_pci_read_config32(dev, bar, &addr);
1082 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1083 return addr & PCI_BASE_ADDRESS_IO_MASK;
1084 else
1085 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1086}
1087
Simon Glass9d731c82016-01-18 20:19:15 -07001088void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1089{
1090 int bar;
1091
1092 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1093 dm_pci_write_config32(dev, bar, addr);
1094}
1095
Simon Glass21d1fe72015-11-29 13:18:03 -07001096static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1097 pci_addr_t bus_addr, unsigned long flags,
1098 unsigned long skip_mask, phys_addr_t *pa)
1099{
1100 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1101 struct pci_region *res;
1102 int i;
1103
1104 for (i = 0; i < hose->region_count; i++) {
1105 res = &hose->regions[i];
1106
1107 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1108 continue;
1109
1110 if (res->flags & skip_mask)
1111 continue;
1112
1113 if (bus_addr >= res->bus_start &&
1114 (bus_addr - res->bus_start) < res->size) {
1115 *pa = (bus_addr - res->bus_start + res->phys_start);
1116 return 0;
1117 }
1118 }
1119
1120 return 1;
1121}
1122
1123phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1124 unsigned long flags)
1125{
1126 phys_addr_t phys_addr = 0;
1127 struct udevice *ctlr;
1128 int ret;
1129
1130 /* The root controller has the region information */
1131 ctlr = pci_get_controller(dev);
1132
1133 /*
1134 * if PCI_REGION_MEM is set we do a two pass search with preference
1135 * on matches that don't have PCI_REGION_SYS_MEMORY set
1136 */
1137 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1138 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1139 flags, PCI_REGION_SYS_MEMORY,
1140 &phys_addr);
1141 if (!ret)
1142 return phys_addr;
1143 }
1144
1145 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1146
1147 if (ret)
1148 puts("pci_hose_bus_to_phys: invalid physical address\n");
1149
1150 return phys_addr;
1151}
1152
1153int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1154 unsigned long flags, unsigned long skip_mask,
1155 pci_addr_t *ba)
1156{
1157 struct pci_region *res;
1158 struct udevice *ctlr;
1159 pci_addr_t bus_addr;
1160 int i;
1161 struct pci_controller *hose;
1162
1163 /* The root controller has the region information */
1164 ctlr = pci_get_controller(dev);
1165 hose = dev_get_uclass_priv(ctlr);
1166
1167 for (i = 0; i < hose->region_count; i++) {
1168 res = &hose->regions[i];
1169
1170 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1171 continue;
1172
1173 if (res->flags & skip_mask)
1174 continue;
1175
1176 bus_addr = phys_addr - res->phys_start + res->bus_start;
1177
1178 if (bus_addr >= res->bus_start &&
1179 (bus_addr - res->bus_start) < res->size) {
1180 *ba = bus_addr;
1181 return 0;
1182 }
1183 }
1184
1185 return 1;
1186}
1187
1188pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1189 unsigned long flags)
1190{
1191 pci_addr_t bus_addr = 0;
1192 int ret;
1193
1194 /*
1195 * if PCI_REGION_MEM is set we do a two pass search with preference
1196 * on matches that don't have PCI_REGION_SYS_MEMORY set
1197 */
1198 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1199 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1200 PCI_REGION_SYS_MEMORY, &bus_addr);
1201 if (!ret)
1202 return bus_addr;
1203 }
1204
1205 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1206
1207 if (ret)
1208 puts("pci_hose_phys_to_bus: invalid physical address\n");
1209
1210 return bus_addr;
1211}
1212
1213void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1214{
1215 pci_addr_t pci_bus_addr;
1216 u32 bar_response;
1217
1218 /* read BAR address */
1219 dm_pci_read_config32(dev, bar, &bar_response);
1220 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1221
1222 /*
1223 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1224 * isn't actualy used on any platform because u-boot assumes a static
1225 * linear mapping. In the future, this could read the BAR size
1226 * and pass that as the size if needed.
1227 */
1228 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1229}
1230
Simon Glassff3e0772015-03-05 12:25:25 -07001231UCLASS_DRIVER(pci) = {
1232 .id = UCLASS_PCI,
1233 .name = "pci",
Simon Glass2bb02e42015-05-10 21:08:06 -06001234 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glass91195482016-07-05 17:10:10 -06001235 .post_bind = dm_scan_fdt_dev,
Simon Glassff3e0772015-03-05 12:25:25 -07001236 .pre_probe = pci_uclass_pre_probe,
1237 .post_probe = pci_uclass_post_probe,
1238 .child_post_bind = pci_uclass_child_post_bind,
1239 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1240 .per_child_platdata_auto_alloc_size =
1241 sizeof(struct pci_child_platdata),
1242};
1243
1244static const struct dm_pci_ops pci_bridge_ops = {
1245 .read_config = pci_bridge_read_config,
1246 .write_config = pci_bridge_write_config,
1247};
1248
1249static const struct udevice_id pci_bridge_ids[] = {
1250 { .compatible = "pci-bridge" },
1251 { }
1252};
1253
1254U_BOOT_DRIVER(pci_bridge_drv) = {
1255 .name = "pci_bridge_drv",
1256 .id = UCLASS_PCI,
1257 .of_match = pci_bridge_ids,
1258 .ops = &pci_bridge_ops,
1259};
1260
1261UCLASS_DRIVER(pci_generic) = {
1262 .id = UCLASS_PCI_GENERIC,
1263 .name = "pci_generic",
1264};
1265
1266static const struct udevice_id pci_generic_ids[] = {
1267 { .compatible = "pci-generic" },
1268 { }
1269};
1270
1271U_BOOT_DRIVER(pci_generic_drv) = {
1272 .name = "pci_generic_drv",
1273 .id = UCLASS_PCI_GENERIC,
1274 .of_match = pci_generic_ids,
1275};
Stephen Warrene578b922016-01-26 11:10:11 -07001276
1277void pci_init(void)
1278{
1279 struct udevice *bus;
1280
1281 /*
1282 * Enumerate all known controller devices. Enumeration has the side-
1283 * effect of probing them, so PCIe devices will be enumerated too.
1284 */
1285 for (uclass_first_device(UCLASS_PCI, &bus);
1286 bus;
1287 uclass_next_device(&bus)) {
1288 ;
1289 }
1290}