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wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf4675562002-10-02 14:20:15 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
21#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_DISPLAY_BOARDINFO
wdenkf4675562002-10-02 14:20:15 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
wdenkf4675562002-10-02 14:20:15 +000026#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020027#define CONFIG_SYS_SMC_RXBUFLEN 128
28#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000029#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenk6aff3112002-12-17 01:51:00 +000030
wdenkae3af052003-08-07 22:18:11 +000031#define CONFIG_BOOTCOUNT_LIMIT
wdenkf4675562002-10-02 14:20:15 +000032
wdenkf4675562002-10-02 14:20:15 +000033
34#define CONFIG_BOARD_TYPES 1 /* support board types */
35
wdenk6aff3112002-12-17 01:51:00 +000036#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010037 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk6aff3112002-12-17 01:51:00 +000038 "echo"
wdenkf4675562002-10-02 14:20:15 +000039
40#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000041
42#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000043 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000044 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010045 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000046 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010047 "addip=setenv bootargs ${bootargs} " \
48 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
49 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000050 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000052 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010053 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
54 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000055 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020056 "hostname=TQM855L\0" \
57 "bootfile=TQM855L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020058 "fdt_addr=40040000\0" \
59 "kernel_addr=40060000\0" \
60 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020061 "u-boot=TQM855L/u-image.bin\0" \
62 "load=tftp 200000 ${u-boot}\0" \
63 "update=prot off 40000000 +${filesize};" \
64 "era 40000000 +${filesize};" \
65 "cp.b 200000 40000000 ${filesize};" \
66 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000067 ""
68#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000069
70#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000072
73#undef CONFIG_WATCHDOG /* watchdog disabled */
74
75#define CONFIG_STATUS_LED 1 /* Status LED enabled */
76
77#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
78
Jon Loeliger37d4bb72007-07-09 21:38:02 -050079/*
80 * BOOTP options
81 */
82#define CONFIG_BOOTP_SUBNETMASK
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85#define CONFIG_BOOTP_BOOTPATH
86#define CONFIG_BOOTP_BOOTFILESIZE
87
wdenkf4675562002-10-02 14:20:15 +000088#define CONFIG_MAC_PARTITION
89#define CONFIG_DOS_PARTITION
90
91#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
92
Jon Loeliger26946902007-07-04 22:30:50 -050093/*
94 * Command line configuration.
95 */
Jon Loeliger26946902007-07-04 22:30:50 -050096#define CONFIG_CMD_DATE
Jon Loeliger26946902007-07-04 22:30:50 -050097#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +020098#define CONFIG_CMD_JFFS2
wdenkf4675562002-10-02 14:20:15 +000099
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200100#define CONFIG_NETCONSOLE
101
wdenkf4675562002-10-02 14:20:15 +0000102/*
103 * Miscellaneous configurable options
104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk6aff3112002-12-17 01:51:00 +0000106
Wolfgang Denk2751a952006-10-28 02:29:14 +0200107#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenk6aff3112002-12-17 01:51:00 +0000108
Jon Loeliger26946902007-07-04 22:30:50 -0500109#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000111#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000113#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
119#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000122
wdenkf4675562002-10-02 14:20:15 +0000123/*
124 * Low Level Configuration Settings
125 * (address mappings, register initial values, etc.)
126 * You should know what you are doing if you make changes here.
127 */
128/*-----------------------------------------------------------------------
129 * Internal Memory Mapped Register
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000132
133/*-----------------------------------------------------------------------
134 * Definitions for initial stack pointer and data area (in DPRAM)
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200137#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200138#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000140
141/*-----------------------------------------------------------------------
142 * Start addresses for the final memory configuration
143 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_SDRAM_BASE 0x00000000
147#define CONFIG_SYS_FLASH_BASE 0x40000000
148#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
149#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
150#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000151
152/*
153 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization.
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000158
159/*-----------------------------------------------------------------------
160 * FLASH organization
161 */
wdenkf4675562002-10-02 14:20:15 +0000162
Martin Krausee318d9e2007-09-27 11:10:08 +0200163/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200165#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
167#define CONFIG_SYS_FLASH_EMPTY_INFO
168#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
169#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
170#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000171
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200172#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200173#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
174#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000175
176/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200177#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
178#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200181
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200182#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
183
wdenkf4675562002-10-02 14:20:15 +0000184/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200185 * Dynamic MTD partition support
186 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100187#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200188#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
189#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200190#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
191
192#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
193 "128k(dtb)," \
194 "1664k(kernel)," \
195 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200196 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200197
198/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000199 * Hardware Information Block
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
202#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
203#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000204
205/*-----------------------------------------------------------------------
206 * Cache Configuration
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500209#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000211#endif
212
213/*-----------------------------------------------------------------------
214 * SYPCR - System Protection Control 11-9
215 * SYPCR can only be written once after reset!
216 *-----------------------------------------------------------------------
217 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
218 */
219#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000221 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
222#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000224#endif
225
226/*-----------------------------------------------------------------------
227 * SIUMCR - SIU Module Configuration 11-6
228 *-----------------------------------------------------------------------
229 * PCMCIA config., multi-function pin tri-state
230 */
231#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000233#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000235#endif /* CONFIG_CAN_DRIVER */
236
237/*-----------------------------------------------------------------------
238 * TBSCR - Time Base Status and Control 11-26
239 *-----------------------------------------------------------------------
240 * Clear Reference Interrupt Status, Timebase freezing enabled
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000243
244/*-----------------------------------------------------------------------
245 * RTCSC - Real-Time Clock Status and Control Register 11-27
246 *-----------------------------------------------------------------------
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000249
250/*-----------------------------------------------------------------------
251 * PISCR - Periodic Interrupt Status and Control 11-31
252 *-----------------------------------------------------------------------
253 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000256
257/*-----------------------------------------------------------------------
258 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
259 *-----------------------------------------------------------------------
260 * Reset PLL lock status sticky bit, timer expired status bit and timer
261 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000264
265/*-----------------------------------------------------------------------
266 * SCCR - System Clock and reset Control Register 15-27
267 *-----------------------------------------------------------------------
268 * Set clock output, timebase and RTC source and divider,
269 * power management and some other internal clocks
270 */
271#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000273 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
274 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000275
276/*-----------------------------------------------------------------------
277 * PCMCIA stuff
278 *-----------------------------------------------------------------------
279 *
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
282#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
283#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
284#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
285#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
286#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
287#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
288#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000289
290/*-----------------------------------------------------------------------
291 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
292 *-----------------------------------------------------------------------
293 */
294
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000295#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf4675562002-10-02 14:20:15 +0000296#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
297
298#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
299#undef CONFIG_IDE_LED /* LED for ide not supported */
300#undef CONFIG_IDE_RESET /* reset for ide not supported */
301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
303#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000306
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000308
309/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000311
312/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000314
315/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000317
wdenkf4675562002-10-02 14:20:15 +0000318/*-----------------------------------------------------------------------
319 *
320 *-----------------------------------------------------------------------
321 *
322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000324
325/*
326 * Init Memory Controller:
327 *
328 * BR0/1 and OR0/1 (FLASH)
329 */
330
331#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
332#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
333
334/* used to re-map FLASH both when starting from SRAM or FLASH:
335 * restrict access enough to keep SRAM working (if any)
336 * but not too much to meddle with FLASH accesses
337 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
339#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000340
341/*
342 * FLASH timing:
343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000345 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
348#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
349#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
352#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
353#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000354
355/*
356 * BR2/3 and OR2/3 (SDRAM)
357 *
358 */
359#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
360#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
361#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
362
363/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000365
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
367#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000368
369#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
371#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000372#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
374#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
375#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
376#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000377 BR_PS_8 | BR_MS_UPMB | BR_V )
378#endif /* CONFIG_CAN_DRIVER */
379
380/*
381 * Memory Periodic Timer Prescaler
382 *
383 * The Divider for PTA (refresh timer) configuration is based on an
384 * example SDRAM configuration (64 MBit, one bank). The adjustment to
385 * the number of chip selects (NCS) and the actually needed refresh
386 * rate is done by setting MPTPR.
387 *
388 * PTA is calculated from
389 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
390 *
391 * gclk CPU clock (not bus clock!)
392 * Trefresh Refresh cycle * 4 (four word bursts used)
393 *
394 * 4096 Rows from SDRAM example configuration
395 * 1000 factor s -> ms
396 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
397 * 4 Number of refresh cycles per period
398 * 64 Refresh cycle in ms per number of rows
399 * --------------------------------------------
400 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
401 *
402 * 50 MHz => 50.000.000 / Divider = 98
403 * 66 Mhz => 66.000.000 / Divider = 129
404 * 80 Mhz => 80.000.000 / Divider = 156
405 */
wdenke9132ea2004-04-24 23:23:30 +0000406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
408#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000409
410/*
411 * For 16 MBit, refresh rates could be 31.3 us
412 * (= 64 ms / 2K = 125 / quad bursts).
413 * For a simpler initialization, 15.6 us is used instead.
414 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
416 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000417 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
419#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000420
421/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
423#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000424
425/*
426 * MAMR settings for SDRAM
427 */
428
429/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000431 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
432 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
433/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000435 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
436 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
437
wdenkf4675562002-10-02 14:20:15 +0000438#define CONFIG_SCC1_ENET
wdenk6aff3112002-12-17 01:51:00 +0000439#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200440#define CONFIG_ETHPRIME "SCC"
wdenkf4675562002-10-02 14:20:15 +0000441
Heiko Schocher7026ead2010-02-09 15:50:27 +0100442#define CONFIG_HWCONFIG 1
443
wdenkf4675562002-10-02 14:20:15 +0000444#endif /* __CONFIG_H */