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Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +09001/*
2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +09007 */
8
9#ifndef __SH7785LCR_H
10#define __SH7785LCR_H
11
12#undef DEBUG
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090013#define CONFIG_CPU_SH7785 1
14#define CONFIG_SH7785LCR 1
15
16#define CONFIG_CMD_FLASH
17#define CONFIG_CMD_MEMORY
18#define CONFIG_CMD_PCI
19#define CONFIG_CMD_NET
20#define CONFIG_CMD_PING
21#define CONFIG_CMD_NFS
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090022#define CONFIG_CMD_SDRAM
23#define CONFIG_CMD_RUN
Mike Frysingerbdab39d2009-01-28 19:08:14 -050024#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu93752532010-12-08 14:00:24 +090025#define CONFIG_CMD_SH_ZIMAGEBOOT
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090026
27#define CONFIG_CMD_USB
28#define CONFIG_USB_STORAGE
29#define CONFIG_CMD_EXT2
30#define CONFIG_CMD_FAT
31#define CONFIG_DOS_PARTITION
32#define CONFIG_MAC_PARTITION
33
34#define CONFIG_BAUDRATE 115200
35#define CONFIG_BOOTDELAY 3
36#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
37
38#define CONFIG_EXTRA_ENV_SETTINGS \
39 "bootdevice=0:1\0" \
40 "usbload=usb reset;usbboot;usb stop;bootm\0"
41
42#define CONFIG_VERSION_VARIABLE
43#undef CONFIG_SHOW_BOOT_PROGRESS
44
45/* MEMORY */
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090046#if defined(CONFIG_SH_32BIT)
Nobuhiro Iwamatsu59272c62011-01-17 21:02:16 +090047#define CONFIG_SYS_TEXT_BASE 0x8FF80000
Nobuhiro Iwamatsu915d6b72010-10-05 16:58:05 +090048/* 0x40000000 - 0x47FFFFFF does not use */
49#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
50#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
51#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090052#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
53#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
54#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
55#define SH7785LCR_USB_BASE (0xa6000000)
56#else
Nobuhiro Iwamatsu59272c62011-01-17 21:02:16 +090057#define CONFIG_SYS_TEXT_BASE 0x0FF80000
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090058#define SH7785LCR_SDRAM_BASE (0x08000000)
59#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
60#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
61#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
62#define SH7785LCR_USB_BASE (0xb4000000)
Yoshihiro Shimodaada93182009-03-03 15:11:17 +090063#endif
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090064
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_LONGHELP
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_CBSIZE 256
67#define CONFIG_SYS_PBSIZE 256
68#define CONFIG_SYS_MAXARGS 16
69#define CONFIG_SYS_BARGSIZE 512
70#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090071
72/* SCIF */
Nobuhiro Iwamatsu1c981722008-08-28 14:53:31 +090073#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090074#define CONFIG_CONS_SCIF1 1
75#define CONFIG_SCIF_EXT_CLOCK 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#undef CONFIG_SYS_CONSOLE_INFO_QUIET
77#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
78#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090079
80
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
82#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090083 (SH7785LCR_SDRAM_SIZE) - \
84 4 * 1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_ALT_MEMTEST
86#undef CONFIG_SYS_MEMTEST_SCRATCH
87#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
90#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
91#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
94#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
95#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +090097
98/* FLASH */
Nobuhiro Iwamatsu1c981722008-08-28 14:53:31 +090099#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_FLASH_CFI
101#undef CONFIG_SYS_FLASH_QUIET_TEST
102#define CONFIG_SYS_FLASH_EMPTY_INFO
103#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
104#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_MAX_FLASH_BANKS 1
107#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900108 (0 * SH7785LCR_FLASH_BANK_SIZE) }
109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
111#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
112#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
113#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#undef CONFIG_SYS_FLASH_PROTECTION
116#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900117
118/* R8A66597 */
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900119#define CONFIG_USB_R8A66597_HCD
120#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
121#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
122#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
123#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
124
125/* PCI Controller */
126#define CONFIG_PCI
127#define CONFIG_SH4_PCI
128#define CONFIG_SH7780_PCI
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900129#if defined(CONFIG_SH_32BIT)
130#define CONFIG_SH7780_PCI_LSR 0x1ff00001
131#define CONFIG_SH7780_PCI_LAR 0x5f000000
132#define CONFIG_SH7780_PCI_BAR 0x5f000000
133#else
Yoshihiro Shimoda06b18162009-02-25 14:26:42 +0900134#define CONFIG_SH7780_PCI_LSR 0x07f00001
135#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
136#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900137#endif
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900138#define CONFIG_PCI_PNP
139#define CONFIG_PCI_SCAN_SHOW 1
140
141#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
142#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
143#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
144
145#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
146#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
147#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
148
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900149#if defined(CONFIG_SH_32BIT)
150#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
151#else
Yoshihiro Shimodab3061b42009-02-25 14:26:55 +0900152#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
Yoshihiro Shimodaada93182009-03-03 15:11:17 +0900153#endif
154#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
Yoshihiro Shimodab3061b42009-02-25 14:26:55 +0900155#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
156
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900157/* Network device (RTL8169) support */
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900158#define CONFIG_RTL8169
159
160/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200161#define CONFIG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900162#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200163#define CONFIG_ENV_SECT_SIZE (256 * 1024)
164#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
166#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200167#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900168
169/* Board Clock */
170/* The SCIF used external clock. system clock only used timer. */
171#define CONFIG_SYS_CLK_FREQ 50000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +0900172#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
173#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +0200174#define CONFIG_SYS_TMU_CLK_DIV 4
Nobuhiro Iwamatsu0d53a472008-08-31 22:45:08 +0900175
176#endif /* __SH7785LCR_H */