blob: 8141a46dc073f10627f894938b42449ac6df451b [file] [log] [blame]
Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
2 * Copyright 2007 Wind River Systems <www.windriver.com>
3 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * sbc8548 board configuration file
27 *
28 * Please refer to doc/README.sbc85xx for more info.
29 *
30 */
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/* High Level Configuration Options */
35#define CONFIG_BOOKE 1 /* BOOKE */
36#define CONFIG_E500 1 /* BOOKE e500 family */
37#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
38#define CONFIG_MPC8548 1 /* MPC8548 specific */
39#define CONFIG_SBC8548 1 /* SBC8548 board specific */
40
41#undef CONFIG_PCI /* enable any pci type devices */
42#undef CONFIG_PCI1 /* PCI controller 1 */
43#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
44#undef CONFIG_RIO
45#undef CONFIG_PCI2
46#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
47
48#define CONFIG_TSEC_ENET /* tsec ethernet support */
49#define CONFIG_ENV_OVERWRITE
Joe Hamman9e3ed392007-12-13 06:45:14 -060050
Joe Hamman9e3ed392007-12-13 06:45:14 -060051#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
52
Kumar Galae2b159d2008-01-16 09:05:27 -060053#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060054
Joe Hamman9e3ed392007-12-13 06:45:14 -060055#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */
56
57/*
58 * These can be toggled for performance analysis, otherwise use default.
59 */
60#define CONFIG_L2_CACHE /* toggle L2 cache */
61#define CONFIG_BTB /* toggle branch predition */
Joe Hamman9e3ed392007-12-13 06:45:14 -060062#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
63
64/*
65 * Only possible on E500 Version 2 or newer cores.
66 */
67#define CONFIG_ENABLE_36BIT_PHYS 1
68
69#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
70
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
72#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
73#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hamman9e3ed392007-12-13 06:45:14 -060074
75/*
76 * Base addresses -- Note these are effective addresses where the
77 * actual resources get mapped (not physical addresses)
78 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
80#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
81#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
82#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Joe Hamman9e3ed392007-12-13 06:45:14 -060083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
85#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
86#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
Joe Hamman9e3ed392007-12-13 06:45:14 -060087
Kumar Gala33b90792008-08-26 23:15:28 -050088/* DDR Setup */
89#define CONFIG_FSL_DDR2
90#undef CONFIG_FSL_DDR_INTERACTIVE
91#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
92#undef CONFIG_DDR_SPD
93#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Joe Hamman9e3ed392007-12-13 06:45:14 -060094
Kumar Gala33b90792008-08-26 23:15:28 -050095#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
96#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
99#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala33b90792008-08-26 23:15:28 -0500100#define CONFIG_VERY_BIG_RAM
101
102#define CONFIG_NUM_DDR_CONTROLLERS 1
103#define CONFIG_DIMM_SLOTS_PER_CTLR 1
104#define CONFIG_CHIP_SELECTS_PER_CTRL 2
105
106/* I2C addresses of SPD EEPROMs */
107#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600108
109/*
110 * Make sure required options are set
111 */
112#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600114#endif
115
116#undef CONFIG_CLOCKS_IN_MHZ
117
118/*
119 * FLASH on the Local Bus
120 * Two banks, one 8MB the other 64MB, using the CFI driver.
121 * Boot from BR0/OR0 bank at 0xff80_0000
122 * Alternate BR6/OR6 bank at 0xfb80_0000
123 *
124 * BR0:
125 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
126 * Port Size = 8 bits = BRx[19:20] = 01
127 * Use GPCM = BRx[24:26] = 000
128 * Valid = BRx[31] = 1
129 *
130 * 0 4 8 12 16 20 24 28
131 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0
132 *
133 * BR6:
134 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
135 * Port Size = 32 bits = BRx[19:20] = 11
136 * Use GPCM = BRx[24:26] = 000
137 * Valid = BRx[31] = 1
138 *
139 * 0 4 8 12 16 20 24 28
140 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6
141 *
142 * OR0:
143 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
144 * XAM = OR0[17:18] = 11
145 * CSNT = OR0[20] = 1
146 * ACS = half cycle delay = OR0[21:22] = 11
147 * SCY = 6 = OR0[24:27] = 0110
148 * TRLX = use relaxed timing = OR0[29] = 1
149 * EAD = use external address latch delay = OR0[31] = 1
150 *
151 * 0 4 8 12 16 20 24 28
152 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0
153 *
154 * OR6:
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400155 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600156 * XAM = OR6[17:18] = 11
157 * CSNT = OR6[20] = 1
158 * ACS = half cycle delay = OR6[21:22] = 11
159 * SCY = 6 = OR6[24:27] = 0110
160 * TRLX = use relaxed timing = OR6[29] = 1
161 * EAD = use external address latch delay = OR6[31] = 1
162 *
163 * 0 4 8 12 16 20 24 28
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400164 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6
Joe Hamman9e3ed392007-12-13 06:45:14 -0600165 */
166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
168#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_BR0_PRELIM 0xff800801
171#define CONFIG_SYS_BR6_PRELIM 0xfb801801
Joe Hamman9e3ed392007-12-13 06:45:14 -0600172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_OR0_PRELIM 0xff806e65
174#define CONFIG_SYS_OR6_PRELIM 0xf8006e65
Joe Hamman9e3ed392007-12-13 06:45:14 -0600175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
178#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
179#undef CONFIG_SYS_FLASH_CHECKSUM
180#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
181#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600184
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200185#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_FLASH_CFI
187#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600188
189/* CS5 = Local bus peripherals controlled by the EPLD */
190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BR5_PRELIM 0xf8000801
192#define CONFIG_SYS_OR5_PRELIM 0xff006e65
193#define CONFIG_SYS_EPLD_BASE 0xf8000000
194#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
195#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
196#define CONFIG_SYS_BD_REV 0xf8300000
197#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600198
199/*
200 * SDRAM on the Local Bus
201 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
203#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600204
205/*
206 * Base Register 3 and Option Register 3 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600208 *
209 * For BR3, need:
210 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
211 * port-size = 32-bits = BR2[19:20] = 11
212 * no parity checking = BR2[21:22] = 00
213 * SDRAM for MSEL = BR2[24:26] = 011
214 * Valid = BR[31] = 1
215 *
216 * 0 4 8 12 16 20 24 28
217 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
218 *
219 */
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_BR3_PRELIM 0xf0001861
Joe Hamman9e3ed392007-12-13 06:45:14 -0600222
223/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600225 *
226 * For OR3, need:
227 * 64MB mask for AM, OR3[0:7] = 1111 1100
228 * XAM, OR3[17:18] = 11
229 * 10 columns OR3[19-21] = 011
230 * 12 rows OR3[23-25] = 011
231 * EAD set for extra time OR[31] = 0
232 *
233 * 0 4 8 12 16 20 24 28
234 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
235 */
236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
240#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
241#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
242#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600243
244/*
245 * LSDMR masks
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
248#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
249#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
250#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
251#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
252#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
253#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
254#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
255#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
256#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
Joe Hamman9e3ed392007-12-13 06:45:14 -0600257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
259#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
260#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
261#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
262#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
263#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
264#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
265#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
Joe Hamman9e3ed392007-12-13 06:45:14 -0600266
267/*
268 * Common settings for all Local Bus SDRAM commands.
269 * At run time, either BSMA1516 (for CPU 1.1)
270 * or BSMA1617 (for CPU 1.0) (old)
271 * is OR'ed in too.
272 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \
274 | CONFIG_SYS_LBC_LSDMR_PRETOACT7 \
275 | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
276 | CONFIG_SYS_LBC_LSDMR_BL8 \
277 | CONFIG_SYS_LBC_LSDMR_WRC4 \
278 | CONFIG_SYS_LBC_LSDMR_CL3 \
279 | CONFIG_SYS_LBC_LSDMR_RFEN \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600280 )
281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_INIT_RAM_LOCK 1
283#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
284#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
289#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
290#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hamman9e3ed392007-12-13 06:45:14 -0600291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
293#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600294
295/* Serial Port */
296#define CONFIG_CONS_INDEX 1
297#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_NS16550
299#define CONFIG_SYS_NS16550_SERIAL
300#define CONFIG_SYS_NS16550_REG_SIZE 1
301#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600304 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
307#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600308
309/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_HUSH_PARSER
311#ifdef CONFIG_SYS_HUSH_PARSER
312#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Joe Hamman9e3ed392007-12-13 06:45:14 -0600313#endif
314
315/* pass open firmware flat tree */
316#define CONFIG_OF_LIBFDT 1
317#define CONFIG_OF_BOARD_SETUP 1
318#define CONFIG_OF_STDOUT_VIA_ALIAS 1
319
320/*
321 * I2C
322 */
323#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
324#define CONFIG_HARD_I2C /* I2C with hardware support*/
325#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
327#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
328#define CONFIG_SYS_I2C_SLAVE 0x7F
329#define CONFIG_SYS_I2C_OFFSET 0x3000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600330
331/*
332 * General PCI
333 * Memory space is mapped 1-1, but I/O space must start from 0.
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
338#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
339#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
340#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
341#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
342#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600343
344#ifdef CONFIG_PCI2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
346#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
347#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
348#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
349#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
350#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600351#endif
352
353#ifdef CONFIG_PCIE1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
355#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
356#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
357#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
358#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
359#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600360#endif
361
362#ifdef CONFIG_RIO
363/*
364 * RapidIO MMU
365 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
367#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600368#endif
369
370#ifdef CONFIG_LEGACY
371#define BRIDGE_ID 17
372#define VIA_ID 2
373#else
374#define BRIDGE_ID 28
375#define VIA_ID 4
376#endif
377
378#if defined(CONFIG_PCI)
379
380#define CONFIG_NET_MULTI
381#define CONFIG_PCI_PNP /* do pci plug-and-play */
382
383#undef CONFIG_EEPRO100
384#undef CONFIG_TULIP
385
386#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
387
Joe Hamman9e3ed392007-12-13 06:45:14 -0600388#endif /* CONFIG_PCI */
389
390
391#if defined(CONFIG_TSEC_ENET)
392
393#ifndef CONFIG_NET_MULTI
394#define CONFIG_NET_MULTI 1
395#endif
396
397#define CONFIG_MII 1 /* MII PHY management */
398#define CONFIG_TSEC1 1
399#define CONFIG_TSEC1_NAME "eTSEC0"
400#define CONFIG_TSEC2 1
401#define CONFIG_TSEC2_NAME "eTSEC1"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600402#undef CONFIG_MPC85XX_FEC
403
Paul Gortmaker58da8892008-12-11 15:47:50 -0500404#define TSEC1_PHY_ADDR 0x19
405#define TSEC2_PHY_ADDR 0x1a
Joe Hamman9e3ed392007-12-13 06:45:14 -0600406
407#define TSEC1_PHYIDX 0
408#define TSEC2_PHYIDX 0
Paul Gortmakerbd931052008-12-11 15:47:49 -0500409
Joe Hamman9e3ed392007-12-13 06:45:14 -0600410#define TSEC1_FLAGS TSEC_GIGABIT
411#define TSEC2_FLAGS TSEC_GIGABIT
Joe Hamman9e3ed392007-12-13 06:45:14 -0600412
413/* Options are: eTSEC[0-3] */
414#define CONFIG_ETHPRIME "eTSEC0"
415#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
416#endif /* CONFIG_TSEC_ENET */
417
418/*
419 * Environment
420 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200421#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200423#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
424#define CONFIG_ENV_SIZE 0x2000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600425
426#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600428
429/*
430 * BOOTP options
431 */
432#define CONFIG_BOOTP_BOOTFILESIZE
433#define CONFIG_BOOTP_BOOTPATH
434#define CONFIG_BOOTP_GATEWAY
435#define CONFIG_BOOTP_HOSTNAME
436
437
438/*
439 * Command line configuration.
440 */
441#include <config_cmd_default.h>
442
443#define CONFIG_CMD_PING
444#define CONFIG_CMD_I2C
445#define CONFIG_CMD_MII
446#define CONFIG_CMD_ELF
447
448#if defined(CONFIG_PCI)
449 #define CONFIG_CMD_PCI
450#endif
451
452
453#undef CONFIG_WATCHDOG /* watchdog disabled */
454
455/*
456 * Miscellaneous configurable options
457 */
Paul Gortmakerad22f922008-12-11 15:47:51 -0500458#define CONFIG_CMDLINE_EDITING /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_LONGHELP /* undef to save memory */
460#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
461#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600462#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600464#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600466#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
468#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
469#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
470#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600471
472/*
473 * For booting Linux, the board info and command line data
474 * have to be in the first 8 MB of memory, since this is
475 * the maximum mapped by the Linux kernel during initialization.
476 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600478
Joe Hamman9e3ed392007-12-13 06:45:14 -0600479/*
480 * Internal Definitions
481 *
482 * Boot Flags
483 */
484#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
485#define BOOTFLAG_WARM 0x02 /* Software reboot */
486
487#if defined(CONFIG_CMD_KGDB)
488#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
489#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
490#endif
491
492/*
493 * Environment Configuration
494 */
495
496/* The mac addresses for all ethernet interface */
497#if defined(CONFIG_TSEC_ENET)
498#define CONFIG_HAS_ETH0
499#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
500#define CONFIG_HAS_ETH1
501#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600502#endif
503
504#define CONFIG_IPADDR 192.168.0.55
505
506#define CONFIG_HOSTNAME sbc8548
507#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
508#define CONFIG_BOOTFILE /uImage
509#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
510
511#define CONFIG_SERVERIP 192.168.0.2
512#define CONFIG_GATEWAYIP 192.168.0.1
513#define CONFIG_NETMASK 255.255.255.0
514
515#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
516
517#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
518#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
519
520#define CONFIG_BAUDRATE 115200
521
522#define CONFIG_EXTRA_ENV_SETTINGS \
523 "netdev=eth0\0" \
524 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
525 "tftpflash=tftpboot $loadaddr $uboot; " \
526 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
527 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
528 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
529 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
530 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
531 "consoledev=ttyS0\0" \
532 "ramdiskaddr=2000000\0" \
533 "ramdiskfile=uRamdisk\0" \
534 "fdtaddr=c00000\0" \
535 "fdtfile=sbc8548.dtb\0"
536
537#define CONFIG_NFSBOOTCOMMAND \
538 "setenv bootargs root=/dev/nfs rw " \
539 "nfsroot=$serverip:$rootpath " \
540 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
541 "console=$consoledev,$baudrate $othbootargs;" \
542 "tftp $loadaddr $bootfile;" \
543 "tftp $fdtaddr $fdtfile;" \
544 "bootm $loadaddr - $fdtaddr"
545
546
547#define CONFIG_RAMBOOTCOMMAND \
548 "setenv bootargs root=/dev/ram rw " \
549 "console=$consoledev,$baudrate $othbootargs;" \
550 "tftp $ramdiskaddr $ramdiskfile;" \
551 "tftp $loadaddr $bootfile;" \
552 "tftp $fdtaddr $fdtfile;" \
553 "bootm $loadaddr $ramdiskaddr $fdtaddr"
554
555#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
556
557#endif /* __CONFIG_H */