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Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +00001/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated.
4 * Sricharan R <r.sricharan@ti.com>
5 *
6 * Derived from OMAP4 done by:
7 * Aneesh V <aneesh@ti.com>
8 *
9 * TI OMAP5 AND DRA7XX common configuration settings
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Tom Rinia8017572013-08-09 11:22:18 -040012 *
13 * For more details, please see the technical documents listed at
14 * http://www.ti.com/product/omap5432
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000015 */
16
Enric Balletbò i Serra3d657a02013-12-06 21:30:19 +010017#ifndef __CONFIG_TI_OMAP5_COMMON_H
18#define __CONFIG_TI_OMAP5_COMMON_H
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000019
Praveen Rao5f603762015-03-09 17:12:06 -050020/* Common ARM Erratas */
21#define CONFIG_ARM_ERRATA_798870
22
Tom Rinia8017572013-08-09 11:22:18 -040023/* Use General purpose timer 1 */
24#define CONFIG_SYS_TIMERBASE GPT2_BASE
25
Tom Rini078aa4f2013-08-20 08:53:52 -040026/*
27 * For the DDR timing information we can either dynamically determine
28 * the timings to use or use pre-determined timings (based on using the
29 * dynamic method. Default to the static timing infomation.
30 */
Tom Rinia8017572013-08-09 11:22:18 -040031#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
Tom Rinia8017572013-08-09 11:22:18 -040032#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
33#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
34#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
35#endif
36
Tom Rinia8017572013-08-09 11:22:18 -040037#define CONFIG_PALMAS_POWER
Tom Rinia8017572013-08-09 11:22:18 -040038
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000039#include <asm/arch/cpu.h>
40#include <asm/arch/omap.h>
41
Nishanth Menon9a0f4002015-07-22 18:05:41 -050042#include <configs/ti_armv7_omap.h>
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000043
44/*
45 * Hardware drivers
46 */
Thomas Chouc7b96862015-11-19 21:48:12 +080047#define CONFIG_SYS_NS16550_CLK 48000000
Tom Rini01e870b2015-09-17 16:47:04 -040048#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000049#define CONFIG_SYS_NS16550_SERIAL
50#define CONFIG_SYS_NS16550_REG_SIZE (-4)
Tom Rini01e870b2015-09-17 16:47:04 -040051#endif
Tom Rinidd2445e2013-04-05 06:21:46 +000052
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000053/*
54 * Environment setup
55 */
Tom Rini9552ee32013-04-05 06:21:45 +000056#ifndef PARTS_DEFAULT
57#define PARTS_DEFAULT
58#endif
59
Kishon Vijay Abraham I7a5a3e32015-02-23 18:40:20 +053060#ifndef DFUARGS
61#define DFUARGS
62#endif
63
Lokesh Vutla4ec3f6e2014-07-14 19:57:58 +053064#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000065#define CONFIG_EXTRA_ENV_SETTINGS \
Tom Rinifb3ad9b2014-03-28 15:03:29 -040066 DEFAULT_LINUX_BOOT_ENV \
Lokesh Vutla85d17be2015-08-28 13:35:07 +053067 DEFAULT_MMC_TI_ARGS \
Lokesh Vutla1e93cc82016-11-29 11:58:00 +053068 DEFAULT_FIT_TI_ARGS \
Tom Rinif6723792013-10-18 18:04:19 -040069 "console=" CONSOLEDEV ",115200n8\0" \
Dan Murphya7143212013-06-06 13:27:06 -050070 "fdtfile=undefined\0" \
SRICHARAN R143070d2013-04-04 23:39:27 +000071 "bootpart=0:2\0" \
72 "bootdir=/boot\0" \
SRICHARAN Raaed0a22013-04-04 23:39:47 +000073 "bootfile=zImage\0" \
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000074 "usbtty=cdc_acm\0" \
75 "vram=16M\0" \
Tom Rini9552ee32013-04-05 06:21:45 +000076 "partitions=" PARTS_DEFAULT "\0" \
Tom Rini85b7ac42013-04-11 05:22:10 +000077 "optargs=\0" \
Lokesh Vutla16862602015-08-13 20:26:38 +053078 "dofastboot=0\0" \
SRICHARAN R143070d2013-04-04 23:39:27 +000079 "findfdt="\
80 "if test $board_name = omap5_uevm; then " \
Dan Murphya7143212013-06-06 13:27:06 -050081 "setenv fdtfile omap5-uevm.dtb; fi; " \
Dan Murphy45dbbf22013-06-11 11:22:30 -050082 "if test $board_name = dra7xx; then " \
83 "setenv fdtfile dra7-evm.dtb; fi;" \
Lokesh Vutladf6b5062016-06-29 14:50:41 +053084 "if test $board_name = dra72x-revc; then " \
85 "setenv fdtfile dra72-evm-revc.dtb; fi;" \
Lokesh Vutla4ec3f6e2014-07-14 19:57:58 +053086 "if test $board_name = dra72x; then " \
87 "setenv fdtfile dra72-evm.dtb; fi;" \
Felipe Balbi1e4ad742014-11-10 14:02:44 -060088 "if test $board_name = beagle_x15; then " \
89 "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
Lokesh Vutlacc5cdaa2016-06-10 09:35:46 +053090 "if test $board_name = am572x_idk; then " \
91 "setenv fdtfile am572x-idk.dtb; fi;" \
Kipisz, Steven212f96f2016-02-24 12:30:58 -060092 "if test $board_name = am57xx_evm; then " \
93 "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \
Dan Murphya7143212013-06-06 13:27:06 -050094 "if test $fdtfile = undefined; then " \
95 "echo WARNING: Could not determine device tree to use; fi; \0" \
Kishon Vijay Abraham I7a5a3e32015-02-23 18:40:20 +053096 DFUARGS \
Cooper Jr., Franklin23208662015-04-21 07:51:04 -050097 NETARGS \
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +000098
99#define CONFIG_BOOTCOMMAND \
Dileep Kattaecd85572015-03-27 23:06:57 +0530100 "if test ${dofastboot} -eq 1; then " \
101 "echo Boot fastboot requested, resetting dofastboot ...;" \
102 "setenv dofastboot 0; saveenv;" \
Semen Protsenkoada03c32016-10-24 18:41:11 +0300103 "echo Booting into fastboot ...; " \
104 "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " \
Dileep Kattaecd85572015-03-27 23:06:57 +0530105 "fi;" \
Lokesh Vutla1e93cc82016-11-29 11:58:00 +0530106 "if test ${boot_fit} -eq 1; then " \
107 "run update_to_fit;" \
108 "fi;" \
SRICHARAN R143070d2013-04-04 23:39:27 +0000109 "run findfdt; " \
Lokesh Vutla18c534b2016-03-09 15:39:35 +0530110 "run envboot; " \
Tom Rini7406d322013-10-09 10:59:33 -0400111 "run mmcboot;" \
112 "setenv mmcdev 1; " \
113 "setenv bootpart 1:2; " \
114 "setenv mmcroot /dev/mmcblk0p2 rw; " \
115 "run mmcboot;" \
Dileep Kattaecd85572015-03-27 23:06:57 +0530116 ""
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000117
Tom Rini078aa4f2013-08-20 08:53:52 -0400118/*
119 * SPL related defines. The Public RAM memory map the ROM defines the
Daniel Allredb9b84032016-05-19 19:10:50 -0500120 * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
121 * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
122 * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
Tom Rini078aa4f2013-08-20 08:53:52 -0400123 * print some information.
124 */
Daniel Allredb9b84032016-05-19 19:10:50 -0500125#ifdef CONFIG_TI_SECURE_DEVICE
126/*
127 * For memory booting on HS parts, the first 4KB of the internal RAM is
128 * reserved for secure world use and the flash loader image is
129 * preceded by a secure certificate. The SPL will therefore run in internal
130 * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
131 */
132#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000
133#define CONFIG_SPL_TEXT_BASE 0x40301350
Daniel Allred32d333f2016-09-02 00:40:23 -0500134/* If no specific start address is specified then the secure EMIF
135 * region will be placed at the end of the DDR space. In order to prevent
136 * the main u-boot relocation from clobbering that memory and causing a
137 * firewall violation, we tell u-boot that memory is protected RAM (PRAM)
138 */
139#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0)
140#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10
141#endif
Daniel Allredb9b84032016-05-19 19:10:50 -0500142#else
143/*
144 * For all booting on GP parts, the flash loader image is
145 * downloaded into internal RAM at address 0x40300000.
146 */
147#define CONFIG_SPL_TEXT_BASE 0x40300000
148#endif
149
Tom Rini983e3702016-11-07 21:34:54 -0500150#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
Tom Rinid3289aa2014-04-03 07:52:53 -0400151#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
152 (128 << 20))
Lokesh Vutla3ef5ebe2013-02-17 23:34:35 +0000153
Enric Balletbò i Serra70e71b62013-12-06 21:30:20 +0100154#ifdef CONFIG_NAND
155#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
156#endif
157
Mugunthan V N136b1012015-09-29 14:42:26 +0530158/*
159 * Disable MMC DM for SPL build and can be re-enabled after adding
160 * DM support in SPL
161 */
162#ifdef CONFIG_SPL_BUILD
163#undef CONFIG_DM_MMC
Mugunthan V N30a0cdb2015-12-24 16:08:18 +0530164#undef CONFIG_TIMER
Mugunthan V N3d12e802016-04-28 15:36:03 +0530165#undef CONFIG_DM_ETH
Mugunthan V N136b1012015-09-29 14:42:26 +0530166#endif
167
Enric Balletbò i Serra3d657a02013-12-06 21:30:19 +0100168#endif /* __CONFIG_TI_OMAP5_COMMON_H */