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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1ee652ab2f356c8a775bc4878f32f26f29a4c941 / . / doc / board / ti / am62x_sk.rst
blob: 3a122b075641b4976ed91d3396d7abeff1791ddd [file] [log] [blame]
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]1.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2.. sectionauthor:: Vignesh Raghavendra <vigneshr@ti.com>
3
Bryan Brattlof0820e112022-12-19 14:29:49 -0600[diff] [blame]4AM62 Platforms
5===============
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]6
7Introduction:
8-------------
9The AM62 SoC family is the follow on AM335x built on the K3 Multicore
10SoC architecture platform, providing ultra-low-power modes, dual
11display, multi-sensor edge compute, security and other BOM-saving
12integrations. The AM62 SoC targets a broad market to enable
13applications such as Industrial HMI, PLC/CNC/Robot control, Medical
14Equipment, Building Automation, Appliances and more.
15
16Some highlights of this SoC are:
17
18* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
19 Pin-to-pin compatible options for single and quad core are available.
20* Cortex-M4F for general-purpose or safety usage.
21* Dual display support, providing 24-bit RBG parallel interface and
22 OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
23 resolution.
24* Selectable GPU support, up to 8GFLOPS, providing better user experience
25 in 3D graphic display case and Android.
26* PRU(Programmable Realtime Unit) support for customized programmable
27 interfaces/IOs.
28* Integrated Giga-bit Ethernet switch supporting up to a total of two
29 external ports (TSN capable).
30* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
31 NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
32 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
33* Dedicated Centralized System Controller for Security, Power, and
34 Resource Management.
35* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
36 enabling battery powered system design.
37
38More details can be found in the Technical Reference Manual:
39https://www.ti.com/lit/pdf/spruiv7
40
41Boot Flow:
42----------
43Below is the pictorial representation of boot flow:
44
45.. code-block:: text
46
47 +------------------------------------------------------------------------+
48 | TIFS | Main R5 | A53 |
49 +------------------------------------------------------------------------+
50 | +--------+ | | |
51 | | Reset | | | |
52 | +--------+ | | |
53 | : | | |
54 | +--------+ | +-----------+ | |
55 | | *ROM* |----------|-->| Reset rls | | |
56 | +--------+ | +-----------+ | |
57 | | | | : | |
58 | | ROM | | : | |
59 | |services| | : | |
60 | | | | +-------------+ | |
61 | | | | | *R5 ROM* | | |
62 | | | | +-------------+ | |
63 | | |<---------|---|Load and auth| | |
64 | | | | | tiboot3.bin | | |
65 | +--------+ | +-------------+ | |
66 | | |<---------|---| Load sysfw | | |
67 | | | | | part to TIFS| | |
68 | | | | | core | | |
69 | | | | +-------------+ | |
70 | | | | : | |
71 | | | | : | |
72 | | | | : | |
73 | | | | +-------------+ | |
74 | | | | | *R5 SPL* | | |
75 | | | | +-------------+ | |
76 | | | | | DDR | | |
77 | | | | | config | | |
78 | | | | +-------------+ | |
79 | | | | | Load | | |
80 | | | | | tispl.bin | | |
81 | | | | +-------------+ | |
82 | | | | | Load R5 | | |
83 | | | | | firmware | | |
84 | | | | +-------------+ | |
85 | | |<---------|---| Start A53 | | |
86 | | | | | and jump to | | |
87 | | | | | DM fw image | | |
88 | | | | +-------------+ | |
89 | | | | | +-----------+ |
90 | | |----------|-----------------------|---->| Reset rls | |
91 | | | | | +-----------+ |
92 | | TIFS | | | : |
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]93 | |Services| | | +-------------+ |
94 | | |<---------|-----------------------|---->|*TF-A/OP-TEE*| |
95 | | | | | +-------------+ |
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]96 | | | | | : |
97 | | | | | +-----------+ |
98 | | |<---------|-----------------------|---->| *A53 SPL* | |
99 | | | | | +-----------+ |
100 | | | | | | Load | |
101 | | | | | | u-boot.img| |
102 | | | | | +-----------+ |
103 | | | | | : |
104 | | | | | +-----------+ |
105 | | |<---------|-----------------------|---->| *U-Boot* | |
106 | | | | | +-----------+ |
107 | | | | | | prompt | |
108 | | |----------|-----------------------|-----+-----------+-----|
109 | +--------+ | | |
110 | | | |
111 +------------------------------------------------------------------------+
112
113- Here TIFS acts as master and provides all the critical services. R5/A53
114 requests TIFS to get these services done as shown in the above diagram.
115
116Sources:
117--------
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1181. Trusted Firmware-A:
119 Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]120 Branch: master
121
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1222. OP-TEE:
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]123 Tree: https://github.com/OP-TEE/optee_os.git
124 Branch: master
125
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1263. U-Boot:
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]127 Tree: https://source.denx.de/u-boot/u-boot
128 Branch: master
129
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1304. TI Linux Firmware:
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]131 Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
132 Branch: ti-linux-firmware
133
134Build procedure:
135----------------
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1361. Trusted Firmware-A:
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]137
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]138.. code-block:: bash
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]139
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]140 $ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 \
141 TARGET_BOARD=lite SPD=opteed
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]142
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1432. OP-TEE:
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]144
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]145.. code-block:: bash
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]146
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]147 $ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- \
148 CROSS_COMPILE64=aarch64-none-linux-gnu-
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]149
1503. U-Boot:
151
152* 3.1 R5:
153
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]154.. code-block:: bash
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]155
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]156 $ make ARCH=arm am62x_evm_r5_defconfig
157 $ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- \
158 BINMAN_INDIRS=<path/to/ti-linux-firmware>
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]159
160* 3.2 A53:
161
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]162.. code-block:: bash
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]163
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]164 $ make ARCH=arm am62x_evm_a53_defconfig
165 $ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- \
166 BL31=<path/to/trusted-firmware-a/dir>/build/k3/lite/release/bl31.bin \
167 TEE=<path/to/optee_os/dir>/out/arm-plat-k3/core/tee-raw.bin \
168 BINMAN_INDIRS=<path/to/ti-linux-firmware>
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]169
170Target Images
171--------------
172Copy the below images to an SD card and boot:
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]173
174 - GP
175
176 * tiboot3-am62x-gp-evm.bin from step 3.1
177 * tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
178
179 - HS-FS
180
181 * tiboot3-am62x-hs-fs-evm.bin from step 3.1
182 * tispl.bin, u-boot.img from step 3.2
183
184 - HS-SE
185
186 * tiboot3-am62x-hs-evm.bin from step 3.1
187 * tispl.bin, u-boot.img from step 3.2
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]188
189Image formats:
190--------------
191
192- tiboot3.bin:
193
194.. code-block:: text
195
196 +-----------------------+
197 | X.509 |
198 | Certificate |
199 | +-------------------+ |
200 | | | |
201 | | R5 | |
202 | | u-boot-spl.bin | |
203 | | | |
204 | +-------------------+ |
205 | | | |
206 | |TIFS with board cfg| |
207 | | | |
208 | +-------------------+ |
209 | | | |
210 | | | |
211 | | FIT header | |
212 | | +---------------+ | |
213 | | | | | |
214 | | | DTB 1...N | | |
215 | | +---------------+ | |
216 | +-------------------+ |
217 +-----------------------+
218
219- tispl.bin
220
221.. code-block:: text
222
223 +-----------------------+
224 | |
225 | FIT HEADER |
226 | +-------------------+ |
227 | | | |
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]228 | | A53 TF-A | |
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]229 | +-------------------+ |
230 | | | |
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]231 | | A53 OP-TEE | |
Vignesh Raghavendrae16aac32022-05-25 13:38:50 +0530[diff] [blame]232 | +-------------------+ |
233 | | | |
234 | | R5 DM FW | |
235 | +-------------------+ |
236 | | | |
237 | | A53 SPL | |
238 | +-------------------+ |
239 | | | |
240 | | SPL DTB 1...N | |
241 | +-------------------+ |
242 +-----------------------+
Judith Mendez354c05f2023-03-31 15:36:15 -0500[diff] [blame]243
Nikhil M Jaina72532f2023-07-18 14:27:35 +0530[diff] [blame]244A53 SPL DDR Memory Layout
245-------------------------
246
247This provides an overview memory usage in A53 SPL stage.
248
249.. list-table::
250 :widths: 16 16 16
251 :header-rows: 1
252
253 * - Region
254 - Start Address
255 - End Address
256
257 * - EMPTY
258 - 0x80000000
259 - 0x80080000
260
261 * - TEXT BASE
262 - 0x80080000
263 - 0x800d8000
264
265 * - EMPTY
266 - 0x800d8000
267 - 0x80200000
268
269 * - BMP IMAGE
270 - 0x80200000
271 - 0x80b77660
272
273 * - STACK
274 - 0x80b77660
275 - 0x80b77e60
276
277 * - GD
278 - 0x80b77e60
279 - 0x80b78000
280
281 * - MALLOC
282 - 0x80b78000
283 - 0x80b80000
284
285 * - EMPTY
286 - 0x80b80000
287 - 0x80c80000
288
289 * - BSS
290 - 0x80c80000
291 - 0x80d00000
292
293 * - BLOBS
294 - 0x80d00000
295 - 0x80d00400
296
297 * - EMPTY
298 - 0x80d00400
299 - 0x81000000
300
Judith Mendez354c05f2023-03-31 15:36:15 -0500[diff] [blame]301Switch Setting for Boot Mode
302----------------------------
303
304Boot Mode pins provide means to select the boot mode and options before the
305device is powered up. After every POR, they are the main source to populate
306the Boot Parameter Tables.
307
308The following table shows some common boot modes used on AM62 platform. More
309details can be found in the Technical Reference Manual:
310https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section.
311
312*Boot Modes*
313
314============ ============= =============
315Switch Label SW2: 12345678 SW3: 12345678
316============ ============= =============
317SD 01000000 11000010
318OSPI 00000000 11001110
319EMMC 00000000 11010010
320UART 00000000 11011100
321USB DFU 00000000 11001010
322============ ============= =============
323
324For SW2 and SW1, the switch state in the "ON" position = 1.