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Tom Rix23b80982009-09-27 11:10:09 -05001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Tom Rix23b80982009-09-27 11:10:09 -05004 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * (C) Copyright 2009
8 * Eric Benard <eric@eukrea.com>
9 *
10 * Configuration settings for the Eukrea CPU9260 board.
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Tom Rix23b80982009-09-27 11:10:09 -050013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
Eric Benardc2b2a072011-04-03 06:35:54 +000018/* to be removed once maemory-map.h is fixed */
19#define AT91_BASE_SYS 0xffffe800
20#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
Tom Rix23b80982009-09-27 11:10:09 -050021
Achim Ehrlich7c966a82010-02-24 10:29:16 +010022#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Eric Benard95d50e52011-06-06 22:48:28 +000023#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Tom Rix23b80982009-09-27 11:10:09 -050024
25#if defined(CONFIG_CPU9G20)
Eric Benardc2b2a072011-04-03 06:35:54 +000026#define CONFIG_AT91SAM9G20
Tom Rix23b80982009-09-27 11:10:09 -050027#elif defined(CONFIG_CPU9260)
Eric Benardc2b2a072011-04-03 06:35:54 +000028#define CONFIG_AT91SAM9260
Tom Rix23b80982009-09-27 11:10:09 -050029#else
30#error "Unknown board"
31#endif
32
Eric Benard95d50e52011-06-06 22:48:28 +000033#include <asm/arch/hardware.h>
34
Eric Benardc2b2a072011-04-03 06:35:54 +000035#define CONFIG_AT91FAMILY
Tom Rix23b80982009-09-27 11:10:09 -050036#define CONFIG_ARCH_CPU_INIT
Eric Benardc2b2a072011-04-03 06:35:54 +000037#define CONFIG_DISPLAY_CPUINFO
38#define CONFIG_BOARD_EARLY_INIT_F
Tom Rix23b80982009-09-27 11:10:09 -050039
Eric Benardc2b2a072011-04-03 06:35:54 +000040#define CONFIG_CMDLINE_TAG
41#define CONFIG_SETUP_MEMORY_TAGS
42#define CONFIG_INITRD_TAG
43
44#if defined(CONFIG_NANDBOOT)
45#define CONFIG_SKIP_LOWLEVEL_INIT
46#define CONFIG_SYS_TEXT_BASE 0x23f00000
47#else
48#define CONFIG_SYS_TEXT_BASE 0x00000000
49#endif
Tom Rix23b80982009-09-27 11:10:09 -050050
51/* clocks */
52#if defined(CONFIG_CPU9G20)
53#define MASTER_PLL_DIV 0x01
54#define MASTER_PLL_MUL 0x2B
55#elif defined(CONFIG_CPU9260)
56#define MASTER_PLL_DIV 0x09
57#define MASTER_PLL_MUL 0x61
58#endif
59
60/* CKGR_MOR - enable main osc. */
61#define CONFIG_SYS_MOR_VAL \
62 (AT91_PMC_MOSCEN | \
63 (255 << 8)) /* Main Oscillator Start-up Time */
64#if defined(CONFIG_CPU9G20)
65#define CONFIG_SYS_PLLAR_VAL \
66 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
67 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
68#elif defined(CONFIG_CPU9260)
69#define CONFIG_SYS_PLLAR_VAL \
70 (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
71 AT91_PMC_OUT | \
72 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
73#endif
74
75#if defined(CONFIG_CPU9G20)
76#define CONFIG_SYS_MCKR1_VAL \
77 (AT91_PMC_CSS_PLLA | \
78 AT91_PMC_PRES_1 | \
79 AT91SAM9_PMC_MDIV_6 | \
80 AT91_PMC_PDIV_2)
81#define CONFIG_SYS_MCKR2_VAL \
82 CONFIG_SYS_MCKR1_VAL
83#elif defined(CONFIG_CPU9260)
84#define CONFIG_SYS_MCKR1_VAL \
85 (AT91_PMC_CSS_SLOW | \
86 AT91_PMC_PRES_1 | \
87 AT91SAM9_PMC_MDIV_2 | \
88 AT91_PMC_PDIV_1)
89#define CONFIG_SYS_MCKR2_VAL \
90 (AT91_PMC_CSS_PLLA | \
91 AT91_PMC_PRES_1 | \
92 AT91SAM9_PMC_MDIV_2 | \
93 AT91_PMC_PDIV_1)
94#endif
95
96/* define PDC[31:16] as DATA[31:16] */
97#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
98/* no pull-up for D[31:16] */
99#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
100
101/* EBI_CSA, 3.3V, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
102#define CONFIG_SYS_MATRIX_EBICSA_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000103 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A | \
104 AT91_MATRIX_CSA_EBI_CS3A | AT91_MATRIX_CSA_VDDIOMSEL_3_3V)
Tom Rix23b80982009-09-27 11:10:09 -0500105
106/* SDRAM */
107/* SDRAMC_MR Mode register */
108#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
109/* SDRAMC_TR - Refresh Timer register */
110#define CONFIG_SYS_SDRC_TR_VAL1 0x287
111/* SDRAMC_CR - Configuration register*/
112#if defined(CONFIG_CPU9G20)
113#define CONFIG_SYS_SDRC_CR_VAL_64MB \
114 (AT91_SDRAMC_NC_9 | \
115 AT91_SDRAMC_NR_13 | \
116 AT91_SDRAMC_NB_4 | \
117 AT91_SDRAMC_CAS_2 | \
118 AT91_SDRAMC_DBW_32 | \
119 (2 << 8) | /* Write Recovery Delay */ \
120 (9 << 12) | /* Row Cycle Delay */ \
121 (3 << 16) | /* Row Precharge Delay */ \
122 (3 << 20) | /* Row to Column Delay */ \
123 (6 << 24) | /* Active to Precharge Delay */ \
124 (10 << 28)) /* Exit Self Refresh to Active Delay */
125
126#define CONFIG_SYS_SDRC_CR_VAL_128MB \
127 (AT91_SDRAMC_NC_10 | \
128 AT91_SDRAMC_NR_13 | \
129 AT91_SDRAMC_NB_4 | \
130 AT91_SDRAMC_CAS_2 | \
131 AT91_SDRAMC_DBW_32 | \
132 (2 << 8) | /* Write Recovery Delay */ \
133 (9 << 12) | /* Row Cycle Delay */ \
134 (3 << 16) | /* Row Precharge Delay */ \
135 (3 << 20) | /* Row to Column Delay */ \
136 (6 << 24) | /* Active to Precharge Delay */ \
137 (10 << 28)) /* Exit Self Refresh to Active Delay */
138#elif defined(CONFIG_CPU9260)
139#define CONFIG_SYS_SDRC_CR_VAL_64MB \
140 (AT91_SDRAMC_NC_9 | \
141 AT91_SDRAMC_NR_13 | \
142 AT91_SDRAMC_NB_4 | \
143 AT91_SDRAMC_CAS_2 | \
144 AT91_SDRAMC_DBW_32 | \
145 (2 << 8) | /* Write Recovery Delay */ \
146 (7 << 12) | /* Row Cycle Delay */ \
147 (2 << 16) | /* Row Precharge Delay */ \
148 (2 << 20) | /* Row to Column Delay */ \
149 (5 << 24) | /* Active to Precharge Delay */ \
150 (8 << 28)) /* Exit Self Refresh to Active Delay */
151
152#define CONFIG_SYS_SDRC_CR_VAL_128MB \
153 (AT91_SDRAMC_NC_10 | \
154 AT91_SDRAMC_NR_13 | \
155 AT91_SDRAMC_NB_4 | \
156 AT91_SDRAMC_CAS_2 | \
157 AT91_SDRAMC_DBW_32 | \
158 (2 << 8) | /* Write Recovery Delay */ \
159 (7 << 12) | /* Row Cycle Delay */ \
160 (2 << 16) | /* Row Precharge Delay */ \
161 (2 << 20) | /* Row to Column Delay */ \
162 (5 << 24) | /* Active to Precharge Delay */ \
163 (8 << 28)) /* Exit Self Refresh to Active Delay */
164#endif
165
166/* Memory Device Register -> SDRAM */
167#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
168#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
169#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
170#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
171#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
172#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
173#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
174#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
175#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
176#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
177#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
178#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
179#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
180#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
181#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
182#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
183#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
184#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
185
186/* setup SMC0, CS0 (NOR Flash) - 16-bit */
187#if defined(CONFIG_CPU9G20)
188#define CONFIG_SYS_SMC0_SETUP0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000189 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
190 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
Tom Rix23b80982009-09-27 11:10:09 -0500191#define CONFIG_SYS_SMC0_PULSE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000192 (AT91_SMC_PULSE_NWE(8) | AT91_SMC_PULSE_NCS_WR(8) | \
193 AT91_SMC_PULSE_NRD(14) | AT91_SMC_PULSE_NCS_RD(14))
Tom Rix23b80982009-09-27 11:10:09 -0500194#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000195 (AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(14))
Tom Rix23b80982009-09-27 11:10:09 -0500196#define CONFIG_SYS_SMC0_MODE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000197 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
198 AT91_SMC_MODE_DBW_16 | \
199 AT91_SMC_MODE_TDF | \
200 AT91_SMC_MODE_TDF_CYCLE(3))
Tom Rix23b80982009-09-27 11:10:09 -0500201#elif defined(CONFIG_CPU9260)
202#define CONFIG_SYS_SMC0_SETUP0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000203 (AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | \
204 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0))
Tom Rix23b80982009-09-27 11:10:09 -0500205#define CONFIG_SYS_SMC0_PULSE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000206 (AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(6) | \
207 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(10))
Tom Rix23b80982009-09-27 11:10:09 -0500208#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000209 (AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(10))
Tom Rix23b80982009-09-27 11:10:09 -0500210#define CONFIG_SYS_SMC0_MODE0_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000211 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
212 AT91_SMC_MODE_DBW_16 | \
213 AT91_SMC_MODE_TDF | \
214 AT91_SMC_MODE_TDF_CYCLE(2))
Tom Rix23b80982009-09-27 11:10:09 -0500215#endif
216
217/* user reset enable */
218#define CONFIG_SYS_RSTC_RMR_VAL \
219 (AT91_RSTC_KEY | \
Eric Benardc2b2a072011-04-03 06:35:54 +0000220 AT91_RSTC_CR_PROCRST | \
221 AT91_RSTC_MR_ERSTL(1) | \
222 AT91_RSTC_MR_ERSTL(2))
Tom Rix23b80982009-09-27 11:10:09 -0500223
224/* Disable Watchdog */
225#define CONFIG_SYS_WDTC_WDMR_VAL \
Eric Benardc2b2a072011-04-03 06:35:54 +0000226 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
227 AT91_WDT_MR_WDV(0xfff) | \
228 AT91_WDT_MR_WDDIS | \
229 AT91_WDT_MR_WDD(0xfff))
Tom Rix23b80982009-09-27 11:10:09 -0500230
231/*
232 * Hardware drivers
233 */
Eric Benardc2b2a072011-04-03 06:35:54 +0000234#define CONFIG_AT91SAM9_WATCHDOG
235#define CONFIG_AT91_GPIO
236#define CONFIG_ATMEL_USART
Eric Benard95d50e52011-06-06 22:48:28 +0000237#define CONFIG_USART_BASE ATMEL_BASE_DBGU
238#define CONFIG_USART_ID ATMEL_ID_SYS
Tom Rix23b80982009-09-27 11:10:09 -0500239
240#define CONFIG_BOOTDELAY 3
241
242/*
243 * BOOTP options
244 */
Eric Benardc2b2a072011-04-03 06:35:54 +0000245#define CONFIG_BOOTP_BOOTFILESIZE
246#define CONFIG_BOOTP_BOOTPATH
247#define CONFIG_BOOTP_GATEWAY
248#define CONFIG_BOOTP_HOSTNAME
Tom Rix23b80982009-09-27 11:10:09 -0500249
250/*
251 * Command line configuration.
252 */
253#include <config_cmd_default.h>
254#undef CONFIG_CMD_BDI
255#undef CONFIG_CMD_IMI
256#undef CONFIG_CMD_FPGA
257#undef CONFIG_CMD_LOADS
258#undef CONFIG_CMD_IMLS
259
Eric Benardc2b2a072011-04-03 06:35:54 +0000260#define CONFIG_CMD_PING
261#define CONFIG_CMD_DHCP
262#define CONFIG_CMD_NAND
263#define CONFIG_CMD_USB
264#define CONFIG_CMD_FAT
265#define CONFIG_CMD_MII
Tom Rix23b80982009-09-27 11:10:09 -0500266
267/* SDRAM */
268#define CONFIG_NR_DRAM_BANKS 1
Eric Benardc2b2a072011-04-03 06:35:54 +0000269#define CONFIG_SYS_SDRAM_BASE 0x20000000
Tom Rix23b80982009-09-27 11:10:09 -0500270#if defined(CONFIG_CPU9260_128M) || defined(CONFIG_CPU9G20_128M)
Eric Benardc2b2a072011-04-03 06:35:54 +0000271#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500272#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_128MB
273#else
Eric Benardc2b2a072011-04-03 06:35:54 +0000274#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500275#define CONFIG_SYS_SDRC_CR_VAL CONFIG_SYS_SDRC_CR_VAL_64MB
276#endif
277
278/* NAND flash */
Eric Benardc2b2a072011-04-03 06:35:54 +0000279#define CONFIG_NAND_ATMEL
Tom Rix23b80982009-09-27 11:10:09 -0500280#define CONFIG_SYS_MAX_NAND_DEVICE 1
281#define CONFIG_SYS_NAND_BASE 0x40000000
282#define CONFIG_SYS_NAND_DBW_8 1
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100283#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PC(13)
284#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tom Rix23b80982009-09-27 11:10:09 -0500285#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
286#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Tom Rix23b80982009-09-27 11:10:09 -0500287
288/* NOR flash */
Eric Benardc2b2a072011-04-03 06:35:54 +0000289#if defined(CONFIG_NANDBOOT)
290#define CONFIG_SYS_NO_FLASH
291#else
292#define CONFIG_SYS_FLASH_CFI
293#define CONFIG_FLASH_CFI_DRIVER
Tom Rix23b80982009-09-27 11:10:09 -0500294#define PHYS_FLASH_1 0x10000000
295#define PHYS_FLASH_2 0x12000000
296#define CONFIG_SYS_FLASH_BANKS_LIST \
297 { PHYS_FLASH_1, PHYS_FLASH_2 }
298#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
299#define CONFIG_SYS_MAX_FLASH_SECT (255+4)
300#define CONFIG_SYS_MAX_FLASH_BANKS 2
301#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Eric Benardc2b2a072011-04-03 06:35:54 +0000302#define CONFIG_SYS_FLASH_EMPTY_INFO
303#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
304#define CONFIG_SYS_FLASH_PROTECTION
Tom Rix23b80982009-09-27 11:10:09 -0500305#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
Eric Benardc2b2a072011-04-03 06:35:54 +0000306#endif
Tom Rix23b80982009-09-27 11:10:09 -0500307
308/* Ethernet */
Eric Benardc2b2a072011-04-03 06:35:54 +0000309#define CONFIG_MACB
310#define CONFIG_RMII
Tom Rix23b80982009-09-27 11:10:09 -0500311#define CONFIG_NET_RETRY_COUNT 20
Eric Benardc2b2a072011-04-03 06:35:54 +0000312#define CONFIG_MACB_SEARCH_PHY
Heiko Schocher4535a242013-11-18 08:07:23 +0100313#define CONFIG_AT91_WANTS_COMMON_PHY
Tom Rix23b80982009-09-27 11:10:09 -0500314
315/* LEDS */
316/* Status LED */
Eric Benardc2b2a072011-04-03 06:35:54 +0000317#define CONFIG_STATUS_LED
318#define CONFIG_BOARD_SPECIFIC_LED
Tom Rix23b80982009-09-27 11:10:09 -0500319#define STATUS_LED_RED 0
320#define STATUS_LED_GREEN 1
321#define STATUS_LED_YELLOW 2
322#define STATUS_LED_BLUE 3
323/* Red */
324#define STATUS_LED_BIT STATUS_LED_RED
325#define STATUS_LED_STATE STATUS_LED_OFF
326#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
327/* Green */
328#define STATUS_LED_BIT1 STATUS_LED_GREEN
329#define STATUS_LED_STATE1 STATUS_LED_OFF
330#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
331/* Yellow */
332#define STATUS_LED_BIT2 STATUS_LED_YELLOW
333#define STATUS_LED_STATE2 STATUS_LED_OFF
334#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
335/* Blue */
336#define STATUS_LED_BIT3 STATUS_LED_BLUE
337#define STATUS_LED_STATE3 STATUS_LED_ON
338#define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 2)
339/* Optional value */
340#define STATUS_LED_BOOT STATUS_LED_BIT
341
Eric Benardc2b2a072011-04-03 06:35:54 +0000342#define CONFIG_RED_LED AT91_PIO_PORTC, 11
343#define CONFIG_GREEN_LED AT91_PIO_PORTC, 12
344#define CONFIG_YELLOW_LED AT91_PIO_PORTC, 7
345#define CONFIG_BLUE_LED AT91_PIO_PORTC, 9
Tom Rix23b80982009-09-27 11:10:09 -0500346
347/* USB */
Eric Benardc2b2a072011-04-03 06:35:54 +0000348#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800349#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Eric Benardc2b2a072011-04-03 06:35:54 +0000350#define CONFIG_USB_OHCI_NEW
351#define CONFIG_DOS_PARTITION
352#define CONFIG_SYS_USB_OHCI_CPU_INIT
Tom Rix23b80982009-09-27 11:10:09 -0500353#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
Eric Benardc2b2a072011-04-03 06:35:54 +0000354#if defined(CONFIG_CPU9G20)
355#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
356#elif defined(CONFIG_CPU9260)
Tom Rix23b80982009-09-27 11:10:09 -0500357#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
Eric Benardc2b2a072011-04-03 06:35:54 +0000358#endif
Tom Rix23b80982009-09-27 11:10:09 -0500359#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Eric Benardc2b2a072011-04-03 06:35:54 +0000360#define CONFIG_USB_STORAGE
Tom Rix23b80982009-09-27 11:10:09 -0500361
362#define CONFIG_SYS_LOAD_ADDR 0x21000000
Eric Benardc2b2a072011-04-03 06:35:54 +0000363#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
Tom Rix23b80982009-09-27 11:10:09 -0500364
Eric Benardc2b2a072011-04-03 06:35:54 +0000365#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
366#define CONFIG_SYS_MEMTEST_END \
367 (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - 512 * 1024)
Tom Rix23b80982009-09-27 11:10:09 -0500368
Eric Benardc2b2a072011-04-03 06:35:54 +0000369#if defined(CONFIG_NANDBOOT)
370#define CONFIG_SYS_USE_NANDFLASH
371#undef CONFIG_SYS_USE_FLASH
372#else
373#define CONFIG_SYS_USE_FLASH
Tom Rix23b80982009-09-27 11:10:09 -0500374#undef CONFIG_SYS_USE_NANDFLASH
Eric Benardc2b2a072011-04-03 06:35:54 +0000375#endif
376
377#if defined(CONFIG_CPU9G20)
378#define CONFIG_SYS_BASEDIR "cpu9G20"
379#elif defined(CONFIG_CPU9260)
380#define CONFIG_SYS_BASEDIR "cpu9260"
381#endif
Tom Rix23b80982009-09-27 11:10:09 -0500382
383#if defined(CONFIG_SYS_USE_FLASH)
Eric Benardc2b2a072011-04-03 06:35:54 +0000384#define CONFIG_ENV_IS_IN_FLASH
Tom Rix23b80982009-09-27 11:10:09 -0500385#define CONFIG_ENV_OFFSET 0x40000
386#define CONFIG_ENV_SECT_SIZE 0x20000
387#define CONFIG_ENV_SIZE 0x20000
Eric Benardc2b2a072011-04-03 06:35:54 +0000388#define CONFIG_ENV_OVERWRITE
Tom Rix23b80982009-09-27 11:10:09 -0500389
390#define CONFIG_BOOTCOMMAND "run flashboot"
391
Eric Benardc2b2a072011-04-03 06:35:54 +0000392#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand"
Tom Rix23b80982009-09-27 11:10:09 -0500393#define MTDPARTS_DEFAULT \
394 "mtdparts=physmap-flash.0:" \
395 "256k(u-boot)ro," \
396 "128k(u-boot-env)ro," \
397 "1792k(kernel)," \
398 "-(rootfs);" \
399 "atmel_nand:-(nand)"
400
401#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 "
402
Tom Rix23b80982009-09-27 11:10:09 -0500403#define CONFIG_EXTRA_ENV_SETTINGS \
404 "mtdids=" MTDIDS_DEFAULT "\0" \
405 "mtdparts=" MTDPARTS_DEFAULT "\0" \
406 "partition=nand0,0\0" \
407 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
Eric Benardc2b2a072011-04-03 06:35:54 +0000408 "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
Tom Rix23b80982009-09-27 11:10:09 -0500409 "run ramargs;bootm 22000000\0" \
410 "flashboot=run ramargs;bootm 0x10060000\0" \
411 "basedir=" CONFIG_SYS_BASEDIR "\0" \
412 "updtub=tftp 0x24000000 $(basedir)/u-boot.bin;protect " \
413 "off 0x10000000 0x1003ffff;erase 0x10000000 " \
414 "0x1003ffff;cp.b 0x24000000 0x10000000 " \
415 "$(filesize)\0" \
416 "updtui=tftp 0x24000000 $(basedir)/uImage;protect off" \
417 " 0x10060000 0x1021ffff;erase 0x10060000 " \
418 "0x1021ffff;cp.b 0x24000000 0x10060000 " \
419 "$(filesize)\0" \
420 "updtrfs=tftp 0x24000000 $(basedir)/rootfs.jffs2; " \
421 "protect off 0x10220000 0x13ffffff;erase " \
422 "0x10220000 0x13ffffff;cp.b 0x24000000 " \
423 "0x10220000 $(filesize)\0" \
424 ""
Eric Benardc2b2a072011-04-03 06:35:54 +0000425#elif defined(CONFIG_NANDBOOT)
426#define CONFIG_ENV_IS_IN_NAND
427#define CONFIG_ENV_OFFSET 0x60000
428#define CONFIG_ENV_OFFSET_REDUND 0x80000
429#define CONFIG_ENV_SECT_SIZE 0x20000
430#define CONFIG_ENV_SIZE 0x20000
431#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
432#define CONFIG_ENV_OVERWRITE
433
434#define CONFIG_BOOTCOMMAND "run flashboot"
435
436#define MTDIDS_DEFAULT "nand0=atmel_nand"
437#define MTDPARTS_DEFAULT \
438 "mtdparts=atmel_nand:" \
439 "128k(bootstrap)ro," \
440 "256k(u-boot)ro," \
441 "128k(u-boot-env)ro," \
442 "128k(u-boot-env2)ro," \
443 "2M(kernel)," \
444 "-(rootfs)"
445
446#define CONFIG_BOOTARGS "root=ubi0:eukrea-cpu9260-rootfs " \
447 "ubi.mtd=5 rootfstype=ubifs at91sam9_wdt.heartbeat=60"
448
449#define CONFIG_EXTRA_ENV_SETTINGS \
450 "mtdids=" MTDIDS_DEFAULT "\0" \
451 "mtdparts=" MTDPARTS_DEFAULT "\0" \
452 "partition=nand0,5\0" \
453 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
454 "ramboot=tftpboot 0x22000000 $(basedir)/uImage;" \
455 "run ramargs;bootm 22000000\0" \
456 "flashboot=run ramargs; nand read 0x22000000 0xA0000 " \
457 "0x200000; bootm 0x22000000\0" \
458 "basedir=" CONFIG_SYS_BASEDIR "\0" \
459 "u-boot=u-boot-eukrea-cpu9260.bin\0" \
460 "kernel=uImage-eukrea-cpu9260.bin\0" \
461 "rootfs=image-eukrea-cpu9260.ubi\0" \
462 "updtub=tftp ${loadaddr} $(basedir)/${u-boot}; " \
463 "nand erase 20000 40000; " \
464 "nand write ${loadaddr} 20000 40000\0" \
465 "updtui=tftp ${loadaddr} $(basedir)/${kernel}; " \
466 "nand erase a0000 200000; " \
467 "nand write ${loadaddr} a0000 200000\0" \
468 "updtrfs=tftp ${loadaddr} $(basedir)/${rootfs}; " \
469 "nand erase 2a0000 fd60000; " \
470 "nand write ${loadaddr} 2a0000 ${filesize}\0"
Tom Rix23b80982009-09-27 11:10:09 -0500471#endif
472
473#define CONFIG_BAUDRATE 115200
Tom Rix23b80982009-09-27 11:10:09 -0500474
475#if defined(CONFIG_CPU9G20)
476#define CONFIG_SYS_PROMPT "CPU9G20=> "
477#elif defined(CONFIG_CPU9260)
478#define CONFIG_SYS_PROMPT "CPU9260=> "
479#endif
480#define CONFIG_SYS_CBSIZE 256
481#define CONFIG_SYS_MAXARGS 16
482#define CONFIG_SYS_PBSIZE \
483 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Eric Benardc2b2a072011-04-03 06:35:54 +0000484#define CONFIG_SYS_LONGHELP
485#define CONFIG_CMDLINE_EDITING
486#define CONFIG_SILENT_CONSOLE
487#define CONFIG_NETCONSOLE
Tom Rix23b80982009-09-27 11:10:09 -0500488
489/*
490 * Size of malloc() pool
491 */
492#define CONFIG_SYS_MALLOC_LEN \
493 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Tom Rix23b80982009-09-27 11:10:09 -0500494
Eric Benardc2b2a072011-04-03 06:35:54 +0000495#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
496 GENERATED_GBL_DATA_SIZE)
497
Tom Rix23b80982009-09-27 11:10:09 -0500498#endif