blob: e955c756e8946609fb64f0b5aec4a3b63f0b17fc [file] [log] [blame]
Kumar Gala83d40df2008-01-16 01:13:58 -06001#ifndef _FSL_LAW_H_
2#define _FSL_LAW_H_
3
4#include <asm/io.h>
5
Kumar Gala83d40df2008-01-16 01:13:58 -06006#define SET_LAW_ENTRY(idx, a, sz, trgt) \
7 { .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
8
9enum law_size {
10 LAW_SIZE_4K = 0xb,
11 LAW_SIZE_8K,
12 LAW_SIZE_16K,
13 LAW_SIZE_32K,
14 LAW_SIZE_64K,
15 LAW_SIZE_128K,
16 LAW_SIZE_256K,
17 LAW_SIZE_512K,
18 LAW_SIZE_1M,
19 LAW_SIZE_2M,
20 LAW_SIZE_4M,
21 LAW_SIZE_8M,
22 LAW_SIZE_16M,
23 LAW_SIZE_32M,
24 LAW_SIZE_64M,
25 LAW_SIZE_128M,
26 LAW_SIZE_256M,
27 LAW_SIZE_512M,
28 LAW_SIZE_1G,
29 LAW_SIZE_2G,
30 LAW_SIZE_4G,
31 LAW_SIZE_8G,
32 LAW_SIZE_16G,
33 LAW_SIZE_32G,
34};
35
36enum law_trgt_if {
37 LAW_TRGT_IF_PCI = 0x00,
38 LAW_TRGT_IF_PCI_2 = 0x01,
39#ifndef CONFIG_MPC8641
40 LAW_TRGT_IF_PCIE_1 = 0x02,
41#endif
42#ifndef CONFIG_MPC8572
43 LAW_TRGT_IF_PCIE_3 = 0x03,
44#endif
45 LAW_TRGT_IF_LBC = 0x04,
46 LAW_TRGT_IF_CCSR = 0x08,
47 LAW_TRGT_IF_DDR_INTRLV = 0x0b,
48 LAW_TRGT_IF_RIO = 0x0c,
49 LAW_TRGT_IF_DDR = 0x0f,
50 LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
51};
52#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
53#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
54#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
55#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
56
57#ifdef CONFIG_MPC8641
58#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
59#endif
60
61#ifdef CONFIG_MPC8572
62#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
63#endif
64
65struct law_entry {
66 int index;
67 phys_addr_t addr;
68 enum law_size size;
69 enum law_trgt_if trgt_id;
70};
71
72extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
73extern void disable_law(u8 idx);
74extern void init_laws(void);
Becky Bruceddcebcb2008-01-23 16:31:05 -060075extern void print_laws(void);
Kumar Gala83d40df2008-01-16 01:13:58 -060076
77/* define in board code */
78extern struct law_entry law_table[];
79extern int num_law_entries;
80#endif