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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR2403f8f2010-01-15 19:15:44 +05302/*
3 * (C) Copyright 2009
4 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
Vipin KUMAR2403f8f2010-01-15 19:15:44 +05305 */
6
7#include <common.h>
Simon Glassafb88652020-01-23 11:48:06 -07008#include <clk.h>
Stefan Roese334b9b02016-04-21 08:19:41 +02009#include <dm.h>
Stefan Roese678398b2014-10-28 12:12:00 +010010#include <i2c.h>
Stefan Roeseba5da552016-04-21 08:19:42 +020011#include <pci.h>
Dinh Nguyen622597d2018-04-04 17:18:24 -050012#include <reset.h>
Vipin KUMAR2403f8f2010-01-15 19:15:44 +053013#include <asm/io.h>
Vipin KUMAR031ed2f2012-02-26 23:13:29 +000014#include "designware_i2c.h"
Vipin KUMAR2403f8f2010-01-15 19:15:44 +053015
Stefan Roeseb6a77b02016-04-27 09:02:12 +020016#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
Simon Glass2b5d0292019-02-16 20:24:39 -070017static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
Stefan Roeseb6a77b02016-04-27 09:02:12 +020018{
19 u32 ena = enable ? IC_ENABLE_0B : 0;
20
21 writel(ena, &i2c_base->ic_enable);
Simon Glass2b5d0292019-02-16 20:24:39 -070022
23 return 0;
Stefan Roeseb6a77b02016-04-27 09:02:12 +020024}
25#else
Simon Glass2b5d0292019-02-16 20:24:39 -070026static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
Stefan Roese1c8b0892016-04-21 08:19:38 +020027{
28 u32 ena = enable ? IC_ENABLE_0B : 0;
29 int timeout = 100;
30
31 do {
32 writel(ena, &i2c_base->ic_enable);
33 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
Simon Glass2b5d0292019-02-16 20:24:39 -070034 return 0;
Stefan Roese1c8b0892016-04-21 08:19:38 +020035
36 /*
37 * Wait 10 times the signaling period of the highest I2C
38 * transfer supported by the driver (for 400KHz this is
39 * 25us) as described in the DesignWare I2C databook.
40 */
41 udelay(25);
42 } while (timeout--);
Stefan Roese1c8b0892016-04-21 08:19:38 +020043 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
Simon Glass2b5d0292019-02-16 20:24:39 -070044
45 return -ETIMEDOUT;
Stefan Roese1c8b0892016-04-21 08:19:38 +020046}
Stefan Roeseb6a77b02016-04-27 09:02:12 +020047#endif
Stefan Roese1c8b0892016-04-21 08:19:38 +020048
Simon Glasse71b6f62020-01-23 11:48:14 -070049/* High and low times in different speed modes (in ns) */
50enum {
51 /* SDA Hold Time */
52 DEFAULT_SDA_HOLD_TIME = 300,
53};
54
55/**
56 * calc_counts() - Convert a period to a number of IC clk cycles
57 *
58 * @ic_clk: Input clock in Hz
59 * @period_ns: Period to represent, in ns
60 * @return calculated count
61 */
62static uint calc_counts(uint ic_clk, uint period_ns)
63{
64 return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
65}
66
67/**
68 * struct i2c_mode_info - Information about an I2C speed mode
69 *
70 * Each speed mode has its own characteristics. This struct holds these to aid
71 * calculations in dw_i2c_calc_timing().
72 *
73 * @speed: Speed in Hz
74 * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
75 * @min_scl_hightime_ns: Minimum value for SCL high period in ns
76 * @def_rise_time_ns: Default rise time in ns
77 * @def_fall_time_ns: Default fall time in ns
78 */
79struct i2c_mode_info {
80 int speed;
81 int min_scl_hightime_ns;
82 int min_scl_lowtime_ns;
83 int def_rise_time_ns;
84 int def_fall_time_ns;
85};
86
87static const struct i2c_mode_info info_for_mode[] = {
88 [IC_SPEED_MODE_STANDARD] = {
Simon Glass54290c62020-01-23 11:48:18 -070089 I2C_SPEED_STANDARD_RATE,
Simon Glasse71b6f62020-01-23 11:48:14 -070090 MIN_SS_SCL_HIGHTIME,
91 MIN_SS_SCL_LOWTIME,
92 1000,
93 300,
94 },
95 [IC_SPEED_MODE_FAST] = {
Simon Glass54290c62020-01-23 11:48:18 -070096 I2C_SPEED_FAST_RATE,
Simon Glasse71b6f62020-01-23 11:48:14 -070097 MIN_FS_SCL_HIGHTIME,
98 MIN_FS_SCL_LOWTIME,
99 300,
100 300,
101 },
Simon Glassd96440d2020-01-23 11:48:23 -0700102 [IC_SPEED_MODE_FAST_PLUS] = {
103 I2C_SPEED_FAST_PLUS_RATE,
104 MIN_FP_SCL_HIGHTIME,
105 MIN_FP_SCL_LOWTIME,
106 260,
107 500,
108 },
Simon Glasse71b6f62020-01-23 11:48:14 -0700109 [IC_SPEED_MODE_HIGH] = {
Simon Glass54290c62020-01-23 11:48:18 -0700110 I2C_SPEED_HIGH_RATE,
Simon Glasse71b6f62020-01-23 11:48:14 -0700111 MIN_HS_SCL_HIGHTIME,
112 MIN_HS_SCL_LOWTIME,
113 120,
114 120,
115 },
116};
117
118/**
119 * dw_i2c_calc_timing() - Calculate the timings to use for a bus
120 *
121 * @priv: Bus private information (NULL if not using driver model)
122 * @mode: Speed mode to use
123 * @ic_clk: IC clock speed in Hz
124 * @spk_cnt: Spike-suppression count
125 * @config: Returns value to use
126 * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
127 */
128static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
129 int ic_clk, int spk_cnt,
130 struct dw_i2c_speed_config *config)
131{
132 int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
133 int hcnt, lcnt, period_cnt, diff, tot;
134 int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
135 const struct i2c_mode_info *info;
136
137 /*
138 * Find the period, rise, fall, min tlow, and min thigh in terms of
139 * counts of the IC clock
140 */
141 info = &info_for_mode[mode];
142 period_cnt = ic_clk / info->speed;
143 scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
144 priv->scl_rise_time_ns : info->def_rise_time_ns;
145 scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
146 priv->scl_fall_time_ns : info->def_fall_time_ns;
147 rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
148 fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
149 min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
150 min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
151
152 debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
153 period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
154 spk_cnt);
155
156 /*
157 * Back-solve for hcnt and lcnt according to the following equations:
158 * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
159 * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
160 */
161 hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
162 lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
163
164 if (hcnt < 0 || lcnt < 0) {
165 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
166 return -EINVAL;
167 }
168
169 /*
170 * Now add things back up to ensure the period is hit. If it is off,
171 * split the difference and bias to lcnt for remainder
172 */
173 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
174
175 if (tot < period_cnt) {
176 diff = (period_cnt - tot) / 2;
177 hcnt += diff;
178 lcnt += diff;
179 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
180 lcnt += period_cnt - tot;
181 }
182
183 config->scl_lcnt = lcnt;
184 config->scl_hcnt = hcnt;
185
186 /* Use internal default unless other value is specified */
187 sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
188 priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
189 config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
190
191 debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
192 config->sda_hold);
193
194 return 0;
195}
196
Simon Glass23ad52e2020-01-23 11:48:25 -0700197static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
198 struct dw_i2c_speed_config *config)
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530199{
Simon Glassd22409e2020-01-23 11:48:12 -0700200 const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
Simon Glass23ad52e2020-01-23 11:48:25 -0700201 struct i2c_regs *regs = priv->regs;
Simon Glass65190d12020-01-23 11:48:08 -0700202 enum i2c_speed_mode i2c_spd;
Simon Glass96fe11c2020-01-23 11:48:15 -0700203 int spk_cnt;
Simon Glasse71b6f62020-01-23 11:48:14 -0700204 int ret;
Stefan Roese11b544a2016-04-21 08:19:39 +0200205
Simon Glassd22409e2020-01-23 11:48:12 -0700206 if (priv)
207 scl_sda_cfg = priv->scl_sda_cfg;
Simon Glass6db79432020-01-23 11:48:07 -0700208 /* Allow high speed if there is no config, or the config allows it */
Simon Glass54290c62020-01-23 11:48:18 -0700209 if (speed >= I2C_SPEED_HIGH_RATE &&
Simon Glass6db79432020-01-23 11:48:07 -0700210 (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
211 i2c_spd = IC_SPEED_MODE_HIGH;
Simon Glass54290c62020-01-23 11:48:18 -0700212 else if (speed >= I2C_SPEED_FAST_RATE)
Simon Glassd96440d2020-01-23 11:48:23 -0700213 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
214 else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
Stefan Roese11b544a2016-04-21 08:19:39 +0200215 i2c_spd = IC_SPEED_MODE_FAST;
216 else
217 i2c_spd = IC_SPEED_MODE_STANDARD;
Armando Visconti5e3e8dd2012-03-29 20:10:17 +0000218
Simon Glass23ad52e2020-01-23 11:48:25 -0700219 /* Get the proper spike-suppression count based on target speed */
220 if (!priv || !priv->has_spk_cnt)
221 spk_cnt = 0;
222 else if (i2c_spd >= IC_SPEED_MODE_HIGH)
223 spk_cnt = readl(&regs->hs_spklen);
224 else
225 spk_cnt = readl(&regs->fs_spklen);
226 if (scl_sda_cfg) {
227 config->sda_hold = scl_sda_cfg->sda_hold;
228 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
229 config->scl_hcnt = scl_sda_cfg->ss_hcnt;
230 config->scl_lcnt = scl_sda_cfg->ss_lcnt;
231 } else {
232 config->scl_hcnt = scl_sda_cfg->fs_hcnt;
233 config->scl_lcnt = scl_sda_cfg->fs_lcnt;
234 }
235 } else {
236 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
237 config);
238 if (ret)
239 return log_msg_ret("gen_confg", ret);
240 }
241 config->speed_mode = i2c_spd;
242
243 return 0;
244}
245
246/*
247 * _dw_i2c_set_bus_speed - Set the i2c speed
248 * @speed: required i2c speed
249 *
250 * Set the i2c speed.
251 */
252static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
253 unsigned int speed, unsigned int bus_clk)
254{
255 struct dw_i2c_speed_config config;
256 unsigned int cntl;
257 unsigned int ena;
258 int ret;
259
260 ret = calc_bus_speed(priv, speed, bus_clk, &config);
261 if (ret)
262 return ret;
263
Jun Chene3b93dc2019-06-05 15:23:16 +0800264 /* Get enable setting for restore later */
265 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
266
Armando Visconti5e3e8dd2012-03-29 20:10:17 +0000267 /* to set speed cltr must be disabled */
Stefan Roese1c8b0892016-04-21 08:19:38 +0200268 dw_i2c_enable(i2c_base, false);
Armando Visconti5e3e8dd2012-03-29 20:10:17 +0000269
Stefan Roese678398b2014-10-28 12:12:00 +0100270 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530271
Simon Glass23ad52e2020-01-23 11:48:25 -0700272 switch (config.speed_mode) {
Simon Glass6db79432020-01-23 11:48:07 -0700273 case IC_SPEED_MODE_HIGH:
Stefan Roeseba5da552016-04-21 08:19:42 +0200274 cntl |= IC_CON_SPD_SS;
Simon Glass31adb872020-01-23 11:48:13 -0700275 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
276 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530277 break;
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530278 case IC_SPEED_MODE_STANDARD:
279 cntl |= IC_CON_SPD_SS;
Simon Glass31adb872020-01-23 11:48:13 -0700280 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
281 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530282 break;
Simon Glassd96440d2020-01-23 11:48:23 -0700283 case IC_SPEED_MODE_FAST_PLUS:
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530284 case IC_SPEED_MODE_FAST:
285 default:
286 cntl |= IC_CON_SPD_FS;
Simon Glass31adb872020-01-23 11:48:13 -0700287 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
288 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530289 break;
290 }
291
Stefan Roese678398b2014-10-28 12:12:00 +0100292 writel(cntl, &i2c_base->ic_con);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530293
Stefan Roeseba5da552016-04-21 08:19:42 +0200294 /* Configure SDA Hold Time if required */
Simon Glass31adb872020-01-23 11:48:13 -0700295 if (config.sda_hold)
296 writel(config.sda_hold, &i2c_base->ic_sda_hold);
Stefan Roeseba5da552016-04-21 08:19:42 +0200297
Jun Chene3b93dc2019-06-05 15:23:16 +0800298 /* Restore back i2c now speed set */
299 if (ena == IC_ENABLE_0B)
300 dw_i2c_enable(i2c_base, true);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530301
Stefan Roese3f4358d2016-04-21 08:19:40 +0200302 return 0;
303}
304
305/*
306 * i2c_setaddress - Sets the target slave address
307 * @i2c_addr: target i2c address
308 *
309 * Sets the target slave address.
310 */
311static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
312{
313 /* Disable i2c */
314 dw_i2c_enable(i2c_base, false);
315
316 writel(i2c_addr, &i2c_base->ic_tar);
317
318 /* Enable i2c */
319 dw_i2c_enable(i2c_base, true);
320}
321
322/*
323 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
324 *
325 * Flushes the i2c RX FIFO
326 */
327static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
328{
329 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
330 readl(&i2c_base->ic_cmd_data);
331}
332
333/*
334 * i2c_wait_for_bb - Waits for bus busy
335 *
336 * Waits for bus busy
337 */
338static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
339{
340 unsigned long start_time_bb = get_timer(0);
341
342 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
343 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
344
345 /* Evaluate timeout */
346 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
347 return 1;
348 }
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530349
350 return 0;
351}
352
Stefan Roese3f4358d2016-04-21 08:19:40 +0200353static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
354 int alen)
355{
356 if (i2c_wait_for_bb(i2c_base))
357 return 1;
358
359 i2c_setaddress(i2c_base, chip);
360 while (alen) {
361 alen--;
362 /* high byte address going out first */
363 writel((addr >> (alen * 8)) & 0xff,
364 &i2c_base->ic_cmd_data);
365 }
366 return 0;
367}
368
369static int i2c_xfer_finish(struct i2c_regs *i2c_base)
370{
371 ulong start_stop_det = get_timer(0);
372
373 while (1) {
374 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
375 readl(&i2c_base->ic_clr_stop_det);
376 break;
377 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
378 break;
379 }
380 }
381
382 if (i2c_wait_for_bb(i2c_base)) {
383 printf("Timed out waiting for bus\n");
384 return 1;
385 }
386
387 i2c_flush_rxfifo(i2c_base);
388
389 return 0;
390}
391
392/*
393 * i2c_read - Read from i2c memory
394 * @chip: target i2c address
395 * @addr: address to read from
396 * @alen:
397 * @buffer: buffer for read data
398 * @len: no of bytes to be read
399 *
400 * Read from i2c memory.
401 */
402static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
403 int alen, u8 *buffer, int len)
404{
405 unsigned long start_time_rx;
Marek Vasutb0338082016-10-20 16:48:28 +0200406 unsigned int active = 0;
Stefan Roese3f4358d2016-04-21 08:19:40 +0200407
408#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
409 /*
410 * EEPROM chips that implement "address overflow" are ones
411 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
412 * address and the extra bits end up in the "chip address"
413 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
414 * four 256 byte chips.
415 *
416 * Note that we consider the length of the address field to
417 * still be one byte because the extra address bits are
418 * hidden in the chip address.
419 */
420 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
421 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
422
423 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
424 addr);
425#endif
426
427 if (i2c_xfer_init(i2c_base, dev, addr, alen))
428 return 1;
429
430 start_time_rx = get_timer(0);
431 while (len) {
Marek Vasutb0338082016-10-20 16:48:28 +0200432 if (!active) {
433 /*
434 * Avoid writing to ic_cmd_data multiple times
435 * in case this loop spins too quickly and the
436 * ic_status RFNE bit isn't set after the first
437 * write. Subsequent writes to ic_cmd_data can
438 * trigger spurious i2c transfer.
439 */
440 if (len == 1)
441 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
442 else
443 writel(IC_CMD, &i2c_base->ic_cmd_data);
444 active = 1;
445 }
Stefan Roese3f4358d2016-04-21 08:19:40 +0200446
447 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
448 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
449 len--;
450 start_time_rx = get_timer(0);
Marek Vasutb0338082016-10-20 16:48:28 +0200451 active = 0;
Stefan Roese3f4358d2016-04-21 08:19:40 +0200452 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
Marek Vasutb0338082016-10-20 16:48:28 +0200453 return 1;
Stefan Roese3f4358d2016-04-21 08:19:40 +0200454 }
455 }
456
457 return i2c_xfer_finish(i2c_base);
458}
459
460/*
461 * i2c_write - Write to i2c memory
462 * @chip: target i2c address
463 * @addr: address to read from
464 * @alen:
465 * @buffer: buffer for read data
466 * @len: no of bytes to be read
467 *
468 * Write to i2c memory.
469 */
470static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
471 int alen, u8 *buffer, int len)
472{
473 int nb = len;
474 unsigned long start_time_tx;
475
476#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
477 /*
478 * EEPROM chips that implement "address overflow" are ones
479 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
480 * address and the extra bits end up in the "chip address"
481 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
482 * four 256 byte chips.
483 *
484 * Note that we consider the length of the address field to
485 * still be one byte because the extra address bits are
486 * hidden in the chip address.
487 */
488 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
489 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
490
491 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
492 addr);
493#endif
494
495 if (i2c_xfer_init(i2c_base, dev, addr, alen))
496 return 1;
497
498 start_time_tx = get_timer(0);
499 while (len) {
500 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
501 if (--len == 0) {
502 writel(*buffer | IC_STOP,
503 &i2c_base->ic_cmd_data);
504 } else {
505 writel(*buffer, &i2c_base->ic_cmd_data);
506 }
507 buffer++;
508 start_time_tx = get_timer(0);
509
510 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
511 printf("Timed out. i2c write Failed\n");
512 return 1;
513 }
514 }
515
516 return i2c_xfer_finish(i2c_base);
517}
518
Stefan Roese334b9b02016-04-21 08:19:41 +0200519/*
520 * __dw_i2c_init - Init function
521 * @speed: required i2c speed
522 * @slaveaddr: slave address for the device
523 *
524 * Initialization function.
525 */
Simon Glass2b5d0292019-02-16 20:24:39 -0700526static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
Stefan Roese334b9b02016-04-21 08:19:41 +0200527{
Simon Glass2b5d0292019-02-16 20:24:39 -0700528 int ret;
529
Stefan Roese334b9b02016-04-21 08:19:41 +0200530 /* Disable i2c */
Simon Glass2b5d0292019-02-16 20:24:39 -0700531 ret = dw_i2c_enable(i2c_base, false);
532 if (ret)
533 return ret;
Stefan Roese334b9b02016-04-21 08:19:41 +0200534
Marek Vasut014e47f2017-08-07 20:45:31 +0200535 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
536 &i2c_base->ic_con);
Stefan Roese334b9b02016-04-21 08:19:41 +0200537 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
538 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
539 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
540#ifndef CONFIG_DM_I2C
Simon Glass23ad52e2020-01-23 11:48:25 -0700541 _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
Stefan Roese334b9b02016-04-21 08:19:41 +0200542 writel(slaveaddr, &i2c_base->ic_sar);
543#endif
544
545 /* Enable i2c */
Simon Glass2b5d0292019-02-16 20:24:39 -0700546 ret = dw_i2c_enable(i2c_base, true);
547 if (ret)
548 return ret;
549
550 return 0;
Stefan Roese334b9b02016-04-21 08:19:41 +0200551}
552
553#ifndef CONFIG_DM_I2C
554/*
555 * The legacy I2C functions. These need to get removed once
556 * all users of this driver are converted to DM.
557 */
Stefan Roese3f4358d2016-04-21 08:19:40 +0200558static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
559{
560 switch (adap->hwadapnr) {
561#if CONFIG_SYS_I2C_BUS_MAX >= 4
562 case 3:
563 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
564#endif
565#if CONFIG_SYS_I2C_BUS_MAX >= 3
566 case 2:
567 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
568#endif
569#if CONFIG_SYS_I2C_BUS_MAX >= 2
570 case 1:
571 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
572#endif
573 case 0:
574 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
575 default:
576 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
577 }
578
579 return NULL;
580}
581
582static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
583 unsigned int speed)
584{
585 adap->speed = speed;
Simon Glass23ad52e2020-01-23 11:48:25 -0700586 return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
Stefan Roese3f4358d2016-04-21 08:19:40 +0200587}
588
Stefan Roese334b9b02016-04-21 08:19:41 +0200589static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530590{
Stefan Roese334b9b02016-04-21 08:19:41 +0200591 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530592}
593
Stefan Roese678398b2014-10-28 12:12:00 +0100594static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
595 int alen, u8 *buffer, int len)
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530596{
Stefan Roese3f4358d2016-04-21 08:19:40 +0200597 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530598}
599
Stefan Roese678398b2014-10-28 12:12:00 +0100600static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
601 int alen, u8 *buffer, int len)
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530602{
Stefan Roese3f4358d2016-04-21 08:19:40 +0200603 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530604}
605
Stefan Roese334b9b02016-04-21 08:19:41 +0200606/* dw_i2c_probe - Probe the i2c chip */
Stefan Roese678398b2014-10-28 12:12:00 +0100607static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530608{
Stefan Roese3f4358d2016-04-21 08:19:40 +0200609 struct i2c_regs *i2c_base = i2c_get_base(adap);
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530610 u32 tmp;
Stefan Roese496ba482012-01-20 11:52:33 +0100611 int ret;
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530612
613 /*
614 * Try to read the first location of the chip.
615 */
Stefan Roese3f4358d2016-04-21 08:19:40 +0200616 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
Stefan Roese496ba482012-01-20 11:52:33 +0100617 if (ret)
Stefan Roese678398b2014-10-28 12:12:00 +0100618 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
Stefan Roese496ba482012-01-20 11:52:33 +0100619
620 return ret;
Vipin KUMAR2403f8f2010-01-15 19:15:44 +0530621}
Armando Viscontiac6e2fe2012-12-06 00:04:15 +0000622
Stefan Roese678398b2014-10-28 12:12:00 +0100623U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
624 dw_i2c_write, dw_i2c_set_bus_speed,
625 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
Armando Viscontiac6e2fe2012-12-06 00:04:15 +0000626
Stefan Roese678398b2014-10-28 12:12:00 +0100627#if CONFIG_SYS_I2C_BUS_MAX >= 2
628U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
629 dw_i2c_write, dw_i2c_set_bus_speed,
630 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
631#endif
Armando Viscontiac6e2fe2012-12-06 00:04:15 +0000632
Stefan Roese678398b2014-10-28 12:12:00 +0100633#if CONFIG_SYS_I2C_BUS_MAX >= 3
634U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
635 dw_i2c_write, dw_i2c_set_bus_speed,
636 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
637#endif
Armando Viscontiac6e2fe2012-12-06 00:04:15 +0000638
Stefan Roese678398b2014-10-28 12:12:00 +0100639#if CONFIG_SYS_I2C_BUS_MAX >= 4
640U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
641 dw_i2c_write, dw_i2c_set_bus_speed,
642 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
Armando Viscontiac6e2fe2012-12-06 00:04:15 +0000643#endif
Stefan Roese334b9b02016-04-21 08:19:41 +0200644
645#else /* CONFIG_DM_I2C */
646/* The DM I2C functions */
647
648static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
649 int nmsgs)
650{
651 struct dw_i2c *i2c = dev_get_priv(bus);
652 int ret;
653
654 debug("i2c_xfer: %d messages\n", nmsgs);
655 for (; nmsgs > 0; nmsgs--, msg++) {
656 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
657 if (msg->flags & I2C_M_RD) {
658 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
659 msg->buf, msg->len);
660 } else {
661 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
662 msg->buf, msg->len);
663 }
664 if (ret) {
665 debug("i2c_write: error sending\n");
666 return -EREMOTEIO;
667 }
668 }
669
670 return 0;
671}
672
673static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
674{
675 struct dw_i2c *i2c = dev_get_priv(bus);
Ley Foon Tan2d1e8792019-06-12 09:48:04 +0800676 ulong rate;
Stefan Roese334b9b02016-04-21 08:19:41 +0200677
Ley Foon Tan2d1e8792019-06-12 09:48:04 +0800678#if CONFIG_IS_ENABLED(CLK)
679 rate = clk_get_rate(&i2c->clk);
680 if (IS_ERR_VALUE(rate))
681 return -EINVAL;
Ley Foon Tan2d1e8792019-06-12 09:48:04 +0800682#else
683 rate = IC_CLK;
684#endif
Simon Glass23ad52e2020-01-23 11:48:25 -0700685 return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
Stefan Roese334b9b02016-04-21 08:19:41 +0200686}
687
688static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
689 uint chip_flags)
690{
691 struct dw_i2c *i2c = dev_get_priv(bus);
692 struct i2c_regs *i2c_base = i2c->regs;
693 u32 tmp;
694 int ret;
695
696 /* Try to read the first location of the chip */
697 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
698 if (ret)
699 __dw_i2c_init(i2c_base, 0, 0);
700
701 return ret;
702}
703
Simon Glass80a03db2020-01-23 11:48:11 -0700704int designware_i2c_ofdata_to_platdata(struct udevice *bus)
Simon Glass457df232019-12-06 21:41:40 -0700705{
706 struct dw_i2c *priv = dev_get_priv(bus);
Simon Glass2034f6c2020-01-23 11:48:26 -0700707 int ret;
Simon Glass457df232019-12-06 21:41:40 -0700708
Simon Glass80a03db2020-01-23 11:48:11 -0700709 if (!priv->regs)
710 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
711 dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
712 dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
713 dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
Simon Glass457df232019-12-06 21:41:40 -0700714
Simon Goldschmidt36821b32019-03-28 21:11:48 +0100715 ret = reset_get_bulk(bus, &priv->resets);
Dinh Nguyen622597d2018-04-04 17:18:24 -0500716 if (ret)
Simon Goldschmidt36821b32019-03-28 21:11:48 +0100717 dev_warn(bus, "Can't get reset: %d\n", ret);
718 else
719 reset_deassert_bulk(&priv->resets);
Dinh Nguyen622597d2018-04-04 17:18:24 -0500720
Ley Foon Tan2d1e8792019-06-12 09:48:04 +0800721#if CONFIG_IS_ENABLED(CLK)
722 ret = clk_get_by_index(bus, 0, &priv->clk);
723 if (ret)
724 return ret;
725
726 ret = clk_enable(&priv->clk);
727 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
728 clk_free(&priv->clk);
729 dev_err(bus, "failed to enable clock\n");
730 return ret;
731 }
732#endif
733
Simon Glass2034f6c2020-01-23 11:48:26 -0700734 return 0;
735}
736
737int designware_i2c_probe(struct udevice *bus)
738{
739 struct dw_i2c *priv = dev_get_priv(bus);
740
Simon Glass2b5d0292019-02-16 20:24:39 -0700741 return __dw_i2c_init(priv->regs, 0, 0);
Stefan Roese334b9b02016-04-21 08:19:41 +0200742}
743
Simon Glass457df232019-12-06 21:41:40 -0700744int designware_i2c_remove(struct udevice *dev)
Simon Goldschmidt36821b32019-03-28 21:11:48 +0100745{
746 struct dw_i2c *priv = dev_get_priv(dev);
747
Ley Foon Tan2d1e8792019-06-12 09:48:04 +0800748#if CONFIG_IS_ENABLED(CLK)
749 clk_disable(&priv->clk);
750 clk_free(&priv->clk);
751#endif
752
Simon Goldschmidt36821b32019-03-28 21:11:48 +0100753 return reset_release_bulk(&priv->resets);
754}
755
Simon Glass457df232019-12-06 21:41:40 -0700756const struct dm_i2c_ops designware_i2c_ops = {
Stefan Roese334b9b02016-04-21 08:19:41 +0200757 .xfer = designware_i2c_xfer,
758 .probe_chip = designware_i2c_probe_chip,
759 .set_bus_speed = designware_i2c_set_bus_speed,
760};
761
762static const struct udevice_id designware_i2c_ids[] = {
763 { .compatible = "snps,designware-i2c" },
764 { }
765};
766
767U_BOOT_DRIVER(i2c_designware) = {
768 .name = "i2c_designware",
769 .id = UCLASS_I2C,
770 .of_match = designware_i2c_ids,
Simon Glass457df232019-12-06 21:41:40 -0700771 .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
Stefan Roese334b9b02016-04-21 08:19:41 +0200772 .probe = designware_i2c_probe,
773 .priv_auto_alloc_size = sizeof(struct dw_i2c),
Simon Goldschmidt36821b32019-03-28 21:11:48 +0100774 .remove = designware_i2c_remove,
Simon Glass457df232019-12-06 21:41:40 -0700775 .flags = DM_FLAG_OS_PREPARE,
Stefan Roese334b9b02016-04-21 08:19:41 +0200776 .ops = &designware_i2c_ops,
777};
778
779#endif /* CONFIG_DM_I2C */