blob: 8a076ddc924d7348a1c9062df658eb88c0151a01 [file] [log] [blame]
Mike Frysinger9171fc82008-03-30 15:46:13 -04001/*
2 * serial.h - common serial defines for early debug and serial driver.
3 * any functions defined here must be always_inline since
4 * initcode cannot have function calls.
5 *
6 * Copyright (c) 2004-2007 Analog Devices Inc.
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#ifndef __BFIN_CPU_SERIAL_H__
12#define __BFIN_CPU_SERIAL_H__
13
14#include <asm/blackfin.h>
15#include <asm/mach-common/bits/uart.h>
16
Mike Frysinger76339032008-10-11 21:52:17 -040017#ifndef CONFIG_UART_CONSOLE
18# define CONFIG_UART_CONSOLE 0
19#endif
20
Mike Frysinger9171fc82008-03-30 15:46:13 -040021#ifdef CONFIG_DEBUG_EARLY_SERIAL
22# define BFIN_DEBUG_EARLY_SERIAL 1
23#else
24# define BFIN_DEBUG_EARLY_SERIAL 0
25#endif
26
Mike Frysingerf9481582009-11-12 18:42:53 -050027#ifndef __ASSEMBLY__
28
Mike Frysingera409fdd2010-06-02 06:00:27 -040029#include <asm/portmux.h>
30
Mike Frysinger9171fc82008-03-30 15:46:13 -040031#define LOB(x) ((x) & 0xFF)
32#define HIB(x) (((x) >> 8) & 0xFF)
33
Mike Frysingercca07412010-12-17 15:25:09 -050034#if defined(__ADSPBF50x__) || defined(__ADSPBF54x__)
35# define BFIN_UART_HW_VER 2
36#else
37# define BFIN_UART_HW_VER 1
38#endif
39
Mike Frysingerf9481582009-11-12 18:42:53 -050040/*
41 * All Blackfin system MMRs are padded to 32bits even if the register
42 * itself is only 16bits. So use a helper macro to streamline this.
43 */
44#define __BFP(m) u16 m; u16 __pad_##m
45struct bfin_mmr_serial {
Mike Frysingercca07412010-12-17 15:25:09 -050046#if BFIN_UART_HW_VER == 2
Mike Frysingerf9481582009-11-12 18:42:53 -050047 __BFP(dll);
48 __BFP(dlh);
49 __BFP(gctl);
50 __BFP(lcr);
51 __BFP(mcr);
52 __BFP(lsr);
53 __BFP(msr);
54 __BFP(scr);
55 __BFP(ier_set);
56 __BFP(ier_clear);
57 __BFP(thr);
58 __BFP(rbr);
59#else
60 union {
61 u16 dll;
62 u16 thr;
63 const u16 rbr;
64 };
65 const u16 __spad0;
66 union {
67 u16 dlh;
68 u16 ier;
69 };
70 const u16 __spad1;
71 const __BFP(iir);
72 __BFP(lcr);
73 __BFP(mcr);
74 __BFP(lsr);
75 __BFP(msr);
76 __BFP(scr);
77 const u32 __spad2;
78 __BFP(gctl);
79#endif
80};
81#undef __BFP
82
Mike Frysingerbaaa4f92010-12-17 16:23:59 -050083#define __PASTE_UART(num, pfx, sfx) pfx##num##_##sfx
84#define _PASTE_UART(num, pfx, sfx) __PASTE_UART(num, pfx, sfx)
Mike Frysinger635f3302011-04-29 23:23:28 -040085#define MMR_UART(n) _PASTE_UART(n, UART, DLL)
86#define _P_UART(n, pin) _PASTE_UART(n, P_UART, pin)
87#define P_UART(pin) _P_UART(CONFIG_UART_CONSOLE, pin)
Mike Frysingerbaaa4f92010-12-17 16:23:59 -050088
89#ifndef UART_DLL
Mike Frysinger635f3302011-04-29 23:23:28 -040090# define UART_DLL MMR_UART(CONFIG_UART_CONSOLE)
Mike Frysingerf9481582009-11-12 18:42:53 -050091#else
Mike Frysinger635f3302011-04-29 23:23:28 -040092# define UART0_DLL UART_DLL
Mike Frysingerf9481582009-11-12 18:42:53 -050093# if CONFIG_UART_CONSOLE != 0
94# error CONFIG_UART_CONSOLE must be 0 on parts with only one UART
95# endif
Mike Frysinger9171fc82008-03-30 15:46:13 -040096#endif
Mike Frysinger635f3302011-04-29 23:23:28 -040097#define pUART ((volatile struct bfin_mmr_serial *)uart_base)
Mike Frysinger9171fc82008-03-30 15:46:13 -040098
Mike Frysingercca07412010-12-17 15:25:09 -050099#if BFIN_UART_HW_VER == 2
Mike Frysinger9171fc82008-03-30 15:46:13 -0400100# define ACCESS_LATCH()
101# define ACCESS_PORT_IER()
Mike Frysinger9171fc82008-03-30 15:46:13 -0400102#else
Mike Frysingerf9481582009-11-12 18:42:53 -0500103# define ACCESS_LATCH() \
Mike Frysingerb1e574d2011-06-06 16:47:31 -0400104 bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) | DLAB)
Mike Frysingerf9481582009-11-12 18:42:53 -0500105# define ACCESS_PORT_IER() \
Mike Frysingerb1e574d2011-06-06 16:47:31 -0400106 bfin_write(&pUART->lcr, bfin_read(&pUART->lcr) & ~DLAB)
Mike Frysinger9171fc82008-03-30 15:46:13 -0400107#endif
108
109__attribute__((always_inline))
110static inline void serial_do_portmux(void)
111{
Mike Frysingera409fdd2010-06-02 06:00:27 -0400112 if (!BFIN_DEBUG_EARLY_SERIAL) {
Mike Frysingerbaaa4f92010-12-17 16:23:59 -0500113 const unsigned short pins[] = { P_UART(RX), P_UART(TX), 0, };
Mike Frysingera409fdd2010-06-02 06:00:27 -0400114 peripheral_request_list(pins, "bfin-uart");
115 return;
116 }
117
Mike Frysingercca07412010-12-17 15:25:09 -0500118#if defined(__ADSPBF50x__)
119# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
120 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_1 | PORT_x_MUX_##mux_rx##_FUNC_1); \
121 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
122 switch (CONFIG_UART_CONSOLE) {
123 case 0: DO_MUX(G, 7, 7, 12, 13); break; /* Port G; mux 7; PG12 and PG13 */
124 case 1: DO_MUX(F, 3, 3, 6, 7); break; /* Port F; mux 3; PF6 and PF7 */
125 }
126 SSYNC();
127#elif defined(__ADSPBF51x__)
Mike Frysinger51230e62008-10-11 21:15:53 -0400128# define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
129 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \
130 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
131 switch (CONFIG_UART_CONSOLE) {
132 case 0: DO_MUX(G, 5, 5, 9, 10); break; /* Port G; mux 5; PG9 and PG10 */
133 case 1: DO_MUX(F, 2, 3, 14, 15); break; /* Port H; mux 2/3; PH14 and PH15 */
134 }
135 SSYNC();
136#elif defined(__ADSPBF52x__)
Mike Frysinger9171fc82008-03-30 15:46:13 -0400137# define DO_MUX(port, mux, tx, rx) \
138 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_3); \
139 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
140 switch (CONFIG_UART_CONSOLE) {
141 case 0: DO_MUX(G, 2, 7, 8); break; /* Port G; mux 2; PG2 and PG8 */
142 case 1: DO_MUX(F, 5, 14, 15); break; /* Port F; mux 5; PF14 and PF15 */
143 }
144 SSYNC();
145#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
Mike Frysingerbaaa4f92010-12-17 16:23:59 -0500146 const uint16_t func[] = { PFDE, PFTE, };
147 bfin_write_PORT_MUX(bfin_read_PORT_MUX() & ~func[CONFIG_UART_CONSOLE]);
148 bfin_write_PORTF_FER(bfin_read_PORTF_FER() |
149 (1 << P_IDENT(P_UART(RX))) |
150 (1 << P_IDENT(P_UART(TX))));
Mike Frysinger9171fc82008-03-30 15:46:13 -0400151 SSYNC();
152#elif defined(__ADSPBF54x__)
153# define DO_MUX(port, tx, rx) \
154 bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##tx##_MASK | PORT_x_MUX_##rx##_MASK)) | PORT_x_MUX_##tx##_FUNC_1 | PORT_x_MUX_##rx##_FUNC_1); \
155 bfin_write_PORT##port##_FER(bfin_read_PORT##port##_FER() | P##port##tx | P##port##rx);
156 switch (CONFIG_UART_CONSOLE) {
157 case 0: DO_MUX(E, 7, 8); break; /* Port E; PE7 and PE8 */
158 case 1: DO_MUX(H, 0, 1); break; /* Port H; PH0 and PH1 */
159 case 2: DO_MUX(B, 4, 5); break; /* Port B; PB4 and PB5 */
160 case 3: DO_MUX(B, 6, 7); break; /* Port B; PB6 and PB7 */
161 }
162 SSYNC();
Mike Frysingerbaaa4f92010-12-17 16:23:59 -0500163#elif defined(__ADSPBF561__)
164 /* UART pins could be GPIO, but they aren't pin muxed. */
165#else
166# if (P_UART(RX) & P_DEFINED) || (P_UART(TX) & P_DEFINED)
167# error "missing portmux logic for UART"
168# endif
Mike Frysinger9171fc82008-03-30 15:46:13 -0400169#endif
170}
171
172__attribute__((always_inline))
Mike Frysinger635f3302011-04-29 23:23:28 -0400173static inline int uart_init(uint32_t uart_base)
Mike Frysinger9171fc82008-03-30 15:46:13 -0400174{
Mike Frysingeraad4eca2009-04-04 09:10:27 -0400175 /* always enable UART -- avoids anomalies 05000309 and 05000350 */
Mike Frysingerb1e574d2011-06-06 16:47:31 -0400176 bfin_write(&pUART->gctl, UCEN);
Mike Frysinger9171fc82008-03-30 15:46:13 -0400177
178 /* Set LCR to Word Lengh 8-bit word select */
Mike Frysingerb1e574d2011-06-06 16:47:31 -0400179 bfin_write(&pUART->lcr, WLS_8);
Mike Frysinger9171fc82008-03-30 15:46:13 -0400180
181 SSYNC();
Mike Frysinger635f3302011-04-29 23:23:28 -0400182
183 return 0;
Mike Frysinger9171fc82008-03-30 15:46:13 -0400184}
185
186__attribute__((always_inline))
Mike Frysinger635f3302011-04-29 23:23:28 -0400187static inline int serial_early_init(uint32_t uart_base)
188{
189 /* handle portmux crap on different Blackfins */
190 serial_do_portmux();
191
192 return uart_init(uart_base);
193}
194
195__attribute__((always_inline))
196static inline int serial_early_uninit(uint32_t uart_base)
197{
198 /* disable the UART by clearing UCEN */
Mike Frysingerb1e574d2011-06-06 16:47:31 -0400199 bfin_write(&pUART->gctl, 0);
Mike Frysinger635f3302011-04-29 23:23:28 -0400200
201 return 0;
202}
203
204__attribute__((always_inline))
205static inline void serial_early_put_div(uint32_t uart_base, uint16_t divisor)
Mike Frysinger9171fc82008-03-30 15:46:13 -0400206{
Mike Frysinger9171fc82008-03-30 15:46:13 -0400207 /* Set DLAB in LCR to Access DLL and DLH */
208 ACCESS_LATCH();
209 SSYNC();
210
211 /* Program the divisor to get the baud rate we want */
Mike Frysingerb1e574d2011-06-06 16:47:31 -0400212 bfin_write(&pUART->dll, LOB(divisor));
213 bfin_write(&pUART->dlh, HIB(divisor));
Mike Frysinger9171fc82008-03-30 15:46:13 -0400214 SSYNC();
215
216 /* Clear DLAB in LCR to Access THR RBR IER */
217 ACCESS_PORT_IER();
218 SSYNC();
219}
220
Mike Frysingerf790ef62008-12-10 12:33:54 -0500221__attribute__((always_inline))
222static inline uint16_t serial_early_get_div(void)
223{
Mike Frysinger635f3302011-04-29 23:23:28 -0400224 uint32_t uart_base = UART_DLL;
225
Mike Frysingerf790ef62008-12-10 12:33:54 -0500226 /* Set DLAB in LCR to Access DLL and DLH */
227 ACCESS_LATCH();
228 SSYNC();
229
Mike Frysingerb1e574d2011-06-06 16:47:31 -0400230 uint8_t dll = bfin_read(&pUART->dll);
231 uint8_t dlh = bfin_read(&pUART->dlh);
Mike Frysingerf790ef62008-12-10 12:33:54 -0500232 uint16_t divisor = (dlh << 8) | dll;
233
234 /* Clear DLAB in LCR to Access THR RBR IER */
235 ACCESS_PORT_IER();
236 SSYNC();
237
238 return divisor;
239}
240
Mike Frysingerf58bf802009-04-24 23:54:19 -0400241/* We cannot use get_sclk() early on as it uses caches in external memory */
242#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
243# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
244#endif
245
Mike Frysingerf790ef62008-12-10 12:33:54 -0500246__attribute__((always_inline))
Mike Frysinger635f3302011-04-29 23:23:28 -0400247static inline void serial_early_set_baud(uint32_t uart_base, uint32_t baud)
Mike Frysingerf790ef62008-12-10 12:33:54 -0500248{
249 /* Translate from baud into divisor in terms of SCLK. The
250 * weird multiplication is to make sure we over sample just
251 * a little rather than under sample the incoming signals.
252 */
Mike Frysinger635f3302011-04-29 23:23:28 -0400253 serial_early_put_div(uart_base,
254 (get_sclk() + (baud * 8)) / (baud * 16) - ANOMALY_05000230);
Mike Frysingerf790ef62008-12-10 12:33:54 -0500255}
256
Mike Frysinger9171fc82008-03-30 15:46:13 -0400257#ifndef BFIN_IN_INITCODE
258__attribute__((always_inline))
259static inline void serial_early_puts(const char *s)
260{
261 if (BFIN_DEBUG_EARLY_SERIAL) {
262 serial_puts("Early: ");
263 serial_puts(s);
264 }
265}
266#endif
267
268#else
269
270.macro serial_early_init
271#ifdef CONFIG_DEBUG_EARLY_SERIAL
272 call _serial_initialize;
273#endif
274.endm
275
276.macro serial_early_set_baud
277#ifdef CONFIG_DEBUG_EARLY_SERIAL
278 R0.L = LO(CONFIG_BAUDRATE);
279 R0.H = HI(CONFIG_BAUDRATE);
280 call _serial_set_baud;
281#endif
282.endm
283
Mike Frysinger9171fc82008-03-30 15:46:13 -0400284/* Since we embed the string right into our .text section, we need
285 * to find its address. We do this by getting our PC and adding 2
286 * bytes (which is the length of the jump instruction). Then we
287 * pass this address to serial_puts().
288 */
289#ifdef CONFIG_DEBUG_EARLY_SERIAL
290# define serial_early_puts(str) \
Mike Frysingere8e35ef2011-06-29 16:21:28 -0400291 .section .rodata; \
292 7: \
Mike Frysinger9171fc82008-03-30 15:46:13 -0400293 .ascii "Early:"; \
294 .ascii __FILE__; \
295 .ascii ": "; \
296 .ascii str; \
297 .asciz "\n"; \
Mike Frysingere8e35ef2011-06-29 16:21:28 -0400298 .previous; \
299 R0.L = 7b; \
300 R0.H = 7b; \
Mike Frysinger9171fc82008-03-30 15:46:13 -0400301 call _serial_puts;
302#else
303# define serial_early_puts(str)
304#endif
305
306#endif
307
308#endif