wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 1 | /* |
Bin Meng | fe0c33a | 2014-12-12 21:05:22 +0800 | [diff] [blame] | 2 | * U-Boot - x86 Startup Code |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 3 | * |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 4 | * (C) Copyright 2008-2011 |
| 5 | * Graeme Russ, <graeme.russ@gmail.com> |
| 6 | * |
| 7 | * (C) Copyright 2002 |
Albert ARIBAUD | fa82f87 | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 8 | * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 9 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 10 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 13 | #include <config.h> |
Graeme Russ | 161b358 | 2010-10-07 20:03:29 +1100 | [diff] [blame] | 14 | #include <asm/global_data.h> |
Simon Glass | d1cd045 | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 15 | #include <asm/post.h> |
Graeme Russ | 109ad14 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 16 | #include <asm/processor.h> |
Graeme Russ | 0c24c9c | 2011-02-12 15:11:32 +1100 | [diff] [blame] | 17 | #include <asm/processor-flags.h> |
Graeme Russ | 9e6c572 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 18 | #include <generated/generic-asm-offsets.h> |
Bin Meng | fe0c33a | 2014-12-12 21:05:22 +0800 | [diff] [blame] | 19 | #include <generated/asm-offsets.h> |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 20 | |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 21 | .section .text |
| 22 | .code32 |
| 23 | .globl _start |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 24 | .type _start, @function |
Graeme Russ | fea2572 | 2011-04-13 19:43:28 +1000 | [diff] [blame] | 25 | .globl _x86boot_start |
| 26 | _x86boot_start: |
Graeme Russ | 077e195 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 27 | /* |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 28 | * This is the fail-safe 32-bit bootstrap entry point. |
| 29 | * |
| 30 | * This code is used when booting from another boot loader like |
| 31 | * coreboot or EFI. So we repeat some of the same init found in |
| 32 | * start16. |
Graeme Russ | 077e195 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 33 | */ |
| 34 | cli |
| 35 | cld |
| 36 | |
Graeme Russ | 2f0e0cd | 2011-11-08 02:33:23 +0000 | [diff] [blame] | 37 | /* Turn off cache (this might require a 486-class CPU) */ |
Graeme Russ | 077e195 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 38 | movl %cr0, %eax |
Graeme Russ | 0c24c9c | 2011-02-12 15:11:32 +1100 | [diff] [blame] | 39 | orl $(X86_CR0_NW | X86_CR0_CD), %eax |
Graeme Russ | 077e195 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 40 | movl %eax, %cr0 |
| 41 | wbinvd |
| 42 | |
Gabe Black | 91d82a2 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 43 | /* Tell 32-bit code it is being entered from an in-RAM copy */ |
Simon Glass | 83ec7de | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 44 | movl $GD_FLG_WARM_BOOT, %ebx |
Simon Glass | 42fde305 | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 45 | |
| 46 | /* |
| 47 | * Zero the BIST (Built-In Self Test) value since we don't have it. |
| 48 | * It must be 0 or the previous loader would have reported an error. |
| 49 | */ |
| 50 | movl $0, %ebp |
| 51 | |
Gabe Black | 91d82a2 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 52 | jmp 1f |
Simon Glass | 83ec7de | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 53 | |
| 54 | /* Add a way for tools to discover the _start entry point */ |
| 55 | .align 4 |
| 56 | .long 0x12345678 |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 57 | _start: |
Gabe Black | 91d82a2 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 58 | /* |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 59 | * This is the 32-bit cold-reset entry point, coming from start16. |
Simon Glass | 83ec7de | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 60 | * Set %ebx to GD_FLG_COLD_BOOT to indicate this. |
Gabe Black | 91d82a2 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 61 | */ |
Simon Glass | 83ec7de | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 62 | movl $GD_FLG_COLD_BOOT, %ebx |
Simon Glass | 42fde305 | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 63 | |
Simon Glass | f67cd51 | 2014-11-06 13:20:10 -0700 | [diff] [blame] | 64 | /* Save BIST */ |
| 65 | movl %eax, %ebp |
Simon Glass | 42fde305 | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 66 | 1: |
| 67 | |
| 68 | /* Save table pointer */ |
| 69 | movl %ecx, %esi |
Graeme Russ | 077e195 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 70 | |
Andy Shevchenko | 446d4e0 | 2017-02-05 16:52:00 +0300 | [diff] [blame] | 71 | #ifdef CONFIG_X86_LOAD_FROM_32_BIT |
Simon Glass | e5aa8a9 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 72 | lgdt gdt_ptr2 |
| 73 | #endif |
| 74 | |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 75 | /* Load the segement registers to match the GDT loaded in start16.S */ |
Graeme Russ | 109ad14 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 76 | movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax |
Graeme Russ | 8ffb2e8 | 2010-10-07 20:03:21 +1100 | [diff] [blame] | 77 | movw %ax, %fs |
| 78 | movw %ax, %ds |
| 79 | movw %ax, %gs |
| 80 | movw %ax, %es |
| 81 | movw %ax, %ss |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 82 | |
Mike Williams | 1626308 | 2011-07-22 04:01:30 +0000 | [diff] [blame] | 83 | /* Clear the interrupt vectors */ |
Graeme Russ | 077e195 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 84 | lidt blank_idt_ptr |
| 85 | |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 86 | /* |
| 87 | * Critical early platform init - generally not used, we prefer init |
| 88 | * to happen later when we have a console, in case something goes |
| 89 | * wrong. |
| 90 | */ |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 91 | jmp early_board_init |
Graeme Russ | 88fa0a6 | 2010-10-07 20:03:27 +1100 | [diff] [blame] | 92 | .globl early_board_init_ret |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 93 | early_board_init_ret: |
Simon Glass | d1cd045 | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 94 | post_code(POST_START) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 95 | |
Graeme Russ | ed4cba7 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 96 | /* Initialise Cache-As-RAM */ |
| 97 | jmp car_init |
| 98 | .globl car_init_ret |
| 99 | car_init_ret: |
Bin Meng | bceb9f0 | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 100 | #ifndef CONFIG_HAVE_FSP |
Graeme Russ | ed4cba7 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 101 | /* |
| 102 | * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, |
| 103 | * or fully initialised SDRAM - we really don't care which) |
| 104 | * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 105 | * and early malloc() area. The MRC requires some space at the top. |
Simon Glass | 76f90f3 | 2014-11-06 13:20:04 -0700 | [diff] [blame] | 106 | * |
| 107 | * Stack grows down from top of CAR. We have: |
| 108 | * |
| 109 | * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE |
Simon Glass | 65dd74a | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 110 | * MRC area |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 111 | * global_data with x86 global descriptor table |
Simon Glass | 76f90f3 | 2014-11-06 13:20:04 -0700 | [diff] [blame] | 112 | * early malloc area |
| 113 | * stack |
| 114 | * bottom-> CONFIG_SYS_CAR_ADDR |
Graeme Russ | ed4cba7 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 115 | */ |
Simon Glass | 65dd74a | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 116 | movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp |
| 117 | #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE |
| 118 | subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp |
| 119 | #endif |
Bin Meng | bceb9f0 | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 120 | #else |
| 121 | /* |
Bin Meng | 48aa6c2 | 2015-08-20 06:40:20 -0700 | [diff] [blame] | 122 | * U-Boot enters here twice. For the first time it comes from |
| 123 | * car_init_done() with esp points to a temporary stack and esi |
| 124 | * set to zero. For the second time it comes from fsp_init_done() |
| 125 | * with esi holding the HOB list address returned by the FSP. |
Bin Meng | bceb9f0 | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 126 | */ |
| 127 | #endif |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 128 | /* Set up global data */ |
| 129 | mov %esp, %eax |
Albert ARIBAUD | ecc3066 | 2015-11-25 17:56:32 +0100 | [diff] [blame] | 130 | call board_init_f_alloc_reserve |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 131 | mov %eax, %esp |
Albert ARIBAUD | ecc3066 | 2015-11-25 17:56:32 +0100 | [diff] [blame] | 132 | call board_init_f_init_reserve |
Graeme Russ | 8d61625 | 2012-11-27 15:38:36 +0000 | [diff] [blame] | 133 | |
Simon Glass | 60994a0 | 2015-10-18 19:51:26 -0600 | [diff] [blame] | 134 | #ifdef CONFIG_DEBUG_UART |
| 135 | call debug_uart_init |
| 136 | #endif |
Simon Glass | bbbe55f | 2015-08-02 18:07:21 -0600 | [diff] [blame] | 137 | |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 138 | /* Get address of global_data */ |
| 139 | mov %fs:0, %edx |
Bin Meng | bceb9f0 | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 140 | #ifdef CONFIG_HAVE_FSP |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 141 | /* Store the HOB list if we have one */ |
Bin Meng | aefaff8 | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 142 | test %esi, %esi |
| 143 | jz skip_hob |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 144 | movl %esi, GD_HOB_LIST(%edx) |
Bin Meng | bceb9f0 | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 145 | |
Bin Meng | 57b10f5 | 2015-08-20 06:40:19 -0700 | [diff] [blame] | 146 | /* |
| 147 | * After fsp_init() returns, the stack has already been switched to a |
| 148 | * place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR. |
| 149 | * Enlarge the size of malloc() pool before relocation since we have |
| 150 | * plenty of memory now. |
| 151 | */ |
| 152 | subl $CONFIG_FSP_SYS_MALLOC_F_LEN, %esp |
| 153 | movl %esp, GD_MALLOC_BASE(%edx) |
Bin Meng | aefaff8 | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 154 | skip_hob: |
Simon Glass | 42fde305 | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 155 | #else |
| 156 | /* Store table pointer */ |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 157 | movl %esi, GD_TABLE(%edx) |
Bin Meng | aefaff8 | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 158 | #endif |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 159 | /* Store BIST */ |
| 160 | movl %ebp, GD_BIST(%edx) |
Graeme Russ | 9e6c572 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 161 | |
Graeme Russ | 96cd664 | 2011-02-12 15:11:54 +1100 | [diff] [blame] | 162 | /* Set parameter to board_init_f() to boot flags */ |
Simon Glass | d1cd045 | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 163 | post_code(POST_START_DONE) |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 164 | xorl %eax, %eax |
Graeme Russ | 161b358 | 2010-10-07 20:03:29 +1100 | [diff] [blame] | 165 | |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 166 | /* Enter, U-Boot! */ |
Graeme Russ | dbf7115 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 167 | call board_init_f |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 168 | |
| 169 | /* indicate (lack of) progress */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 170 | movw $0x85, %ax |
Graeme Russ | fb00290 | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 171 | jmp die |
| 172 | |
Graeme Russ | f48dd6f | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 173 | .globl board_init_f_r_trampoline |
| 174 | .type board_init_f_r_trampoline, @function |
| 175 | board_init_f_r_trampoline: |
Graeme Russ | fb00290 | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 176 | /* |
| 177 | * SDRAM has been initialised, U-Boot code has been copied into |
| 178 | * RAM, BSS has been cleared and relocation adjustments have been |
| 179 | * made. It is now time to jump into the in-RAM copy of U-Boot |
| 180 | * |
Graeme Russ | f48dd6f | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 181 | * %eax = Address of top of new stack |
Graeme Russ | fb00290 | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 182 | */ |
| 183 | |
Graeme Russ | 8d61625 | 2012-11-27 15:38:36 +0000 | [diff] [blame] | 184 | /* Stack grows down from top of SDRAM */ |
Graeme Russ | fb00290 | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 185 | movl %eax, %esp |
| 186 | |
Simon Glass | f0c7d9c | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 187 | /* See if we need to disable CAR */ |
Simon Glass | 801d70c | 2015-01-01 16:18:13 -0700 | [diff] [blame] | 188 | .weak car_uninit |
| 189 | movl $car_uninit, %eax |
| 190 | cmpl $0, %eax |
| 191 | jz 1f |
| 192 | |
| 193 | call car_uninit |
| 194 | 1: |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 195 | /* Re-enter U-Boot by calling board_init_f_r() */ |
Graeme Russ | f48dd6f | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 196 | call board_init_f_r |
Graeme Russ | fb00290 | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 197 | |
Graeme Russ | 2f0e0cd | 2011-11-08 02:33:23 +0000 | [diff] [blame] | 198 | die: |
| 199 | hlt |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 200 | jmp die |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 201 | hlt |
Graeme Russ | 077e195 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 202 | |
| 203 | blank_idt_ptr: |
| 204 | .word 0 /* limit */ |
| 205 | .long 0 /* base */ |
Graeme Russ | a206cc2 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 206 | |
| 207 | .p2align 2 /* force 4-byte alignment */ |
| 208 | |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 209 | /* Add a multiboot header so U-Boot can be loaded by GRUB2 */ |
Graeme Russ | a206cc2 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 210 | multiboot_header: |
| 211 | /* magic */ |
Simon Glass | da3a95d | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 212 | .long 0x1badb002 |
Graeme Russ | a206cc2 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 213 | /* flags */ |
| 214 | .long (1 << 16) |
| 215 | /* checksum */ |
| 216 | .long -0x1BADB002 - (1 << 16) |
| 217 | /* header addr */ |
| 218 | .long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE |
| 219 | /* load addr */ |
| 220 | .long CONFIG_SYS_TEXT_BASE |
| 221 | /* load end addr */ |
| 222 | .long 0 |
| 223 | /* bss end addr */ |
| 224 | .long 0 |
| 225 | /* entry addr */ |
| 226 | .long CONFIG_SYS_TEXT_BASE |
Simon Glass | e5aa8a9 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 227 | |
Andy Shevchenko | 446d4e0 | 2017-02-05 16:52:00 +0300 | [diff] [blame] | 228 | #ifdef CONFIG_X86_LOAD_FROM_32_BIT |
Simon Glass | e5aa8a9 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 229 | /* |
| 230 | * The following Global Descriptor Table is just enough to get us into |
| 231 | * 'Flat Protected Mode' - It will be discarded as soon as the final |
| 232 | * GDT is setup in a safe location in RAM |
| 233 | */ |
| 234 | gdt_ptr2: |
| 235 | .word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */ |
| 236 | .long gdt_rom2 /* base */ |
| 237 | |
| 238 | /* Some CPUs are picky about GDT alignment... */ |
| 239 | .align 16 |
| 240 | .globl gdt_rom2 |
| 241 | gdt_rom2: |
| 242 | /* |
| 243 | * The GDT table ... |
| 244 | * |
| 245 | * Selector Type |
| 246 | * 0x00 NULL |
| 247 | * 0x08 Unused |
| 248 | * 0x10 32bit code |
| 249 | * 0x18 32bit data/stack |
| 250 | */ |
| 251 | /* The NULL Desciptor - Mandatory */ |
| 252 | .word 0x0000 /* limit_low */ |
| 253 | .word 0x0000 /* base_low */ |
| 254 | .byte 0x00 /* base_middle */ |
| 255 | .byte 0x00 /* access */ |
| 256 | .byte 0x00 /* flags + limit_high */ |
| 257 | .byte 0x00 /* base_high */ |
| 258 | |
| 259 | /* Unused Desciptor - (matches Linux) */ |
| 260 | .word 0x0000 /* limit_low */ |
| 261 | .word 0x0000 /* base_low */ |
| 262 | .byte 0x00 /* base_middle */ |
| 263 | .byte 0x00 /* access */ |
| 264 | .byte 0x00 /* flags + limit_high */ |
| 265 | .byte 0x00 /* base_high */ |
| 266 | |
| 267 | /* |
| 268 | * The Code Segment Descriptor: |
| 269 | * - Base = 0x00000000 |
| 270 | * - Size = 4GB |
| 271 | * - Access = Present, Ring 0, Exec (Code), Readable |
| 272 | * - Flags = 4kB Granularity, 32-bit |
| 273 | */ |
| 274 | .word 0xffff /* limit_low */ |
| 275 | .word 0x0000 /* base_low */ |
| 276 | .byte 0x00 /* base_middle */ |
| 277 | .byte 0x9b /* access */ |
| 278 | .byte 0xcf /* flags + limit_high */ |
| 279 | .byte 0x00 /* base_high */ |
| 280 | |
| 281 | /* |
| 282 | * The Data Segment Descriptor: |
| 283 | * - Base = 0x00000000 |
| 284 | * - Size = 4GB |
| 285 | * - Access = Present, Ring 0, Non-Exec (Data), Writable |
| 286 | * - Flags = 4kB Granularity, 32-bit |
| 287 | */ |
| 288 | .word 0xffff /* limit_low */ |
| 289 | .word 0x0000 /* base_low */ |
| 290 | .byte 0x00 /* base_middle */ |
| 291 | .byte 0x93 /* access */ |
| 292 | .byte 0xcf /* flags + limit_high */ |
| 293 | .byte 0x00 /* base_high */ |
| 294 | #endif |