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roy zangc6411c02006-11-02 18:55:04 +08001/*
2 * Copyright (c) 2005 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2006
5 * Alex Bounine , Tundra Semiconductor Corp.
roy zang4efe20c2006-12-04 14:46:23 +08006 * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
roy zangc6411c02006-11-02 18:55:04 +08007 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
roy zangee311212006-12-01 11:47:36 +080027/*
roy zangc6411c02006-11-02 18:55:04 +080028 * board specific configuration options for Freescale
29 * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
30 *
roy zangee311212006-12-01 11:47:36 +080031 */
roy zangc6411c02006-11-02 18:55:04 +080032
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
roy zangc6411c02006-11-02 18:55:04 +080036/* Board Configuration Definitions */
37/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
38
39#define CONFIG_MPC7448HPC2
40
41#define CONFIG_74xx
Becky Bruce31d82672008-05-08 19:02:12 -050042#define CONFIG_HIGH_BATS /* High BATs supported */
roy zangc6411c02006-11-02 18:55:04 +080043#define CONFIG_ALTIVEC /* undef to disable */
44
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II"
roy zangee311212006-12-01 11:47:36 +080046#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
roy zangc6411c02006-11-02 18:55:04 +080047
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */
49#define CONFIG_SYS_CONFIG_BUS_CLK 133000000
roy zangc6411c02006-11-02 18:55:04 +080050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
roy zangc6411c02006-11-02 18:55:04 +080052
53#undef CONFIG_ECC /* disable ECC support */
54
55/* Board-specific Initialization Functions to be called */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_BOARD_ASM_INIT
roy zangc6411c02006-11-02 18:55:04 +080057#define CONFIG_BOARD_EARLY_INIT_F
58#define CONFIG_BOARD_EARLY_INIT_R
59#define CONFIG_MISC_INIT_R
60
Gerald Van Barenfec6d9e2008-06-03 20:34:45 -040061#define CONFIG_HAS_ETH0
roy zangc6411c02006-11-02 18:55:04 +080062#define CONFIG_HAS_ETH1
roy zangc6411c02006-11-02 18:55:04 +080063
64#define CONFIG_ENV_OVERWRITE
65
66/*
67 * High Level Configuration Options
68 * (easy to change)
69 */
70
roy zangee311212006-12-01 11:47:36 +080071#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
roy zangc6411c02006-11-02 18:55:04 +080072
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073/*#define CONFIG_SYS_HUSH_PARSER */
74#undef CONFIG_SYS_HUSH_PARSER
roy zangc6411c02006-11-02 18:55:04 +080075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
roy zangc6411c02006-11-02 18:55:04 +080077
78/* Pass open firmware flat tree */
Gerald Van Baren589c0422008-06-03 20:24:58 -040079#define CONFIG_OF_LIBFDT 1
roy zangc6411c02006-11-02 18:55:04 +080080#define CONFIG_OF_BOARD_SETUP 1
81
roy zangc6411c02006-11-02 18:55:04 +080082#define OF_CPU "PowerPC,7448@0"
83#define OF_TSI "tsi108@c0000000"
84#define OF_TBCLK (bd->bi_busfreq / 8)
85#define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
86
87/*
88 * The following defines let you select what serial you want to use
89 * for your console driver.
90 *
91 * what to do:
roy zangee311212006-12-01 11:47:36 +080092 * If you have hacked a serial cable onto the second DUART channel,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 * change the CONFIG_SYS_DUART port from 1 to 0 below.
roy zangc6411c02006-11-02 18:55:04 +080094 *
95 */
96
roy zangee311212006-12-01 11:47:36 +080097#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_NS16550
99#define CONFIG_SYS_NS16550_SERIAL
100#define CONFIG_SYS_NS16550_REG_SIZE 1
101#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8
roy zangc6411c02006-11-02 18:55:04 +0800102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
104#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
105#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
roy zangc6411c02006-11-02 18:55:04 +0800106
roy zangee311212006-12-01 11:47:36 +0800107#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
roy zangc6411c02006-11-02 18:55:04 +0800108#define CONFIG_ZERO_BOOTDELAY_CHECK
109
110#undef CONFIG_BOOTARGS
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100111/* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
roy zangc6411c02006-11-02 18:55:04 +0800112
113#if (CONFIG_BOOTDELAY >= 0)
roy zangee311212006-12-01 11:47:36 +0800114#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
roy zangc6411c02006-11-02 18:55:04 +0800115 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
116 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
117
118#define CONFIG_BOOTARGS "console=ttyS0,115200"
119#endif
120
121#undef CONFIG_EXTRA_ENV_SETTINGS
122
roy zangee311212006-12-01 11:47:36 +0800123#define CONFIG_SERIAL "No. 1"
roy zangc6411c02006-11-02 18:55:04 +0800124
125/* Networking Configuration */
126
roy zangee311212006-12-01 11:47:36 +0800127#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */
roy zangc6411c02006-11-02 18:55:04 +0800128
129#define CONFIG_TSI108_ETH
roy zangee311212006-12-01 11:47:36 +0800130#define CONFIG_TSI108_ETH_NUM_PORTS 2
roy zangc6411c02006-11-02 18:55:04 +0800131
132#define CONFIG_NET_MULTI
133
roy zangee311212006-12-01 11:47:36 +0800134#define CONFIG_BOOTFILE zImage.initrd.elf
135#define CONFIG_LOADADDR 0x400000
roy zangc6411c02006-11-02 18:55:04 +0800136
roy zangc6411c02006-11-02 18:55:04 +0800137/*-------------------------------------------------------------------------- */
138
roy zangee311212006-12-01 11:47:36 +0800139#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
roy zangc6411c02006-11-02 18:55:04 +0800141
142#undef CONFIG_WATCHDOG /* watchdog disabled */
143
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500144/*
145 * BOOTP options
146 */
147#define CONFIG_BOOTP_SUBNETMASK
148#define CONFIG_BOOTP_GATEWAY
149#define CONFIG_BOOTP_HOSTNAME
150#define CONFIG_BOOTP_BOOTPATH
151#define CONFIG_BOOTP_BOOTFILESIZE
roy zangc6411c02006-11-02 18:55:04 +0800152
roy zangc6411c02006-11-02 18:55:04 +0800153
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500154/*
155 * Command line configuration.
156 */
157#include <config_cmd_default.h>
158
159#define CONFIG_CMD_ASKENV
160#define CONFIG_CMD_CACHE
161#define CONFIG_CMD_PCI
162#define CONFIG_CMD_I2C
163#define CONFIG_CMD_SDRAM
164#define CONFIG_CMD_EEPROM
165#define CONFIG_CMD_FLASH
166#define CONFIG_CMD_ENV
167#define CONFIG_CMD_BSP
168#define CONFIG_CMD_DHCP
169#define CONFIG_CMD_PING
170#define CONFIG_CMD_DATE
171
roy zangc6411c02006-11-02 18:55:04 +0800172
173/*set date in u-boot*/
174#define CONFIG_RTC_M48T35A
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000
176#define CONFIG_SYS_NVRAM_SIZE 0x8000
roy zangc6411c02006-11-02 18:55:04 +0800177/*
178 * Miscellaneous configurable options
179 */
roy zangee311212006-12-01 11:47:36 +0800180#define CONFIG_VERSION_VARIABLE 1
roy zangc6411c02006-11-02 18:55:04 +0800181#define CONFIG_TSI108_I2C
182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
184#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
roy zangc6411c02006-11-02 18:55:04 +0800185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_LONGHELP /* undef to save memory */
187#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
roy zangc6411c02006-11-02 18:55:04 +0800188
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500189#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
roy zangee311212006-12-01 11:47:36 +0800191#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
roy zangc6411c02006-11-02 18:55:04 +0800192#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
roy zangc6411c02006-11-02 18:55:04 +0800194#endif
195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
197#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
198#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
roy zangc6411c02006-11-02 18:55:04 +0800199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
201#define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
roy zangc6411c02006-11-02 18:55:04 +0800202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
roy zangc6411c02006-11-02 18:55:04 +0800204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
roy zangc6411c02006-11-02 18:55:04 +0800206
207/*
208 * Low Level Configuration Settings
209 * (address mappings, register initial values, etc.)
210 * You should know what you are doing if you make changes here.
211 */
212
213/*-----------------------------------------------------------------------
214 * Definitions for initial stack pointer and data area
215 */
216
217/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
roy zangc6411c02006-11-02 18:55:04 +0800219 * To an unused memory region. The stack will remain in cache until RAM
220 * is initialized
roy zangee311212006-12-01 11:47:36 +0800221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#undef CONFIG_SYS_INIT_RAM_LOCK
223#define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
224#define CONFIG_SYS_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */
roy zangc6411c02006-11-02 18:55:04 +0800225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for init data */
227#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
roy zangc6411c02006-11-02 18:55:04 +0800228
229/*-----------------------------------------------------------------------
230 * Start addresses for the final memory configuration
231 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
roy zangc6411c02006-11-02 18:55:04 +0800233 */
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
236#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
roy zangc6411c02006-11-02 18:55:04 +0800237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
239#define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
roy zangc6411c02006-11-02 18:55:04 +0800240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
roy zangc6411c02006-11-02 18:55:04 +0800242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
roy zangc6411c02006-11-02 18:55:04 +0800244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
roy zangc6411c02006-11-02 18:55:04 +0800246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */
248#define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
roy zangc6411c02006-11-02 18:55:04 +0800249
250#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
251
roy zangee311212006-12-01 11:47:36 +0800252#define PCI0_IO_BASE_BOOTM 0xfd000000
roy zangc6411c02006-11-02 18:55:04 +0800253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_RESET_ADDRESS 0x3fffff00
255#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
256#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* u-boot code base */
257#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
roy zangc6411c02006-11-02 18:55:04 +0800258
259/* Peripheral Device section */
260
roy zangee311212006-12-01 11:47:36 +0800261/*
roy zangc6411c02006-11-02 18:55:04 +0800262 * Resources on the Tsi108
roy zangee311212006-12-01 11:47:36 +0800263 */
roy zangc6411c02006-11-02 18:55:04 +0800264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
266#define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
roy zangc6411c02006-11-02 18:55:04 +0800267
268#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
269
270#undef DISABLE_PBM
271
roy zangee311212006-12-01 11:47:36 +0800272/*
roy zangc6411c02006-11-02 18:55:04 +0800273 * PCI stuff
roy zangee311212006-12-01 11:47:36 +0800274 *
roy zangc6411c02006-11-02 18:55:04 +0800275 */
276
277#define CONFIG_PCI /* include pci support */
278#define CONFIG_TSI108_PCI /* include tsi108 pci support */
279
roy zangee311212006-12-01 11:47:36 +0800280#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
281#define PCI_HOST_FORCE 1 /* configure as pci host */
282#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
roy zangc6411c02006-11-02 18:55:04 +0800283
284#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
285#define CONFIG_PCI_PNP /* do pci plug-and-play */
286
287/* PCI MEMORY MAP section */
288
289/* PCI view of System Memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
291#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
292#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
roy zangc6411c02006-11-02 18:55:04 +0800293
294/* PCI Memory Space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS)
296#define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */
297#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
roy zangc6411c02006-11-02 18:55:04 +0800298
299/* PCI I/O Space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_PCI_IO_BUS 0x00000000
301#define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
roy zangc6411c02006-11-02 18:55:04 +0800302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */
roy zangc6411c02006-11-02 18:55:04 +0800304
305#define _IO_BASE 0x00000000 /* points to PCI I/O space */
306
307/* PCI Config Space mapping */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
309#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */
roy zangc6411c02006-11-02 18:55:04 +0800310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_IBAT0U 0xFE0003FF
312#define CONFIG_SYS_IBAT0L 0xFE000002
roy zangc6411c02006-11-02 18:55:04 +0800313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_IBAT1U 0x00007FFF
315#define CONFIG_SYS_IBAT1L 0x00000012
roy zangc6411c02006-11-02 18:55:04 +0800316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_IBAT2U 0x80007FFF
318#define CONFIG_SYS_IBAT2L 0x80000022
roy zangc6411c02006-11-02 18:55:04 +0800319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_IBAT3U 0x00000000
321#define CONFIG_SYS_IBAT3L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_IBAT4U 0x00000000
324#define CONFIG_SYS_IBAT4L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_IBAT5U 0x00000000
327#define CONFIG_SYS_IBAT5L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_IBAT6U 0x00000000
330#define CONFIG_SYS_IBAT6L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_IBAT7U 0x00000000
333#define CONFIG_SYS_IBAT7L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_DBAT0U 0xE0003FFF
336#define CONFIG_SYS_DBAT0L 0xE000002A
roy zangc6411c02006-11-02 18:55:04 +0800337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_DBAT1U 0x00007FFF
339#define CONFIG_SYS_DBAT1L 0x00000012
roy zangc6411c02006-11-02 18:55:04 +0800340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_DBAT2U 0x00000000
342#define CONFIG_SYS_DBAT2L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_DBAT3U 0xC0000003
345#define CONFIG_SYS_DBAT3L 0xC000002A
roy zangc6411c02006-11-02 18:55:04 +0800346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_DBAT4U 0x00000000
348#define CONFIG_SYS_DBAT4L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_DBAT5U 0x00000000
351#define CONFIG_SYS_DBAT5L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_DBAT6U 0x00000000
354#define CONFIG_SYS_DBAT6L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_DBAT7U 0x00000000
357#define CONFIG_SYS_DBAT7L 0x00000000
roy zangc6411c02006-11-02 18:55:04 +0800358
359/* I2C addresses for the two DIMM SPD chips */
roy zangee311212006-12-01 11:47:36 +0800360#define DIMM0_I2C_ADDR 0x51
361#define DIMM1_I2C_ADDR 0x52
roy zangc6411c02006-11-02 18:55:04 +0800362
363/*
364 * For booting Linux, the board info and command line data
365 * have to be in the first 8 MB of memory, since this is
366 * the maximum mapped by the Linux kernel during initialization.
367 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
roy zangc6411c02006-11-02 18:55:04 +0800369
370/*-----------------------------------------------------------------------
371 * FLASH organization
372 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
roy zangee311212006-12-01 11:47:36 +0800374#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
roy zangc6411c02006-11-02 18:55:04 +0800376
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200377#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_FLASH_CFI
379#define CONFIG_SYS_WRITE_SWAPPED_DATA
roy zangc6411c02006-11-02 18:55:04 +0800380
roy zangee311212006-12-01 11:47:36 +0800381#define PHYS_FLASH_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_MAX_FLASH_SECT (128)
roy zangc6411c02006-11-02 18:55:04 +0800383
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200384#define CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200385#define CONFIG_ENV_ADDR 0xFC000000
roy zangc6411c02006-11-02 18:55:04 +0800386
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200387#define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
388#define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
roy zangc6411c02006-11-02 18:55:04 +0800389
390/*-----------------------------------------------------------------------
391 * Cache Configuration
392 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger5dc11a52007-07-04 22:33:01 -0500394#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
roy zangc6411c02006-11-02 18:55:04 +0800396#endif
397
398/*-----------------------------------------------------------------------
399 * L2CR setup -- make sure this is right for your board!
400 * look in include/mpc74xx.h for the defines used here
401 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#undef CONFIG_SYS_L2
roy zangc6411c02006-11-02 18:55:04 +0800403
roy zangee311212006-12-01 11:47:36 +0800404#define L2_INIT 0
405#define L2_ENABLE (L2_INIT | L2CR_L2E)
roy zangc6411c02006-11-02 18:55:04 +0800406
407/*
408 * Internal Definitions
409 *
410 * Boot Flags
411 */
roy zangee311212006-12-01 11:47:36 +0800412#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
413#define BOOTFLAG_WARM 0x02 /* Software reboot */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
roy zangee311212006-12-01 11:47:36 +0800415#endif /* __CONFIG_H */