blob: f428f7e9aa66674cda441c887ce6129cbb04765d [file] [log] [blame]
wdenke887afc2002-08-27 09:44:07 +00001/*
2 * (C) Copyright 2000
3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
wdenke887afc2002-08-27 09:44:07 +000026#if defined(CONFIG_8xx)
27#include <mpc8xx.h>
stroesee075fbe2003-12-09 14:59:11 +000028#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
wdenke887afc2002-08-27 09:44:07 +000029#include <asm/processor.h>
wdenk0db5bca2003-03-31 17:27:09 +000030#elif defined (CONFIG_5xx)
31#include <mpc5xx.h>
wdenk56523f12004-07-11 17:40:54 +000032#elif defined (CONFIG_MPC5200)
33#include <mpc5xxx.h>
wdenke887afc2002-08-27 09:44:07 +000034#endif
35#if (CONFIG_COMMANDS & CFG_CMD_REGINFO)
36
37int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
38{
39#if defined(CONFIG_8xx)
40 volatile immap_t *immap = (immap_t *)CFG_IMMR;
41 volatile memctl8xx_t *memctl = &immap->im_memctl;
42 volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
43 volatile sit8xx_t *timers = &immap->im_sit;
44
45 /* Hopefully more PowerPC knowledgable people will add code to display
46 * other useful registers
47 */
48
wdenk4b9206e2004-03-23 22:14:11 +000049 printf ("\nSystem Configuration registers\n"
wdenke887afc2002-08-27 09:44:07 +000050
wdenk4b9206e2004-03-23 22:14:11 +000051 "\tIMMR\t0x%08X\n", get_immr(0));
wdenke887afc2002-08-27 09:44:07 +000052
53 printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
54 printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
55
56 printf("\tSWT\t0x%08X", sysconf->sc_swt);
57 printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
58
59 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
60 sysconf->sc_sipend, sysconf->sc_simask);
61 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
62 sysconf->sc_siel, sysconf->sc_sivec);
63 printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
64 sysconf->sc_tesr, sysconf->sc_sdcr);
65
wdenk4b9206e2004-03-23 22:14:11 +000066 printf ("Memory Controller Registers\n"
wdenke887afc2002-08-27 09:44:07 +000067
wdenk4b9206e2004-03-23 22:14:11 +000068 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
wdenke887afc2002-08-27 09:44:07 +000069 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
70 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
71 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
72 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
73 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
74 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
75 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
wdenk4b9206e2004-03-23 22:14:11 +000076 printf ("\n"
77 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
wdenke887afc2002-08-27 09:44:07 +000078 memctl->memc_mamr, memctl->memc_mbmr );
79 printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
80 memctl->memc_mstat, memctl->memc_mptpr );
81 printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
82
wdenk4b9206e2004-03-23 22:14:11 +000083 printf ("\nSystem Integration Timers\n"
84 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
wdenke887afc2002-08-27 09:44:07 +000085 timers->sit_tbscr, timers->sit_rtcsc);
86 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
87
88 /*
89 * May be some CPM info here?
90 */
91
stroesee075fbe2003-12-09 14:59:11 +000092#elif defined (CONFIG_405GP)
wdenk50015ab2003-12-09 20:22:16 +000093 printf ("\n405GP registers; MSR=%08x\n",mfmsr());
94 printf ("\nUniversal Interrupt Controller Regs\n"
95 "uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
96 "\n"
97 "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
wdenke887afc2002-08-27 09:44:07 +000098 mfdcr(uicsr),
99 mfdcr(uicsrs),
100 mfdcr(uicer),
101 mfdcr(uiccr),
102 mfdcr(uicpr),
103 mfdcr(uictr),
104 mfdcr(uicmsr),
105 mfdcr(uicvr),
106 mfdcr(uicvcr));
107
wdenk4b9206e2004-03-23 22:14:11 +0000108 puts ("\nMemory (SDRAM) Configuration\n"
wdenk50015ab2003-12-09 20:22:16 +0000109 "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
wdenke887afc2002-08-27 09:44:07 +0000110
111 mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd));
112 mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd));
113 mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd));
114 mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd));
115 mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd));
116 mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
117 mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
118 mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
119
wdenk4b9206e2004-03-23 22:14:11 +0000120 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000121 "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
wdenke887afc2002-08-27 09:44:07 +0000122 mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
123 mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
124 mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd));
125 mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd));
126 mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
127 mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd));
128 mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd));
129
130 printf ("\n\n"
wdenk50015ab2003-12-09 20:22:16 +0000131 "DMA Channels\n"
132 "dmasr dmasgc dmaadr\n"
133 "%08x %08x %08x\n"
134 "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n"
135 "%08x %08x %08x %08x %08x\n"
136 "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n"
137 "%08x %08x %08x %08x %08x\n",
138 mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
139 mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
140 mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
wdenke887afc2002-08-27 09:44:07 +0000141
142 printf (
wdenk50015ab2003-12-09 20:22:16 +0000143 "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
144 "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
145 mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
146 mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
wdenke887afc2002-08-27 09:44:07 +0000147
wdenk4b9206e2004-03-23 22:14:11 +0000148 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000149 "External Bus\n"
150 "pbear pbesr0 pbesr1 epcr\n");
wdenke887afc2002-08-27 09:44:07 +0000151 mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
152 mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
153 mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
154 mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
155
wdenk4b9206e2004-03-23 22:14:11 +0000156 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000157 "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
wdenke887afc2002-08-27 09:44:07 +0000158 mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
159 mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
160 mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
161 mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
162 mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
163 mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
164 mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
165 mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
166
wdenk4b9206e2004-03-23 22:14:11 +0000167 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000168 "pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n");
wdenke887afc2002-08-27 09:44:07 +0000169 mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
170 mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
171 mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd));
172 mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd));
173 mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd));
174 mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd));
175 mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd));
176 mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
177
wdenk4b9206e2004-03-23 22:14:11 +0000178 puts ("\n\n");
wdenk56523f12004-07-11 17:40:54 +0000179
stroesee075fbe2003-12-09 14:59:11 +0000180#elif defined(CONFIG_405EP)
wdenk50015ab2003-12-09 20:22:16 +0000181 printf ("\n405EP registers; MSR=%08x\n",mfmsr());
182 printf ("\nUniversal Interrupt Controller Regs\n"
183 "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
184 "\n"
185 "%08x %08x %08x %08x %08x %08x %08x %08x\n",
stroesee075fbe2003-12-09 14:59:11 +0000186 mfdcr(uicsr),
187 mfdcr(uicer),
188 mfdcr(uiccr),
189 mfdcr(uicpr),
190 mfdcr(uictr),
191 mfdcr(uicmsr),
192 mfdcr(uicvr),
193 mfdcr(uicvcr));
194
wdenk4b9206e2004-03-23 22:14:11 +0000195 puts ("\nMemory (SDRAM) Configuration\n"
wdenk50015ab2003-12-09 20:22:16 +0000196 "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
stroesee075fbe2003-12-09 14:59:11 +0000197
198 mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
199 mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
200 mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
201 mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
202 mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
203 mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
204
205 printf ("\n\n"
wdenk50015ab2003-12-09 20:22:16 +0000206 "DMA Channels\n"
207 "dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
208 "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
209 "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
210 mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
211 mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
212 mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
stroesee075fbe2003-12-09 14:59:11 +0000213
214 printf (
wdenk50015ab2003-12-09 20:22:16 +0000215 "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
216 "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
217 mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
218 mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
stroesee075fbe2003-12-09 14:59:11 +0000219
wdenk4b9206e2004-03-23 22:14:11 +0000220 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000221 "External Bus\n"
222 "pbear pbesr0 pbesr1 epcr\n");
stroesee075fbe2003-12-09 14:59:11 +0000223 mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
224 mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
225 mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
226 mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
227
wdenk4b9206e2004-03-23 22:14:11 +0000228 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000229 "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
stroesee075fbe2003-12-09 14:59:11 +0000230 mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
231 mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
232 mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
233 mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
234 mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
235 mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
236 mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
237 mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
238
wdenk4b9206e2004-03-23 22:14:11 +0000239 puts ("\n"
wdenk50015ab2003-12-09 20:22:16 +0000240 "pb4cr pb4ap\n");
stroesee075fbe2003-12-09 14:59:11 +0000241 mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
242 mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
243
wdenk4b9206e2004-03-23 22:14:11 +0000244 puts ("\n\n");
wdenk0db5bca2003-03-31 17:27:09 +0000245#elif defined(CONFIG_5xx)
wdenke887afc2002-08-27 09:44:07 +0000246
wdenk0db5bca2003-03-31 17:27:09 +0000247 volatile immap_t *immap = (immap_t *)CFG_IMMR;
248 volatile memctl5xx_t *memctl = &immap->im_memctl;
249 volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
250 volatile sit5xx_t *timers = &immap->im_sit;
251 volatile car5xx_t *car = &immap->im_clkrst;
252 volatile uimb5xx_t *uimb = &immap->im_uimb;
253
wdenk4b9206e2004-03-23 22:14:11 +0000254 puts ("\nSystem Configuration registers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000255 printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
256 printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
257 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
258 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
259 printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
260
wdenk4b9206e2004-03-23 22:14:11 +0000261 puts ("\nMemory Controller Registers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000262 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
263 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
264 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
265 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
266 printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
267 printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
268
wdenk4b9206e2004-03-23 22:14:11 +0000269 puts ("\nSystem Integration Timers\n");
wdenk0db5bca2003-03-31 17:27:09 +0000270 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
271 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
272
wdenk4b9206e2004-03-23 22:14:11 +0000273 puts ("\nClocks and Reset\n");
wdenk0db5bca2003-03-31 17:27:09 +0000274 printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
275
wdenk4b9206e2004-03-23 22:14:11 +0000276 puts ("\nU-Bus to IMB3 Bus Interface\n");
wdenk0db5bca2003-03-31 17:27:09 +0000277 printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
wdenk4b9206e2004-03-23 22:14:11 +0000278 puts ("\n\n");
wdenk56523f12004-07-11 17:40:54 +0000279
280#elif defined(CONFIG_MPC5200)
281 puts ("\nMPC5200 registers\n");
282 printf ("MBAR=%08x\n", CFG_MBAR);
283 puts ("Memory map registers\n");
wdenk81050922004-07-11 20:04:51 +0000284 printf ("\tCS0: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000285 *(volatile ulong*)MPC5XXX_CS0_START,
286 *(volatile ulong*)MPC5XXX_CS0_STOP,
287 *(volatile ulong*)MPC5XXX_CS0_CFG,
288 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000289 printf ("\tCS1: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000290 *(volatile ulong*)MPC5XXX_CS1_START,
291 *(volatile ulong*)MPC5XXX_CS1_STOP,
292 *(volatile ulong*)MPC5XXX_CS1_CFG,
293 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000294 printf ("\tCS2: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000295 *(volatile ulong*)MPC5XXX_CS2_START,
296 *(volatile ulong*)MPC5XXX_CS2_STOP,
297 *(volatile ulong*)MPC5XXX_CS2_CFG,
298 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000299 printf ("\tCS3: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000300 *(volatile ulong*)MPC5XXX_CS3_START,
301 *(volatile ulong*)MPC5XXX_CS3_STOP,
302 *(volatile ulong*)MPC5XXX_CS3_CFG,
303 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000304 printf ("\tCS4: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000305 *(volatile ulong*)MPC5XXX_CS4_START,
306 *(volatile ulong*)MPC5XXX_CS4_STOP,
307 *(volatile ulong*)MPC5XXX_CS4_CFG,
308 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000309 printf ("\tCS5: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000310 *(volatile ulong*)MPC5XXX_CS5_START,
311 *(volatile ulong*)MPC5XXX_CS5_STOP,
312 *(volatile ulong*)MPC5XXX_CS5_CFG,
313 (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000314 printf ("\tCS6: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000315 *(volatile ulong*)MPC5XXX_CS6_START,
316 *(volatile ulong*)MPC5XXX_CS6_STOP,
317 *(volatile ulong*)MPC5XXX_CS6_CFG,
318 (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000319 printf ("\tCS7: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000320 *(volatile ulong*)MPC5XXX_CS7_START,
321 *(volatile ulong*)MPC5XXX_CS7_STOP,
322 *(volatile ulong*)MPC5XXX_CS7_CFG,
323 (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000324 printf ("\tBOOTCS: start %08X\tstop %08X\tconfig %08X\ten %d\n",
wdenk56523f12004-07-11 17:40:54 +0000325 *(volatile ulong*)MPC5XXX_BOOTCS_START,
326 *(volatile ulong*)MPC5XXX_BOOTCS_STOP,
327 *(volatile ulong*)MPC5XXX_BOOTCS_CFG,
328 (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
wdenk81050922004-07-11 20:04:51 +0000329 printf ("\tSDRAMCS0: %08X\n",
wdenk56523f12004-07-11 17:40:54 +0000330 *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
Wolfgang Denk45a212c2006-07-19 17:52:30 +0200331 printf ("\tSDRAMCS1: %08X\n",
wdenk56523f12004-07-11 17:40:54 +0000332 *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
333#endif /* CONFIG_MPC5200 */
wdenke887afc2002-08-27 09:44:07 +0000334 return 0;
335}
336
wdenk0db5bca2003-03-31 17:27:09 +0000337#endif /* CONFIG_COMMANDS & CFG_CMD_REGINFO */
wdenk8bde7f72003-06-27 21:31:46 +0000338
339
340 /**************************************************/
341
wdenk56523f12004-07-11 17:40:54 +0000342#if ( defined(CONFIG_8xx) || defined(CONFIG_405GP) || \
343 defined(CONFIG_405EP) || defined(CONFIG_MPC5200) ) && \
344 (CONFIG_COMMANDS & CFG_CMD_REGINFO)
wdenk8bde7f72003-06-27 21:31:46 +0000345
wdenk0d498392003-07-01 21:06:45 +0000346U_BOOT_CMD(
347 reginfo, 2, 1, do_reginfo,
wdenk8bde7f72003-06-27 21:31:46 +0000348 "reginfo - print register information\n",
349);
350#endif