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wdenk945af8d2003-07-16 21:53:01 +00001/*
wdenk5e5f9ed2005-04-13 23:15:10 +00002 * (C) Copyright 2003-2005
wdenk945af8d2003-07-16 21:53:01 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9#include <common.h>
10#include <mpc5xxx.h>
11#include <malloc.h>
12#include <net.h>
13#include <miiphy.h>
14#include "sdma.h"
15#include "fec.h"
16
Wolfgang Denkd87080b2006-03-31 18:32:53 +020017DECLARE_GLOBAL_DATA_PTR;
18
wdenk77846742003-07-26 08:08:08 +000019/* #define DEBUG 0x28 */
wdenk945af8d2003-07-16 21:53:01 +000020
Jon Loeliger44312832007-07-09 19:06:00 -050021#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
wdenkcbd8a352004-02-24 02:00:03 +000022 defined(CONFIG_MPC5xxx_FEC)
wdenk945af8d2003-07-16 21:53:01 +000023
Jon Loeliger44312832007-07-09 19:06:00 -050024#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
Marian Balakowicz63ff0042005-10-28 22:30:33 +020025#error "CONFIG_MII has to be defined!"
26#endif
27
wdenk945af8d2003-07-16 21:53:01 +000028#if (DEBUG & 0x60)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020029static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
30static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
wdenk945af8d2003-07-16 21:53:01 +000031#endif /* DEBUG */
32
33#if (DEBUG & 0x40)
34static uint32 local_crc32(char *string, unsigned int crc_value, int len);
35#endif
36
wdenk77846742003-07-26 08:08:08 +000037typedef struct {
38 uint8 data[1500]; /* actual data */
39 int length; /* actual length */
40 int used; /* buffer in use or not */
41 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
42} NBUF;
43
Marian Balakowicz63ff0042005-10-28 22:30:33 +020044int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
45int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
46
wdenk945af8d2003-07-16 21:53:01 +000047/********************************************************************/
wdenkd4ca31c2004-01-02 14:00:00 +000048#if (DEBUG & 0x2)
Marian Balakowicz63ff0042005-10-28 22:30:33 +020049static void mpc5xxx_fec_phydump (char *devname)
wdenkd4ca31c2004-01-02 14:00:00 +000050{
51 uint16 phyStatus, i;
52 uint8 phyAddr = CONFIG_PHY_ADDR;
53 uint8 reg_mask[] = {
54#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
55 /* regs to print: 0...7, 16...19, 21, 23, 24 */
56 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
58#else
59 /* regs to print: 0...8, 16...20 */
60 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
61 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
62#endif
63 };
64
65 for (i = 0; i < 32; i++) {
66 if (reg_mask[i]) {
Marian Balakowicz63ff0042005-10-28 22:30:33 +020067 miiphy_read(devname, phyAddr, i, &phyStatus);
wdenkd4ca31c2004-01-02 14:00:00 +000068 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
69 }
70 }
71}
72#endif
73
74/********************************************************************/
wdenk945af8d2003-07-16 21:53:01 +000075static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
76{
77 int ix;
78 char *data;
wdenk77846742003-07-26 08:08:08 +000079 static int once = 0;
wdenk945af8d2003-07-16 21:53:01 +000080
wdenk945af8d2003-07-16 21:53:01 +000081 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
wdenk77846742003-07-26 08:08:08 +000082 if (!once) {
83 data = (char *)malloc(FEC_MAX_PKT_SIZE);
84 if (data == NULL) {
85 printf ("RBD INIT FAILED\n");
86 return -1;
87 }
88 fec->rbdBase[ix].dataPointer = (uint32)data;
wdenk945af8d2003-07-16 21:53:01 +000089 }
90 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
91 fec->rbdBase[ix].dataLength = 0;
wdenk945af8d2003-07-16 21:53:01 +000092 }
wdenk77846742003-07-26 08:08:08 +000093 once ++;
wdenk945af8d2003-07-16 21:53:01 +000094
95 /*
96 * have the last RBD to close the ring
97 */
98 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
99 fec->rbdIndex = 0;
100
101 return 0;
102}
103
104/********************************************************************/
105static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
106{
107 int ix;
108
109 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
110 fec->tbdBase[ix].status = 0;
111 }
112
113 /*
114 * Have the last TBD to close the ring
115 */
116 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
117
118 /*
119 * Initialize some indices
120 */
121 fec->tbdIndex = 0;
122 fec->usedTbdIndex = 0;
123 fec->cleanTbdNum = FEC_TBD_NUM;
124}
125
126/********************************************************************/
wdenk151ab832005-02-24 22:44:16 +0000127static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
wdenk945af8d2003-07-16 21:53:01 +0000128{
129 /*
130 * Reset buffer descriptor as empty
131 */
132 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
133 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
134 else
135 pRbd->status = FEC_RBD_EMPTY;
136
137 pRbd->dataLength = 0;
138
139 /*
140 * Now, we have an empty RxBD, restart the SmartDMA receive task
141 */
142 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
143
144 /*
145 * Increment BD count
146 */
147 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
148}
149
150/********************************************************************/
151static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
152{
wdenk151ab832005-02-24 22:44:16 +0000153 volatile FEC_TBD *pUsedTbd;
wdenk945af8d2003-07-16 21:53:01 +0000154
155#if (DEBUG & 0x1)
156 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
157 fec->cleanTbdNum, fec->usedTbdIndex);
158#endif
159
160 /*
161 * process all the consumed TBDs
162 */
163 while (fec->cleanTbdNum < FEC_TBD_NUM) {
164 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
165 if (pUsedTbd->status & FEC_TBD_READY) {
166#if (DEBUG & 0x20)
167 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
168#endif
169 return;
170 }
171
172 /*
173 * clean this buffer descriptor
174 */
175 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
176 pUsedTbd->status = FEC_TBD_WRAP;
177 else
178 pUsedTbd->status = 0;
179
180 /*
181 * update some indeces for a correct handling of the TBD ring
182 */
183 fec->cleanTbdNum++;
184 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
185 }
186}
187
188/********************************************************************/
189static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
190{
191 uint8 currByte; /* byte for which to compute the CRC */
192 int byte; /* loop - counter */
193 int bit; /* loop - counter */
194 uint32 crc = 0xffffffff; /* initial value */
195
196 /*
197 * The algorithm used is the following:
198 * we loop on each of the six bytes of the provided address,
199 * and we compute the CRC by left-shifting the previous
200 * value by one position, so that each bit in the current
201 * byte of the address may contribute the calculation. If
202 * the latter and the MSB in the CRC are different, then
203 * the CRC value so computed is also ex-ored with the
204 * "polynomium generator". The current byte of the address
205 * is also shifted right by one bit at each iteration.
206 * This is because the CRC generatore in hardware is implemented
207 * as a shift-register with as many ex-ores as the radixes
208 * in the polynomium. This suggests that we represent the
209 * polynomiumm itself as a 32-bit constant.
210 */
211 for (byte = 0; byte < 6; byte++) {
212 currByte = mac[byte];
213 for (bit = 0; bit < 8; bit++) {
214 if ((currByte & 0x01) ^ (crc & 0x01)) {
215 crc >>= 1;
216 crc = crc ^ 0xedb88320;
217 } else {
218 crc >>= 1;
219 }
220 currByte >>= 1;
221 }
222 }
223
224 crc = crc >> 26;
225
226 /*
227 * Set individual hash table register
228 */
229 if (crc >= 32) {
230 fec->eth->iaddr1 = (1 << (crc - 32));
231 fec->eth->iaddr2 = 0;
232 } else {
233 fec->eth->iaddr1 = 0;
234 fec->eth->iaddr2 = (1 << crc);
235 }
236
237 /*
238 * Set physical address
239 */
240 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
241 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
242}
243
244/********************************************************************/
245static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
246{
247 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
248 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
wdenk945af8d2003-07-16 21:53:01 +0000249
250#if (DEBUG & 0x1)
251 printf ("mpc5xxx_fec_init... Begin\n");
252#endif
253
254 /*
255 * Initialize RxBD/TxBD rings
256 */
257 mpc5xxx_fec_rbd_init(fec);
258 mpc5xxx_fec_tbd_init(fec);
259
260 /*
wdenk945af8d2003-07-16 21:53:01 +0000261 * Clear FEC-Lite interrupt event register(IEVENT)
262 */
263 fec->eth->ievent = 0xffffffff;
264
265 /*
266 * Set interrupt mask register
267 */
268 fec->eth->imask = 0x00000000;
269
270 /*
271 * Set FEC-Lite receive control register(R_CNTRL):
272 */
273 if (fec->xcv_type == SEVENWIRE) {
274 /*
275 * Frame length=1518; 7-wire mode
276 */
277 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
278 } else {
279 /*
280 * Frame length=1518; MII mode;
281 */
282 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
283 }
284
wdenk7e780362004-04-08 22:31:29 +0000285 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
286 if (fec->xcv_type != SEVENWIRE) {
wdenk945af8d2003-07-16 21:53:01 +0000287 /*
wdenk7152b1d2003-09-05 23:19:14 +0000288 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
wdenk945af8d2003-07-16 21:53:01 +0000289 * and do not drop the Preamble.
290 */
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100291 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
wdenk945af8d2003-07-16 21:53:01 +0000292 }
293
294 /*
295 * Set Opcode/Pause Duration Register
296 */
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100297 fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
wdenk945af8d2003-07-16 21:53:01 +0000298
299 /*
300 * Set Rx FIFO alarm and granularity value
301 */
Wolfgang Denkc44ffb92005-09-04 23:19:41 +0200302 fec->eth->rfifo_cntrl = 0x0c000000
303 | (fec->eth->rfifo_cntrl & ~0x0f000000);
wdenk945af8d2003-07-16 21:53:01 +0000304 fec->eth->rfifo_alarm = 0x0000030c;
305#if (DEBUG & 0x22)
306 if (fec->eth->rfifo_status & 0x00700000 ) {
307 printf("mpc5xxx_fec_init() RFIFO error\n");
308 }
309#endif
310
311 /*
312 * Set Tx FIFO granularity value
313 */
Wolfgang Denkc44ffb92005-09-04 23:19:41 +0200314 fec->eth->tfifo_cntrl = 0x0c000000
315 | (fec->eth->tfifo_cntrl & ~0x0f000000);
wdenk945af8d2003-07-16 21:53:01 +0000316#if (DEBUG & 0x2)
317 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
318 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
319#endif
320
321 /*
322 * Set transmit fifo watermark register(X_WMRK), default = 64
323 */
324 fec->eth->tfifo_alarm = 0x00000080;
325 fec->eth->x_wmrk = 0x2;
326
327 /*
328 * Set individual address filter for unicast address
329 * and set physical address registers.
330 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200331 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
wdenk945af8d2003-07-16 21:53:01 +0000332
333 /*
334 * Set multicast address filter
335 */
336 fec->eth->gaddr1 = 0x00000000;
337 fec->eth->gaddr2 = 0x00000000;
338
339 /*
340 * Turn ON cheater FSM: ????
341 */
342 fec->eth->xmit_fsm = 0x03000000;
343
344#if defined(CONFIG_MPC5200)
345 /*
346 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
347 * work w/ the current receive task.
348 */
349 sdma->PtdCntrl |= 0x00000001;
350#endif
351
352 /*
353 * Set priority of different initiators
354 */
355 sdma->IPR0 = 7; /* always */
356 sdma->IPR3 = 6; /* Eth RX */
357 sdma->IPR4 = 5; /* Eth Tx */
358
359 /*
360 * Clear SmartDMA task interrupt pending bits
361 */
362 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
363
364 /*
wdenk945af8d2003-07-16 21:53:01 +0000365 * Initialize SmartDMA parameters stored in SRAM
366 */
wdenk151ab832005-02-24 22:44:16 +0000367 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
368 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
369 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
370 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
wdenk945af8d2003-07-16 21:53:01 +0000371
wdenk6c1362c2004-05-12 22:18:31 +0000372 /*
373 * Enable FEC-Lite controller
374 */
375 fec->eth->ecntrl |= 0x00000006;
376
377#if (DEBUG & 0x2)
378 if (fec->xcv_type != SEVENWIRE)
Heiko Schocher6dedf3d2006-12-21 16:14:48 +0100379 mpc5xxx_fec_phydump (dev->name);
wdenk6c1362c2004-05-12 22:18:31 +0000380#endif
381
382 /*
383 * Enable SmartDMA receive task
384 */
385 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
386
387#if (DEBUG & 0x1)
388 printf("mpc5xxx_fec_init... Done \n");
389#endif
390
391 return 1;
392}
393
394/********************************************************************/
395static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
396{
wdenk6c1362c2004-05-12 22:18:31 +0000397 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
398 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
399
400#if (DEBUG & 0x1)
401 printf ("mpc5xxx_fec_init_phy... Begin\n");
402#endif
403
404 /*
405 * Initialize GPIO pins
406 */
407 if (fec->xcv_type == SEVENWIRE) {
408 /* 10MBit with 7-wire operation */
wdenk6c7a1402004-07-11 19:17:20 +0000409#if defined(CONFIG_TOTAL5200)
410 /* 7-wire and USB2 on Ethernet */
411 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
412#else /* !CONFIG_TOTAL5200 */
413 /* 7-wire only */
wdenk6c1362c2004-05-12 22:18:31 +0000414 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
wdenk6c7a1402004-07-11 19:17:20 +0000415#endif /* CONFIG_TOTAL5200 */
wdenk6c1362c2004-05-12 22:18:31 +0000416 } else {
417 /* 100MBit with MD operation */
418 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
419 }
420
421 /*
422 * Clear FEC-Lite interrupt event register(IEVENT)
423 */
424 fec->eth->ievent = 0xffffffff;
425
426 /*
427 * Set interrupt mask register
428 */
429 fec->eth->imask = 0x00000000;
430
Bartlomiej Sieka008861a2007-05-07 22:36:15 +0200431/*
432 * In original Promess-provided code PHY initialization is disabled with the
433 * following comment: "Phy initialization is DISABLED for now. There was a
434 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
435 * PHY initialization for the Motion-PRO board, until a proper fix is found.
436 */
437
wdenk6c1362c2004-05-12 22:18:31 +0000438 if (fec->xcv_type != SEVENWIRE) {
439 /*
440 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
441 * and do not drop the Preamble.
442 */
443 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
444 }
445
wdenk945af8d2003-07-16 21:53:01 +0000446 if (fec->xcv_type != SEVENWIRE) {
447 /*
448 * Initialize PHY(LXT971A):
449 *
450 * Generally, on power up, the LXT971A reads its configuration
451 * pins to check for forced operation, If not cofigured for
452 * forced operation, it uses auto-negotiation/parallel detection
453 * to automatically determine line operating conditions.
454 * If the PHY device on the other side of the link supports
455 * auto-negotiation, the LXT971A auto-negotiates with it
456 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
457 * support auto-negotiation, the LXT971A automatically detects
458 * the presence of either link pulses(10Mbps PHY) or Idle
459 * symbols(100Mbps) and sets its operating conditions accordingly.
460 *
461 * When auto-negotiation is controlled by software, the following
462 * steps are recommended.
463 *
464 * Note:
465 * The physical address is dependent on hardware configuration.
466 *
467 */
468 int timeout = 1;
469 uint16 phyStatus;
470
471 /*
472 * Reset PHY, then delay 300ns
473 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200474 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
wdenk945af8d2003-07-16 21:53:01 +0000475 udelay(1000);
476
Heiko Schocher37403002007-04-14 05:26:48 +0200477#if defined(CONFIG_UC101)
478 /* Set the LED configuration Register for the UC101 Board */
479 miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
480#endif
wdenk945af8d2003-07-16 21:53:01 +0000481 if (fec->xcv_type == MII10) {
482 /*
483 * Force 10Base-T, FDX operation
484 */
wdenka57106f2003-09-16 17:29:31 +0000485#if (DEBUG & 0x2)
wdenk945af8d2003-07-16 21:53:01 +0000486 printf("Forcing 10 Mbps ethernet link... ");
wdenka57106f2003-09-16 17:29:31 +0000487#endif
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200488 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000489 /*
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200490 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
wdenk945af8d2003-07-16 21:53:01 +0000491 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200492 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
wdenk945af8d2003-07-16 21:53:01 +0000493
494 timeout = 20;
495 do { /* wait for link status to go down */
496 udelay(10000);
497 if ((timeout--) == 0) {
498#if (DEBUG & 0x2)
499 printf("hmmm, should not have waited...");
500#endif
501 break;
502 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200503 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000504#if (DEBUG & 0x2)
505 printf("=");
506#endif
507 } while ((phyStatus & 0x0004)); /* !link up */
508
509 timeout = 1000;
510 do { /* wait for link status to come back up */
511 udelay(10000);
512 if ((timeout--) == 0) {
513 printf("failed. Link is down.\n");
514 break;
515 }
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200516 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000517#if (DEBUG & 0x2)
518 printf("+");
519#endif
520 } while (!(phyStatus & 0x0004)); /* !link up */
521
dzuab209d52003-09-30 14:08:43 +0000522#if (DEBUG & 0x2)
wdenk945af8d2003-07-16 21:53:01 +0000523 printf ("done.\n");
dzuab209d52003-09-30 14:08:43 +0000524#endif
wdenk945af8d2003-07-16 21:53:01 +0000525 } else { /* MII100 */
526 /*
527 * Set the auto-negotiation advertisement register bits
528 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200529 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
wdenk945af8d2003-07-16 21:53:01 +0000530
531 /*
532 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
533 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200534 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
wdenk945af8d2003-07-16 21:53:01 +0000535
536 /*
537 * Wait for AN completion
538 */
539 timeout = 5000;
540 do {
541 udelay(1000);
542
543 if ((timeout--) == 0) {
544#if (DEBUG & 0x2)
545 printf("PHY auto neg 0 failed...\n");
546#endif
547 return -1;
548 }
549
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200550 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
wdenk945af8d2003-07-16 21:53:01 +0000551#if (DEBUG & 0x2)
552 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
553#endif
554 return -1;
555 }
wdenk7e780362004-04-08 22:31:29 +0000556 } while (!(phyStatus & 0x0004));
wdenk945af8d2003-07-16 21:53:01 +0000557
558#if (DEBUG & 0x2)
559 printf("PHY auto neg complete! \n");
560#endif
561 }
562
563 }
564
wdenk945af8d2003-07-16 21:53:01 +0000565#if (DEBUG & 0x2)
wdenkd4ca31c2004-01-02 14:00:00 +0000566 if (fec->xcv_type != SEVENWIRE)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200567 mpc5xxx_fec_phydump (dev->name);
wdenk945af8d2003-07-16 21:53:01 +0000568#endif
wdenkd4ca31c2004-01-02 14:00:00 +0000569
wdenk945af8d2003-07-16 21:53:01 +0000570
571#if (DEBUG & 0x1)
wdenk6c1362c2004-05-12 22:18:31 +0000572 printf("mpc5xxx_fec_init_phy... Done \n");
wdenk945af8d2003-07-16 21:53:01 +0000573#endif
574
wdenk013dc8d2003-08-07 14:52:18 +0000575 return 1;
wdenk945af8d2003-07-16 21:53:01 +0000576}
577
578/********************************************************************/
579static void mpc5xxx_fec_halt(struct eth_device *dev)
580{
wdenk77846742003-07-26 08:08:08 +0000581#if defined(CONFIG_MPC5200)
wdenk945af8d2003-07-16 21:53:01 +0000582 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
wdenk77846742003-07-26 08:08:08 +0000583#endif
584 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
wdenk945af8d2003-07-16 21:53:01 +0000585 int counter = 0xffff;
586
587#if (DEBUG & 0x2)
wdenkd4ca31c2004-01-02 14:00:00 +0000588 if (fec->xcv_type != SEVENWIRE)
Heiko Schocher6dedf3d2006-12-21 16:14:48 +0100589 mpc5xxx_fec_phydump (dev->name);
wdenk945af8d2003-07-16 21:53:01 +0000590#endif
591
wdenk945af8d2003-07-16 21:53:01 +0000592 /*
593 * mask FEC chip interrupts
594 */
595 fec->eth->imask = 0;
596
597 /*
598 * issue graceful stop command to the FEC transmitter if necessary
599 */
600 fec->eth->x_cntrl |= 0x00000001;
601
602 /*
603 * wait for graceful stop to register
604 */
605 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
606
wdenk945af8d2003-07-16 21:53:01 +0000607 /*
608 * Disable SmartDMA tasks
609 */
610 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
611 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
612
613#if defined(CONFIG_MPC5200)
614 /*
615 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
616 * done. It doesn't work w/ the current receive task.
617 */
618 sdma->PtdCntrl &= ~0x00000001;
619#endif
620
621 /*
622 * Disable the Ethernet Controller
623 */
624 fec->eth->ecntrl &= 0xfffffffd;
625
626 /*
627 * Clear FIFO status registers
628 */
629 fec->eth->rfifo_status &= 0x00700000;
630 fec->eth->tfifo_status &= 0x00700000;
631
632 fec->eth->reset_cntrl = 0x01000000;
633
634 /*
635 * Issue a reset command to the FEC chip
636 */
637 fec->eth->ecntrl |= 0x1;
638
639 /*
640 * wait at least 16 clock cycles
641 */
642 udelay(10);
643
644#if (DEBUG & 0x3)
645 printf("Ethernet task stopped\n");
646#endif
647}
648
649#if (DEBUG & 0x60)
650/********************************************************************/
651
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200652static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
wdenk945af8d2003-07-16 21:53:01 +0000653{
wdenkd4ca31c2004-01-02 14:00:00 +0000654 uint16 phyAddr = CONFIG_PHY_ADDR;
wdenk945af8d2003-07-16 21:53:01 +0000655 uint16 phyStatus;
656
657 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
658 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
659
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200660 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000661 printf("\nphyStatus: 0x%04x\n", phyStatus);
662 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
663 printf("ievent: 0x%08x\n", fec->eth->ievent);
664 printf("x_status: 0x%08x\n", fec->eth->x_status);
665 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
666
667 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
668 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
669 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
670 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
671 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
672 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
673 }
674}
675
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200676static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
wdenk945af8d2003-07-16 21:53:01 +0000677{
wdenkd4ca31c2004-01-02 14:00:00 +0000678 uint16 phyAddr = CONFIG_PHY_ADDR;
wdenk945af8d2003-07-16 21:53:01 +0000679 uint16 phyStatus;
680
681 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
682 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
683
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200684 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000685 printf("\nphyStatus: 0x%04x\n", phyStatus);
686 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
687 printf("ievent: 0x%08x\n", fec->eth->ievent);
688 printf("x_status: 0x%08x\n", fec->eth->x_status);
689 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
690
691 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
692 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
693 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
694 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
695 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
696 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
697 }
698}
699#endif /* DEBUG */
700
701/********************************************************************/
702
703static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
704 int data_length)
705{
706 /*
707 * This routine transmits one frame. This routine only accepts
708 * 6-byte Ethernet addresses.
709 */
710 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
wdenk151ab832005-02-24 22:44:16 +0000711 volatile FEC_TBD *pTbd;
wdenk945af8d2003-07-16 21:53:01 +0000712
713#if (DEBUG & 0x20)
714 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200715 tfifo_print(dev->name, fec);
wdenk945af8d2003-07-16 21:53:01 +0000716#endif
717
718 /*
719 * Clear Tx BD ring at first
720 */
721 mpc5xxx_fec_tbd_scrub(fec);
722
723 /*
724 * Check for valid length of data.
725 */
726 if ((data_length > 1500) || (data_length <= 0)) {
727 return -1;
728 }
729
730 /*
731 * Check the number of vacant TxBDs.
732 */
733 if (fec->cleanTbdNum < 1) {
734#if (DEBUG & 0x20)
735 printf("No available TxBDs ...\n");
736#endif
737 return -1;
738 }
739
740 /*
741 * Get the first TxBD to send the mac header
742 */
743 pTbd = &fec->tbdBase[fec->tbdIndex];
744 pTbd->dataLength = data_length;
745 pTbd->dataPointer = (uint32)eth_data;
wdenk77846742003-07-26 08:08:08 +0000746 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
wdenk945af8d2003-07-16 21:53:01 +0000747 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
748
749#if (DEBUG & 0x100)
750 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
751#endif
752
753 /*
754 * Kick the MII i/f
755 */
756 if (fec->xcv_type != SEVENWIRE) {
757 uint16 phyStatus;
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200758 miiphy_read(dev->name, 0, 0x1, &phyStatus);
wdenk945af8d2003-07-16 21:53:01 +0000759 }
760
761 /*
762 * Enable SmartDMA transmit task
763 */
764
765#if (DEBUG & 0x20)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200766 tfifo_print(dev->name, fec);
wdenk945af8d2003-07-16 21:53:01 +0000767#endif
768 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
769#if (DEBUG & 0x20)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200770 tfifo_print(dev->name, fec);
wdenk945af8d2003-07-16 21:53:01 +0000771#endif
772#if (DEBUG & 0x8)
773 printf( "+" );
774#endif
775
776 fec->cleanTbdNum -= 1;
777
778#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
779 printf ("smartDMA ethernet Tx task enabled\n");
780#endif
781 /*
782 * wait until frame is sent .
783 */
784 while (pTbd->status & FEC_TBD_READY) {
785 udelay(10);
786#if (DEBUG & 0x8)
787 printf ("TDB status = %04x\n", pTbd->status);
788#endif
789 }
790
791 return 0;
792}
793
794
795/********************************************************************/
796static int mpc5xxx_fec_recv(struct eth_device *dev)
797{
798 /*
799 * This command pulls one frame from the card
800 */
801 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
wdenk151ab832005-02-24 22:44:16 +0000802 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
wdenk945af8d2003-07-16 21:53:01 +0000803 unsigned long ievent;
wdenk77846742003-07-26 08:08:08 +0000804 int frame_length, len = 0;
805 NBUF *frame;
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200806 uchar buff[FEC_MAX_PKT_SIZE];
wdenk945af8d2003-07-16 21:53:01 +0000807
808#if (DEBUG & 0x1)
809 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
810#endif
811#if (DEBUG & 0x8)
812 printf( "-" );
813#endif
814
815 /*
816 * Check if any critical events have happened
817 */
818 ievent = fec->eth->ievent;
819 fec->eth->ievent = ievent;
820 if (ievent & 0x20060000) {
821 /* BABT, Rx/Tx FIFO errors */
822 mpc5xxx_fec_halt(dev);
823 mpc5xxx_fec_init(dev, NULL);
824 return 0;
825 }
826 if (ievent & 0x80000000) {
827 /* Heartbeat error */
828 fec->eth->x_cntrl |= 0x00000001;
829 }
830 if (ievent & 0x10000000) {
831 /* Graceful stop complete */
832 if (fec->eth->x_cntrl & 0x00000001) {
833 mpc5xxx_fec_halt(dev);
834 fec->eth->x_cntrl &= ~0x00000001;
835 mpc5xxx_fec_init(dev, NULL);
836 }
837 }
838
wdenk77846742003-07-26 08:08:08 +0000839 if (!(pRbd->status & FEC_RBD_EMPTY)) {
840 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
841 ((pRbd->dataLength - 4) > 14)) {
wdenk945af8d2003-07-16 21:53:01 +0000842
wdenk77846742003-07-26 08:08:08 +0000843 /*
844 * Get buffer address and size
845 */
846 frame = (NBUF *)pRbd->dataPointer;
847 frame_length = pRbd->dataLength - 4;
848
849#if (DEBUG & 0x20)
850 {
851 int i;
852 printf("recv data hdr:");
853 for (i = 0; i < 14; i++)
854 printf("%x ", *(frame->head + i));
855 printf("\n");
856 }
wdenk945af8d2003-07-16 21:53:01 +0000857#endif
wdenk77846742003-07-26 08:08:08 +0000858 /*
859 * Fill the buffer and pass it to upper layers
860 */
861 memcpy(buff, frame->head, 14);
862 memcpy(buff + 14, frame->data, frame_length);
863 NetReceive(buff, frame_length);
864 len = frame_length;
865 }
866 /*
867 * Reset buffer descriptor as empty
868 */
869 mpc5xxx_fec_rbd_clean(fec, pRbd);
wdenk945af8d2003-07-16 21:53:01 +0000870 }
wdenk77846742003-07-26 08:08:08 +0000871 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
872 return len;
wdenk945af8d2003-07-16 21:53:01 +0000873}
874
875
876/********************************************************************/
877int mpc5xxx_fec_initialize(bd_t * bis)
878{
879 mpc5xxx_fec_priv *fec;
880 struct eth_device *dev;
wdenk12f34242003-09-02 22:48:03 +0000881 char *tmp, *end;
882 char env_enetaddr[6];
883 int i;
wdenk945af8d2003-07-16 21:53:01 +0000884
885 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
886 dev = (struct eth_device *)malloc(sizeof(*dev));
wdenk12f34242003-09-02 22:48:03 +0000887 memset(dev, 0, sizeof *dev);
wdenk945af8d2003-07-16 21:53:01 +0000888
889 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
890 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
891 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
Bartlomiej Siekafa1df302007-07-11 20:11:07 +0200892#if defined(CONFIG_CANMB) || \
Bartlomiej Sieka86b116b2007-08-03 12:08:16 +0200893 defined(CONFIG_CM5200) || \
Bartlomiej Siekafa1df302007-07-11 20:11:07 +0200894 defined(CONFIG_HMI1001) || \
895 defined(CONFIG_ICECUBE) || \
896 defined(CONFIG_INKA4X0) || \
897 defined(CONFIG_JUPITER) || \
898 defined(CONFIG_MCC200) || \
899 defined(CONFIG_MOTIONPRO) || \
900 defined(CONFIG_O2DNT) || \
901 defined(CONFIG_PM520) || \
902 defined(CONFIG_TOP5200) || \
903 defined(CONFIG_TQM5200) || \
904 defined(CONFIG_UC101) || \
Heiko Schocher6341d9d2008-01-11 15:15:14 +0100905 defined(CONFIG_V38B) || \
906 defined(CONFIG_MUNICES)
wdenkefa329c2004-03-23 20:18:25 +0000907# ifndef CONFIG_FEC_10MBIT
wdenk945af8d2003-07-16 21:53:01 +0000908 fec->xcv_type = MII100;
wdenkefa329c2004-03-23 20:18:25 +0000909# else
wdenka57106f2003-09-16 17:29:31 +0000910 fec->xcv_type = MII10;
wdenkefa329c2004-03-23 20:18:25 +0000911# endif
wdenk6c7a1402004-07-11 19:17:20 +0000912#elif defined(CONFIG_TOTAL5200)
913 fec->xcv_type = SEVENWIRE;
wdenka57106f2003-09-16 17:29:31 +0000914#else
915#error fec->xcv_type not initialized.
wdenk945af8d2003-07-16 21:53:01 +0000916#endif
917
918 dev->priv = (void *)fec;
919 dev->iobase = MPC5XXX_FEC;
920 dev->init = mpc5xxx_fec_init;
921 dev->halt = mpc5xxx_fec_halt;
922 dev->send = mpc5xxx_fec_send;
923 dev->recv = mpc5xxx_fec_recv;
924
wdenk77846742003-07-26 08:08:08 +0000925 sprintf(dev->name, "FEC ETHERNET");
wdenk945af8d2003-07-16 21:53:01 +0000926 eth_register(dev);
927
Jon Loeliger44312832007-07-09 19:06:00 -0500928#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200929 miiphy_register (dev->name,
930 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
931#endif
932
wdenk12f34242003-09-02 22:48:03 +0000933 /*
934 * Try to set the mac address now. The fec mac address is
wdenk42d1f032003-10-15 23:53:47 +0000935 * a garbage after reset. When not using fec for booting
wdenk12f34242003-09-02 22:48:03 +0000936 * the Linux fec driver will try to work with this garbage.
937 */
938 tmp = getenv("ethaddr");
939 if (tmp) {
940 for (i=0; i<6; i++) {
941 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
942 if (tmp)
943 tmp = (*end) ? end+1 : end;
944 }
945 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
946 }
947
wdenk6c1362c2004-05-12 22:18:31 +0000948 mpc5xxx_fec_init_phy(dev, bis);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200949
wdenk945af8d2003-07-16 21:53:01 +0000950 return 1;
951}
952
953/* MII-interface related functions */
954/********************************************************************/
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200955int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
wdenk945af8d2003-07-16 21:53:01 +0000956{
957 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
958 uint32 reg; /* convenient holder for the PHY register */
959 uint32 phy; /* convenient holder for the PHY */
960 int timeout = 0xffff;
961
962 /*
963 * reading from any PHY's register is done by properly
964 * programming the FEC's MII data register.
965 */
966 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
967 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
968
969 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
970
971 /*
972 * wait for the related interrupt
973 */
974 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
975
976 if (timeout == 0) {
977#if (DEBUG & 0x2)
978 printf ("Read MDIO failed...\n");
979#endif
980 return -1;
981 }
982
983 /*
984 * clear mii interrupt bit
985 */
986 eth->ievent = 0x00800000;
987
988 /*
989 * it's now safe to read the PHY's register
990 */
991 *retVal = (uint16) eth->mii_data;
992
993 return 0;
994}
995
996/********************************************************************/
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200997int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
wdenk945af8d2003-07-16 21:53:01 +0000998{
999 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
1000 uint32 reg; /* convenient holder for the PHY register */
1001 uint32 phy; /* convenient holder for the PHY */
1002 int timeout = 0xffff;
1003
1004 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
1005 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
1006
1007 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
1008 FEC_MII_DATA_TA | phy | reg | data);
1009
1010 /*
1011 * wait for the MII interrupt
1012 */
1013 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
1014
1015 if (timeout == 0) {
1016#if (DEBUG & 0x2)
1017 printf ("Write MDIO failed...\n");
1018#endif
1019 return -1;
1020 }
1021
1022 /*
1023 * clear MII interrupt bit
1024 */
1025 eth->ievent = 0x00800000;
1026
1027 return 0;
1028}
1029
1030#if (DEBUG & 0x40)
1031static uint32 local_crc32(char *string, unsigned int crc_value, int len)
1032{
1033 int i;
1034 char c;
1035 unsigned int crc, count;
1036
1037 /*
1038 * crc32 algorithm
1039 */
1040 /*
1041 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1042 */
1043 crc = crc_value;
1044
1045 for (i = len; --i >= 0;) {
1046 c = *string++;
1047 for (count = 0; count < 8; count++) {
1048 if ((c & 0x01) ^ (crc & 0x01)) {
1049 crc >>= 1;
1050 crc = crc ^ 0xedb88320;
1051 } else {
1052 crc >>= 1;
1053 }
1054 c >>= 1;
1055 }
1056 }
1057
1058 /*
1059 * In big endian system, do byte swaping for crc value
1060 */
1061 /**/ return crc;
1062}
1063#endif /* DEBUG */
1064
wdenkcbd8a352004-02-24 02:00:03 +00001065#endif /* CONFIG_MPC5xxx_FEC */