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wdenk7a8e9bed2003-05-31 18:35:21 +00001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
Graeme Russe17ee152009-02-24 21:14:56 +110031#define CONFIG_SKIP_RELOCATE_UBOOT
32
wdenk7a8e9bed2003-05-31 18:35:21 +000033/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_X86 1 /* This is a X86 CPU */
Graeme Russ6d83e3a2009-02-24 21:12:20 +110039#define CONFIG_SYS_SC520 1 /* Include support for AMD SC520 */
Graeme Russ91ee4e12009-08-23 12:59:54 +100040#define CONFIG_SYS_SC520_SSI
wdenk7a8e9bed2003-05-31 18:35:21 +000041
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6 /* 6T */
43#define CONFIG_SYS_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
44#define CONFIG_SYS_SDRAM_RAS_CAS_DELAY 3 /* 3T */
wdenk7a8e9bed2003-05-31 18:35:21 +000045
46/* define at most one of these */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
48#define CONFIG_SYS_SDRAM_CAS_LATENCY_3T
wdenk7a8e9bed2003-05-31 18:35:21 +000049
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
Graeme Russ6d83e3a2009-02-24 21:12:20 +110051#undef CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
52#undef CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
53#define CONFIG_SYS_GENERIC_TIMER 1 /* use the i8254 PIT timers */
54#undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
Graeme Russabf0cd32009-02-24 21:13:40 +110055#define CONFIG_SYS_PCAT_INTERRUPTS
56#define CONFIG_SYS_NUM_IRQS 16
wdenk7a8e9bed2003-05-31 18:35:21 +000057
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
wdenk7a8e9bed2003-05-31 18:35:21 +000059
60#define CONFIG_SHOW_BOOT_PROGRESS 1
61#define CONFIG_LAST_STAGE_INIT 1
62
63/*
64 * Size of malloc() pool
65 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020066#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)
wdenk7a8e9bed2003-05-31 18:35:21 +000067
68
69#define CONFIG_BAUDRATE 9600
70
wdenk7a8e9bed2003-05-31 18:35:21 +000071
Jon Loeliger46da1e92007-07-04 22:33:30 -050072/*
Jon Loeliger079a1362007-07-10 10:12:10 -050073 * BOOTP options
74 */
75#define CONFIG_BOOTP_BOOTFILESIZE
76#define CONFIG_BOOTP_BOOTPATH
77#define CONFIG_BOOTP_GATEWAY
78#define CONFIG_BOOTP_HOSTNAME
79
80
81/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050082 * Command line configuration.
83 */
84#include <config_cmd_default.h>
85
86#define CONFIG_CMD_PCI
87#define CONFIG_CMD_JFFS2
88#define CONFIG_CMD_IDE
89#define CONFIG_CMD_NET
90#define CONFIG_CMD_PCMCIA
91#define CONFIG_CMD_EEPROM
92
wdenk7a8e9bed2003-05-31 18:35:21 +000093
94#define CONFIG_BOOTDELAY 15
Wolfgang Denk53677ef2008-05-20 16:00:29 +020095#define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 " \
96 "mtdparts=phys:7936k(root),256k(uboot) "
97#define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf " \
98 "console=ttyS0,9600 " \
99 "mtdparts=phys:7808k(root),128k(env),256k(uboot);" \
100 "bootp;bootm"
wdenk7a8e9bed2003-05-31 18:35:21 +0000101
Jon Loeliger46da1e92007-07-04 22:33:30 -0500102#if defined(CONFIG_CMD_KGDB)
wdenk7a8e9bed2003-05-31 18:35:21 +0000103#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
104#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
105#endif
106
107
108/*
109 * Miscellaneous configurable options
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_LONGHELP /* undef to save memory */
112#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
113#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7a8e9bed2003-05-31 18:35:21 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
119#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
wdenk7a8e9bed2003-05-31 18:35:21 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk7a8e9bed2003-05-31 18:35:21 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */
wdenk7a8e9bed2003-05-31 18:35:21 +0000124
125 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk7a8e9bed2003-05-31 18:35:21 +0000127
128
129/*-----------------------------------------------------------------------
130 * Physical Memory Map
131 */
132#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */
133
134/*-----------------------------------------------------------------------
135 * FLASH and environment organization
136 */
137
138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
140#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
wdenk7a8e9bed2003-05-31 18:35:21 +0000141
142/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
144#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk7a8e9bed2003-05-31 18:35:21 +0000145
146
147#define CONFIG_SPI_EEPROM /* SPI EEPROMs such as AT25010 or AT25640 */
148#define CONFIG_MW_EEPROM /* MicroWire EEPROMS such as AT93LC46 */
Michal Simek18c8a282008-07-11 15:11:57 +0200149#define CONFIG_DTT_DS1722 /* Dallas DS1722 SPI Temperature probe */
stroese53cf9432003-06-05 15:39:44 +0000150
wdenk7a8e9bed2003-05-31 18:35:21 +0000151
152/* allow to overwrite serial and ethaddr */
153#define CONFIG_ENV_OVERWRITE
154
155
156#if 0
157/* Environment in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200158#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200159# define CONFIG_ENV_ADDR (0x387a0000) /* Addr of Environment Sector */
160# define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector (or 0x10000) */
161# define CONFIG_ENV_OFFSET 0
wdenk7a8e9bed2003-05-31 18:35:21 +0000162
163#else
164/* Environment in EEPROM */
165
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200166# define CONFIG_ENV_IS_IN_EEPROM 1
wdenk7a8e9bed2003-05-31 18:35:21 +0000167# define CONFIG_SPI
168# define CONFIG_SPI_X 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200169# define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment EEPROM */
170# define CONFIG_ENV_OFFSET 0x1c00
wdenk7a8e9bed2003-05-31 18:35:21 +0000171
172#endif
173
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200174/*
175 * JFFS2 partitions
176 *
177 */
178/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100179#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200180#define CONFIG_JFFS2_DEV "nor0"
181#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
182#define CONFIG_JFFS2_PART_OFFSET 0x00000000
183
184/* mtdparts command line support */
185/* Note: fake mtd_id used, no linux mtd map file */
186/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100187#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200188#define MTDIDS_DEFAULT "nor0=sc520_spunk-0"
189#define MTDPARTS_DEFAULT "mtdparts=sc520_spunk-0:-(jffs2)"
190*/
wdenk7a8e9bed2003-05-31 18:35:21 +0000191
192/*-----------------------------------------------------------------------
193 * Device drivers
194 */
195#define CONFIG_NET_MULTI /* Multi ethernet cards support */
196#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk7a8e9bed2003-05-31 18:35:21 +0000198
199/************************************************************
200 * IDE/ATA stuff
201 ************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
203#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
204#define CONFIG_SYS_ATA_BASE_ADDR 0
205#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0 /* ide0 offset */
206#define CONFIG_SYS_ATA_IDE1_OFFSET 0xe000 /* ide1 offset */
207#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
208#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
209#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenk7a8e9bed2003-05-31 18:35:21 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FIRST_PCMCIA_BUS 1
wdenk7a8e9bed2003-05-31 18:35:21 +0000212
213#undef CONFIG_IDE_LED /* no led for ide supported */
214#undef CONFIG_IDE_RESET /* reset for ide unsupported... */
215#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
216
217#define CONFIG_IDE_TI_CARDBUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_PCMCIA_CIS_WIN 0x27f00000
219#define CONFIG_SYS_PCMCIA_CIS_WIN_SIZE 0x00100000
220#define CONFIG_SYS_PCMCIA_IO_WIN 0xe000
221#define CONFIG_SYS_PCMCIA_IO_WIN_SIZE 16
Graeme Russ91ee4e12009-08-23 12:59:54 +1000222#define CONFIG_PCMCIA_SLOT_A /* TODO: Check this */
wdenk7a8e9bed2003-05-31 18:35:21 +0000223
224/************************************************************
225 * DISK Partition support
226 ************************************************************/
227#define CONFIG_DOS_PARTITION
228#define CONFIG_MAC_PARTITION
229#define CONFIG_ISO_PARTITION /* Experimental */
230
231
wdenk7a8e9bed2003-05-31 18:35:21 +0000232/************************************************************
233 * RTC
234 ***********************************************************/
235#define CONFIG_RTC_MC146818
236#undef CONFIG_WATCHDOG /* watchdog disabled */
237
238/*
239 * PCI stuff
240 */
241#define CONFIG_PCI /* include pci support */
242#define CONFIG_PCI_PNP /* pci plug-and-play */
243#define CONFIG_PCI_SCAN_SHOW
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FIRST_PCI_IRQ 9
246#define CONFIG_SYS_SECOND_PCI_IRQ 10
247#define CONFIG_SYS_THIRD_PCI_IRQ 11
248#define CONFIG_SYS_FORTH_PCI_IRQ 12
wdenk7a8e9bed2003-05-31 18:35:21 +0000249
wdenk7a8e9bed2003-05-31 18:35:21 +0000250#endif /* __CONFIG_H */