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wdenk1cb8e982003-03-06 21:55:29 +00001/*
wdenk531716e2003-09-13 19:01:12 +00002 * (C) Copyright 2002, 2003
wdenk1cb8e982003-03-06 21:55:29 +00003 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <gj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * Configuation settings for the MPL VCMA9 board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
wdenk1cb8e982003-03-06 21:55:29 +000033 * High Level Configuration Options
34 * (easy to change)
35 */
36#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
37#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
38#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
39
40/* input clock of PLL */
41#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
42
43#define USE_920T_MMU 1
44#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
45
Wolfgang Denk53677ef2008-05-20 16:00:29 +020046#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenk1cb8e982003-03-06 21:55:29 +000047#define CONFIG_SETUP_MEMORY_TAGS 1
48#define CONFIG_INITRD_TAG 1
49
wdenk1cb8e982003-03-06 21:55:29 +000050
Jon Loeligera5562902007-07-08 15:31:57 -050051/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050052 * BOOTP options
53 */
54#define CONFIG_BOOTP_BOOTFILESIZE
55#define CONFIG_BOOTP_BOOTPATH
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58
59
60/*
Jon Loeligera5562902007-07-08 15:31:57 -050061 * Command line configuration.
62 */
63#include <config_cmd_default.h>
64
65#define CONFIG_CMD_CACHE
66#define CONFIG_CMD_EEPROM
67#define CONFIG_CMD_I2C
68#define CONFIG_CMD_USB
69#define CONFIG_CMD_REGINFO
70#define CONFIG_CMD_FAT
71#define CONFIG_CMD_DATE
72#define CONFIG_CMD_ELF
73#define CONFIG_CMD_DHCP
74#define CONFIG_CMD_PING
75#define CONFIG_CMD_BSP
76
wdenk1cb8e982003-03-06 21:55:29 +000077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_HUSH_PARSER
79#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk1cb8e982003-03-06 21:55:29 +000080/***********************************************************
81 * I2C stuff:
82 * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
83 * address 0x50 with 16bit addressing
84 ***********************************************************/
85#define CONFIG_HARD_I2C /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
87#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
wdenk1cb8e982003-03-06 21:55:29 +000088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
90#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020091#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020092#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */
93#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */
wdenk1cb8e982003-03-06 21:55:29 +000094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
96#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */
97#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenk1cb8e982003-03-06 21:55:29 +000098
99/*
100 * Size of malloc() pool
101 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200102/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk1cb8e982003-03-06 21:55:29 +0000104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
106#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */
wdenk1cb8e982003-03-06 21:55:29 +0000107
108/*
109 * Hardware drivers
110 */
111#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
112#define CS8900_BASE 0x20000300
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200113#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
wdenk1cb8e982003-03-06 21:55:29 +0000114
115#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */
116
117/*
118 * select serial console configuration
119 */
120#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
121
wdenk48b42612003-06-19 23:01:32 +0000122/************************************************************
123 * USB support
124 ************************************************************/
wdenka2663ea2003-12-07 18:32:37 +0000125#define CONFIG_USB_OHCI 1
126#define CONFIG_USB_KEYBOARD 1
127#define CONFIG_USB_STORAGE 1
128#define CONFIG_DOS_PARTITION 1
wdenk48b42612003-06-19 23:01:32 +0000129
130/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */
wdenk48b42612003-06-19 23:01:32 +0000132
133/************************************************************
134 * RTC
135 ************************************************************/
136#define CONFIG_RTC_S3C24X0 1
137
138
wdenk1cb8e982003-03-06 21:55:29 +0000139/* allow to overwrite serial and ethaddr */
140#define CONFIG_ENV_OVERWRITE
141
142#define CONFIG_BAUDRATE 9600
143
wdenka2663ea2003-12-07 18:32:37 +0000144#define CONFIG_BOOTDELAY 5
145/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
Wolfgang Denk2893ecb2005-08-14 01:52:14 +0200146/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200147#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
wdenka2663ea2003-12-07 18:32:37 +0000148
wdenk1cb8e982003-03-06 21:55:29 +0000149#define CONFIG_NETMASK 255.255.255.0
150#define CONFIG_IPADDR 10.0.0.110
151#define CONFIG_SERVERIP 10.0.0.1
152
Jon Loeligera5562902007-07-08 15:31:57 -0500153#if defined(CONFIG_CMD_KGDB)
wdenk1cb8e982003-03-06 21:55:29 +0000154#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
155/* what's this ? it's not used anywhere */
156#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
157#endif
158
159/*
160 * Miscellaneous configurable options
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_LONGHELP /* undef to save memory */
163#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */
164#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
165#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
166#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
167#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk1cb8e982003-03-06 21:55:29 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
170#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */
wdenk531716e2003-09-13 19:01:12 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_ALT_MEMTEST
173#define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */
wdenk1cb8e982003-03-06 21:55:29 +0000174
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
wdenk1cb8e982003-03-06 21:55:29 +0000177
178/* we configure PWM Timer 4 to 1us ~ 1MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179/*#define CONFIG_SYS_HZ 1000000 */
180#define CONFIG_SYS_HZ 1562500
wdenk1cb8e982003-03-06 21:55:29 +0000181
182/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk1cb8e982003-03-06 21:55:29 +0000184
wdenka2663ea2003-12-07 18:32:37 +0000185/* support BZIP2 compression */
186#define CONFIG_BZIP2 1
187
wdenk48b42612003-06-19 23:01:32 +0000188/************************************************************
189 * Ident
190 ************************************************************/
191/*#define VERSION_TAG "released"*/
192#define VERSION_TAG "unstable"
193#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
194
wdenk1cb8e982003-03-06 21:55:29 +0000195/*-----------------------------------------------------------------------
196 * Stack sizes
197 *
198 * The stack sizes are set up in start.S using the settings below
199 */
200#define CONFIG_STACKSIZE (128*1024) /* regular stack */
201#ifdef CONFIG_USE_IRQ
202#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
203#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
204#endif
205
206/*-----------------------------------------------------------------------
207 * Physical Memory Map
208 */
209#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
210#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
wdenk1cb8e982003-03-06 21:55:29 +0000211#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk1cb8e982003-03-06 21:55:29 +0000214
215/*-----------------------------------------------------------------------
216 * FLASH and environment organization
217 */
218
219#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
220#if 0
221#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
222#endif
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk1cb8e982003-03-06 21:55:29 +0000225#ifdef CONFIG_AMD_LV800
226#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
228#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
wdenk1cb8e982003-03-06 21:55:29 +0000229#endif
230#ifdef CONFIG_AMD_LV400
231#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
233#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
wdenk1cb8e982003-03-06 21:55:29 +0000234#endif
235
236/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
238#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk1cb8e982003-03-06 21:55:29 +0000239
240#if 0
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200241#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200242#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
wdenk1cb8e982003-03-06 21:55:29 +0000243#endif
244
wdenk48b42612003-06-19 23:01:32 +0000245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_JFFS2_FIRST_BANK 0
247#define CONFIG_SYS_JFFS2_NUM_BANKS 1
wdenk48b42612003-06-19 23:01:32 +0000248
249#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
250
251/*-----------------------------------------------------------------------
252 * NAND flash settings
253 */
Jon Loeligera5562902007-07-08 15:31:57 -0500254#if defined(CONFIG_CMD_NAND)
wdenk48b42612003-06-19 23:01:32 +0000255
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +0200256#define CONFIG_NAND_LEGACY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
wdenk48b42612003-06-19 23:01:32 +0000258#define SECTORSIZE 512
259
260#define ADDR_COLUMN 1
261#define ADDR_PAGE 2
262#define ADDR_COLUMN_PAGE 3
263
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200264#define NAND_ChipID_UNKNOWN 0x00
wdenk48b42612003-06-19 23:01:32 +0000265#define NAND_MAX_FLOORS 1
wdenk48b42612003-06-19 23:01:32 +0000266
267#define NAND_WAIT_READY(nand) NF_WaitRB()
268
269#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
270#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
271
272
273#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
274#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
275#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
276#define WRITE_NAND(d, adr) NF_Write(d)
277#define READ_NAND(adr) NF_Read()
278/* the following functions are NOP's because S3C24X0 handles this in hardware */
279#define NAND_CTL_CLRALE(nandptr)
280#define NAND_CTL_SETALE(nandptr)
281#define NAND_CTL_CLRCLE(nandptr)
282#define NAND_CTL_SETCLE(nandptr)
283
284#define CONFIG_MTD_NAND_VERIFY_WRITE 1
285#define CONFIG_MTD_NAND_ECC_JFFS2 1
286
Jon Loeligera5562902007-07-08 15:31:57 -0500287#endif
wdenk1cb8e982003-03-06 21:55:29 +0000288
289#endif /* __CONFIG_H */