blob: 40e95464316de0c3b2cb89d500d1ee58d2a0ea2c [file] [log] [blame]
Kim Phillips1c274c42007-07-25 19:25:33 -05001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published
6 * by the Free Software Foundation.
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Kim Phillips1c274c42007-07-25 19:25:33 -050012/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
16#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050017#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050018#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
Kim Phillips1c274c42007-07-25 19:25:33 -050019
Wolfgang Denk2ae18242010-10-06 09:05:45 +020020#define CONFIG_SYS_TEXT_BASE 0xFE000000
21
Kim Phillips1c274c42007-07-25 19:25:33 -050022#define CONFIG_PCI 1
Kim Phillips1c274c42007-07-25 19:25:33 -050023
24/*
25 * System Clock Setup
26 */
27#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
28
29#ifndef CONFIG_SYS_CLK_FREQ
30#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
31#endif
32
33/*
34 * Hardware Reset Configuration Word
35 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_HRCW_LOW (\
Kim Phillips1c274c42007-07-25 19:25:33 -050037 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
38 HRCWL_DDR_TO_SCB_CLK_2X1 |\
39 HRCWL_VCO_1X2 |\
40 HRCWL_CSB_TO_CLKIN_2X1 |\
41 HRCWL_CORE_TO_CSB_2_5X1 |\
42 HRCWL_CE_PLL_VCO_DIV_2 |\
43 HRCWL_CE_PLL_DIV_1X1 |\
44 HRCWL_CE_TO_PLL_1X3)
45
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips1c274c42007-07-25 19:25:33 -050047 HRCWH_PCI_HOST |\
48 HRCWH_PCI1_ARBITER_ENABLE |\
49 HRCWH_CORE_ENABLE |\
50 HRCWH_FROM_0X00000100 |\
51 HRCWH_BOOTSEQ_DISABLE |\
52 HRCWH_SW_WATCHDOG_DISABLE |\
53 HRCWH_ROM_LOC_LOCAL_16BIT |\
54 HRCWH_BIG_ENDIAN |\
55 HRCWH_LALE_NORMAL)
56
57/*
58 * System IO Config
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips1c274c42007-07-25 19:25:33 -050061
Kim Phillips1c274c42007-07-25 19:25:33 -050062/*
63 * IMMR new address
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_IMMR 0xE0000000
Kim Phillips1c274c42007-07-25 19:25:33 -050066
67/*
Michael Barkowski5bbeea82008-03-20 13:15:34 -040068 * System performance
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050071#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
72/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
73#define CONFIG_SYS_SPCR_OPT 1
Michael Barkowski5bbeea82008-03-20 13:15:34 -040074
75/*
Kim Phillips1c274c42007-07-25 19:25:33 -050076 * DDR Setup
77 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050078#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
79#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Kim Phillips1c274c42007-07-25 19:25:33 -050081
82#undef CONFIG_SPD_EEPROM
83#if defined(CONFIG_SPD_EEPROM)
84/* Determine DDR configuration from I2C interface
85 */
86#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
87#else
88/* Manually set up DDR parameters
89 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050090#define CONFIG_SYS_DDR_SIZE 64 /* MB */
91#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger4dde49d2011-10-11 23:57:12 -050092 | CSCONFIG_ROW_BIT_13 \
93 | CSCONFIG_COL_BIT_9)
Michael Barkowski5bbeea82008-03-20 13:15:34 -040094 /* 0x80010101 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -050095#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
96 | (0 << TIMING_CFG0_WRT_SHIFT) \
97 | (0 << TIMING_CFG0_RRT_SHIFT) \
98 | (0 << TIMING_CFG0_WWT_SHIFT) \
99 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
100 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
101 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
102 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Michael Barkowskifc549c82008-03-20 13:15:28 -0400103 /* 0x00220802 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500104#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
105 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
106 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
107 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
108 | (3 << TIMING_CFG1_REFREC_SHIFT) \
109 | (2 << TIMING_CFG1_WRREC_SHIFT) \
110 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
111 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400112 /* 0x26253222 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500113#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
114 | (31 << TIMING_CFG2_CPO_SHIFT) \
115 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
116 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
117 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
118 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
119 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400120 /* 0x1f9048c7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_DDR_TIMING_3 0x00000000
122#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Michael Barkowskifc549c82008-03-20 13:15:28 -0400123 /* 0x02000000 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500124#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
125 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Michael Barkowski5bbeea82008-03-20 13:15:34 -0400126 /* 0x44480232 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500127#define CONFIG_SYS_DDR_MODE2 0x8000c000
128#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
129 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Michael Barkowskifc549c82008-03-20 13:15:28 -0400130 /* 0x03200064 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500132#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Michael Barkowskifc549c82008-03-20 13:15:28 -0400133 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500134 | SDRAM_CFG_32_BE)
Michael Barkowskifc549c82008-03-20 13:15:28 -0400135 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Kim Phillips1c274c42007-07-25 19:25:33 -0500137#endif
138
139/*
140 * Memory test
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
143#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
144#define CONFIG_SYS_MEMTEST_END 0x03f00000
Kim Phillips1c274c42007-07-25 19:25:33 -0500145
146/*
147 * The reserved memory
148 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200149#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips1c274c42007-07-25 19:25:33 -0500150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
152#define CONFIG_SYS_RAMBOOT
Kim Phillips1c274c42007-07-25 19:25:33 -0500153#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#undef CONFIG_SYS_RAMBOOT
Kim Phillips1c274c42007-07-25 19:25:33 -0500155#endif
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500158#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
159#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Kim Phillips1c274c42007-07-25 19:25:33 -0500160
161/*
162 * Initial RAM Base Address Setup
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500165#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
166#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
167#define CONFIG_SYS_GBL_DATA_OFFSET \
168 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips1c274c42007-07-25 19:25:33 -0500169
170/*
171 * Local Bus Configuration & Clock Setup
172 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500173#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
174#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_LBC_LBCR 0x00000000
Kim Phillips1c274c42007-07-25 19:25:33 -0500176
177/*
178 * FLASH on the Local Bus
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200181#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500182#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500184#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Kim Phillips1c274c42007-07-25 19:25:33 -0500185
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500186 /* Window base at flash base */
187#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500188#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Kim Phillips1c274c42007-07-25 19:25:33 -0500189
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500190#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500191 | BR_PS_16 /* 16 bit port */ \
192 | BR_MS_GPCM /* MSEL = GPCM */ \
193 | BR_V) /* valid */
194#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
195 | OR_GPCM_XAM \
196 | OR_GPCM_CSNT \
197 | OR_GPCM_ACS_DIV2 \
198 | OR_GPCM_XACS \
199 | OR_GPCM_SCY_15 \
200 | OR_GPCM_TRLX_SET \
201 | OR_GPCM_EHTR_SET \
202 | OR_GPCM_EAD)
203 /* 0xFE006FF7 */
Kim Phillips1c274c42007-07-25 19:25:33 -0500204
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500205#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
206#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Kim Phillips1c274c42007-07-25 19:25:33 -0500207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#undef CONFIG_SYS_FLASH_CHECKSUM
Kim Phillips1c274c42007-07-25 19:25:33 -0500209
210/*
Kim Phillips1c274c42007-07-25 19:25:33 -0500211 * Serial Port
212 */
213#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_NS16550
215#define CONFIG_SYS_NS16550_SERIAL
216#define CONFIG_SYS_NS16550_REG_SIZE 1
217#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips1c274c42007-07-25 19:25:33 -0500218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500220 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Kim Phillips1c274c42007-07-25 19:25:33 -0500221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
223#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips1c274c42007-07-25 19:25:33 -0500224
225#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500226#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillips1c274c42007-07-25 19:25:33 -0500227/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_HUSH_PARSER
229#ifdef CONFIG_SYS_HUSH_PARSER
230#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kim Phillips1c274c42007-07-25 19:25:33 -0500231#endif
232
233/* pass open firmware flat tree */
234#define CONFIG_OF_LIBFDT 1
235#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600236#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillips1c274c42007-07-25 19:25:33 -0500237
238/* I2C */
239#define CONFIG_HARD_I2C /* I2C with hardware support */
240#undef CONFIG_SOFT_I2C /* I2C bit-banged */
241#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
243#define CONFIG_SYS_I2C_SLAVE 0x7F
244#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
245#define CONFIG_SYS_I2C_OFFSET 0x3000
Kim Phillips1c274c42007-07-25 19:25:33 -0500246
247/*
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400248 * Config on-board EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
251#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
252#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
253#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Kim Phillips1c274c42007-07-25 19:25:33 -0500254
255/*
256 * General PCI
257 * Addresses are mapped 1-1.
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
260#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
261#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
262#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
263#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
264#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
265#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
266#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
267#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
Kim Phillips1c274c42007-07-25 19:25:33 -0500268
269#ifdef CONFIG_PCI
Michael Barkowski8f325cf2008-03-28 15:15:38 -0400270#define CONFIG_PCI_SKIP_HOST_BRIDGE
Kim Phillips1c274c42007-07-25 19:25:33 -0500271#define CONFIG_PCI_PNP /* do pci plug-and-play */
272
273#undef CONFIG_EEPRO100
274#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Kim Phillips1c274c42007-07-25 19:25:33 -0500276
277#endif /* CONFIG_PCI */
278
Kim Phillips1c274c42007-07-25 19:25:33 -0500279/*
280 * QE UEC ethernet configuration
281 */
282#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500283#define CONFIG_ETHPRIME "UEC0"
Kim Phillips1c274c42007-07-25 19:25:33 -0500284
285#define CONFIG_UEC_ETH1 /* ETH3 */
286
287#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
289#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
290#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
291#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
292#define CONFIG_SYS_UEC1_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500293#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100294#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Kim Phillips1c274c42007-07-25 19:25:33 -0500295#endif
296
297#define CONFIG_UEC_ETH2 /* ETH4 */
298
299#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
301#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
302#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
303#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
304#define CONFIG_SYS_UEC2_PHY_ADDR 0
Andy Fleming865ff852011-04-13 00:37:12 -0500305#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100306#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Kim Phillips1c274c42007-07-25 19:25:33 -0500307#endif
308
309/*
310 * Environment
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200313 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500314 #define CONFIG_ENV_ADDR \
315 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200316 #define CONFIG_ENV_SECT_SIZE 0x20000
317 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500318#else
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500319 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200320 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200322 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips1c274c42007-07-25 19:25:33 -0500323#endif
324
325#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips1c274c42007-07-25 19:25:33 -0500327
328/*
329 * BOOTP options
330 */
331#define CONFIG_BOOTP_BOOTFILESIZE
332#define CONFIG_BOOTP_BOOTPATH
333#define CONFIG_BOOTP_GATEWAY
334#define CONFIG_BOOTP_HOSTNAME
335
336/*
337 * Command line configuration.
338 */
339#include <config_cmd_default.h>
340
341#define CONFIG_CMD_PING
342#define CONFIG_CMD_I2C
Michael Barkowski0fa7a1b2008-03-20 13:15:39 -0400343#define CONFIG_CMD_EEPROM
Kim Phillips1c274c42007-07-25 19:25:33 -0500344#define CONFIG_CMD_ASKENV
345
346#if defined(CONFIG_PCI)
347 #define CONFIG_CMD_PCI
348#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500350 #undef CONFIG_CMD_SAVEENV
Kim Phillips1c274c42007-07-25 19:25:33 -0500351 #undef CONFIG_CMD_LOADS
352#endif
353
354#undef CONFIG_WATCHDOG /* watchdog disabled */
355
356/*
357 * Miscellaneous configurable options
358 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500359#define CONFIG_SYS_LONGHELP /* undef to save memory */
360#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
361#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kim Phillips1c274c42007-07-25 19:25:33 -0500362
363#if (CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500365#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kim Phillips1c274c42007-07-25 19:25:33 -0500367#endif
368
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500369 /* Print Buffer Size */
370#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500372 /* Boot Argument Buffer Size */
373#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
374#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kim Phillips1c274c42007-07-25 19:25:33 -0500375
376/*
377 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700378 * have to be in the first 256 MB of memory, since this is
Kim Phillips1c274c42007-07-25 19:25:33 -0500379 * the maximum mapped by the Linux kernel during initialization.
380 */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500381 /* Initial Memory map for Linux */
382#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Kim Phillips1c274c42007-07-25 19:25:33 -0500383
384/*
385 * Core HID Setup
386 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500387#define CONFIG_SYS_HID0_INIT 0x000000000
388#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
389 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_HID2 HID2_HBE
Kim Phillips1c274c42007-07-25 19:25:33 -0500391
392/*
Kim Phillips1c274c42007-07-25 19:25:33 -0500393 * MMU Setup
394 */
Becky Bruce31d82672008-05-08 19:02:12 -0500395#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Kim Phillips1c274c42007-07-25 19:25:33 -0500396
397/* DDR: cache cacheable */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500398#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500399 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500400 | BATL_MEMCOHERENCE)
401#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
402 | BATU_BL_256M \
403 | BATU_VS \
404 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
406#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Kim Phillips1c274c42007-07-25 19:25:33 -0500407
408/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500409#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500410 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500411 | BATL_CACHEINHIBIT \
412 | BATL_GUARDEDSTORAGE)
413#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
414 | BATU_BL_4M \
415 | BATU_VS \
416 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
418#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Kim Phillips1c274c42007-07-25 19:25:33 -0500419
420/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500421#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500422 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500423 | BATL_MEMCOHERENCE)
424#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
425 | BATU_BL_32M \
426 | BATU_VS \
427 | BATU_VP)
428#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500429 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500430 | BATL_CACHEINHIBIT \
431 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Kim Phillips1c274c42007-07-25 19:25:33 -0500433
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_IBAT3L (0)
435#define CONFIG_SYS_IBAT3U (0)
436#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
437#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Kim Phillips1c274c42007-07-25 19:25:33 -0500438
439/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500440#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500441#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
442 | BATU_BL_128K \
443 | BATU_VS \
444 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
446#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Kim Phillips1c274c42007-07-25 19:25:33 -0500447
448#ifdef CONFIG_PCI
449/* PCI MEM space: cacheable */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500450#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500451 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500452 | BATL_MEMCOHERENCE)
453#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
454 | BATU_BL_256M \
455 | BATU_VS \
456 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
458#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Kim Phillips1c274c42007-07-25 19:25:33 -0500459/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500460#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500461 | BATL_PP_RW \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500462 | BATL_CACHEINHIBIT \
463 | BATL_GUARDEDSTORAGE)
464#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
465 | BATU_BL_256M \
466 | BATU_VS \
467 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
469#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips1c274c42007-07-25 19:25:33 -0500470#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_IBAT5L (0)
472#define CONFIG_SYS_IBAT5U (0)
473#define CONFIG_SYS_IBAT6L (0)
474#define CONFIG_SYS_IBAT6U (0)
475#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
476#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
477#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
478#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips1c274c42007-07-25 19:25:33 -0500479#endif
480
481/* Nothing in BAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_IBAT7L (0)
483#define CONFIG_SYS_IBAT7U (0)
484#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
485#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips1c274c42007-07-25 19:25:33 -0500486
Kim Phillips1c274c42007-07-25 19:25:33 -0500487#if (CONFIG_CMD_KGDB)
488#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
489#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
490#endif
491
492/*
493 * Environment Configuration
494 */
495#define CONFIG_ENV_OVERWRITE
496
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500497#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
498#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
Kim Phillips1c274c42007-07-25 19:25:33 -0500499
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500500/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
501 * (see CONFIG_SYS_I2C_EEPROM) */
502 /* MAC address offset in I2C EEPROM */
503#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
Michael Barkowski5b2793a2008-03-27 14:34:43 -0400504
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500505#define CONFIG_NETDEV "eth1"
Kim Phillips1c274c42007-07-25 19:25:33 -0500506
507#define CONFIG_HOSTNAME mpc8323erdb
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000508#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000509#define CONFIG_BOOTFILE "uImage"
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500510 /* U-Boot image on TFTP server */
511#define CONFIG_UBOOTPATH "u-boot.bin"
512#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
513#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
Kim Phillips1c274c42007-07-25 19:25:33 -0500514
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500515 /* default location for tftp and bootm */
516#define CONFIG_LOADADDR 800000
Kim Phillips7fd0bea2008-09-24 08:46:25 -0500517#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Kim Phillips1c274c42007-07-25 19:25:33 -0500518#define CONFIG_BAUDRATE 115200
519
520#define XMK_STR(x) #x
521#define MK_STR(x) XMK_STR(x)
522
523#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500524 "netdev=" CONFIG_NETDEV "\0" \
525 "uboot=" CONFIG_UBOOTPATH "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500526 "tftpflash=tftp $loadaddr $uboot;" \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500527 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
528 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
529 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
530 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
531 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
Kim Phillips79f516b2009-08-21 16:34:38 -0500532 "fdtaddr=780000\0" \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500533 "fdtfile=" CONFIG_FDTFILE "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500534 "ramdiskaddr=1000000\0" \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500535 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
Kim Phillips1c274c42007-07-25 19:25:33 -0500536 "console=ttyS0\0" \
537 "setbootargs=setenv bootargs " \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500538 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
Kim Phillips1c274c42007-07-25 19:25:33 -0500539 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger4dde49d2011-10-11 23:57:12 -0500540 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
541 "$netdev:off "\
Kim Phillips1c274c42007-07-25 19:25:33 -0500542 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
543
544#define CONFIG_NFSBOOTCOMMAND \
545 "setenv rootdev /dev/nfs;" \
546 "run setbootargs;" \
547 "run setipargs;" \
548 "tftp $loadaddr $bootfile;" \
549 "tftp $fdtaddr $fdtfile;" \
550 "bootm $loadaddr - $fdtaddr"
551
552#define CONFIG_RAMBOOTCOMMAND \
553 "setenv rootdev /dev/ram;" \
554 "run setbootargs;" \
555 "tftp $ramdiskaddr $ramdiskfile;" \
556 "tftp $loadaddr $bootfile;" \
557 "tftp $fdtaddr $fdtfile;" \
558 "bootm $loadaddr $ramdiskaddr $fdtaddr"
559
560#undef MK_STR
561#undef XMK_STR
562
563#endif /* __CONFIG_H */