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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Bin Meng9c7dea62015-05-25 22:35:04 +08002/*
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
Bin Meng9c7dea62015-05-25 22:35:04 +08004 */
5
6#ifndef _ARCH_IRQ_H_
7#define _ARCH_IRQ_H_
8
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11/**
12 * Intel interrupt router configuration mechanism
13 *
14 * There are two known ways of Intel interrupt router configuration mechanism
Wolfgang Wallner49113582020-07-21 13:01:45 +020015 * so far. On most cases, the IRQ routing configuration is controlled by PCI
16 * configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0).
Bin Meng9c7dea62015-05-25 22:35:04 +080017 * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
18 * in the IBASE register block where IBASE is memory-mapped.
19 */
20enum pirq_config {
21 PIRQ_VIA_PCI,
22 PIRQ_VIA_IBASE
23};
24
Bin Meng51050ff2018-06-12 01:26:46 -070025struct pirq_regmap {
26 int link;
27 int offset;
28};
29
Bin Meng9c7dea62015-05-25 22:35:04 +080030/**
31 * Intel interrupt router control block
32 *
33 * Its members' value will be filled in based on device tree's input.
34 *
35 * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
36 * @link_base: link value base number
Bin Mengdcec5d52018-06-12 01:26:45 -070037 * @link_num: number of PIRQ links supported
Bin Meng51050ff2018-06-12 01:26:46 -070038 * @has_regmap: has mapping table between PIRQ link and routing register offset
Wolfgang Wallner49113582020-07-21 13:01:45 +020039 * @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means
Bin Meng9c7dea62015-05-25 22:35:04 +080040 * IRQ N is available to be routed
41 * @lb_bdf: irq router's PCI bus/device/function number encoding
42 * @ibase: IBASE register block base address
Bin Mengd4e61f52016-05-07 07:46:14 -070043 * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
44 * @actl_addr: ACTL register offset
Bin Meng9c7dea62015-05-25 22:35:04 +080045 */
46struct irq_router {
47 int config;
48 u32 link_base;
Bin Mengdcec5d52018-06-12 01:26:45 -070049 int link_num;
Bin Meng51050ff2018-06-12 01:26:46 -070050 bool has_regmap;
51 struct pirq_regmap *regmap;
Bin Meng9c7dea62015-05-25 22:35:04 +080052 u16 irq_mask;
53 u32 bdf;
54 u32 ibase;
Bin Mengd4e61f52016-05-07 07:46:14 -070055 bool actl_8bit;
56 int actl_addr;
Bin Meng9c7dea62015-05-25 22:35:04 +080057};
58
59struct pirq_routing {
60 int bdf;
61 int pin;
62 int pirq;
63};
64
Bin Meng9c7dea62015-05-25 22:35:04 +080065#define PIRQ_BITMAP 0xdef8
66
Bin Meng9c7dea62015-05-25 22:35:04 +080067#endif /* _ARCH_IRQ_H_ */