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Marek Vasut71a758e12011-11-08 23:18:09 +00001/*
2 * Freescale i.MX28 SSP MMC driver
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * Based on code from LTIB:
8 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
9 * Terry Lv
10 *
11 * Copyright 2007, Freescale Semiconductor, Inc
12 * Andy Fleming
13 *
14 * Based vaguely on the pxa mmc code:
15 * (C) Copyright 2003
16 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
17 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020018 * SPDX-License-Identifier: GPL-2.0+
Marek Vasut71a758e12011-11-08 23:18:09 +000019 */
20#include <common.h>
21#include <malloc.h>
22#include <mmc.h>
23#include <asm/errno.h>
24#include <asm/io.h>
25#include <asm/arch/clock.h>
26#include <asm/arch/imx-regs.h>
27#include <asm/arch/sys_proto.h>
Stefan Roese04992182013-04-09 21:06:07 +000028#include <asm/imx-common/dma.h>
Marek Vasut4e6d81d2012-08-26 15:19:07 +000029#include <bouncebuf.h>
Marek Vasut71a758e12011-11-08 23:18:09 +000030
31struct mxsmmc_priv {
32 int id;
Otavio Salvador9c471142012-08-05 09:05:31 +000033 struct mxs_ssp_regs *regs;
Marek Vasut71a758e12011-11-08 23:18:09 +000034 uint32_t buswidth;
35 int (*mmc_is_wp)(int);
Marek Vasut90bc2bf2013-01-22 15:01:03 +000036 int (*mmc_cd)(int);
Marek Vasut3687c412012-03-15 18:33:21 +000037 struct mxs_dma_desc *desc;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020038 struct mmc_config cfg; /* mmc configuration */
Marek Vasut71a758e12011-11-08 23:18:09 +000039};
40
41#define MXSMMC_MAX_TIMEOUT 10000
Marek Vasut20255902012-07-06 21:25:56 +000042#define MXSMMC_SMALL_TRANSFER 512
Marek Vasut71a758e12011-11-08 23:18:09 +000043
Marek Vasut90bc2bf2013-01-22 15:01:03 +000044static int mxsmmc_cd(struct mxsmmc_priv *priv)
45{
46 struct mxs_ssp_regs *ssp_regs = priv->regs;
47
48 if (priv->mmc_cd)
49 return priv->mmc_cd(priv->id);
50
51 return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
52}
53
Marek Vasut86983322012-07-06 21:25:55 +000054static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
55{
56 struct mxs_ssp_regs *ssp_regs = priv->regs;
57 uint32_t *data_ptr;
58 int timeout = MXSMMC_MAX_TIMEOUT;
59 uint32_t reg;
60 uint32_t data_count = data->blocksize * data->blocks;
61
62 if (data->flags & MMC_DATA_READ) {
63 data_ptr = (uint32_t *)data->dest;
64 while (data_count && --timeout) {
65 reg = readl(&ssp_regs->hw_ssp_status);
66 if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
67 *data_ptr++ = readl(&ssp_regs->hw_ssp_data);
68 data_count -= 4;
69 timeout = MXSMMC_MAX_TIMEOUT;
70 } else
71 udelay(1000);
72 }
73 } else {
74 data_ptr = (uint32_t *)data->src;
75 timeout *= 100;
76 while (data_count && --timeout) {
77 reg = readl(&ssp_regs->hw_ssp_status);
78 if (!(reg & SSP_STATUS_FIFO_FULL)) {
79 writel(*data_ptr++, &ssp_regs->hw_ssp_data);
80 data_count -= 4;
81 timeout = MXSMMC_MAX_TIMEOUT;
82 } else
83 udelay(1000);
84 }
85 }
86
87 return timeout ? 0 : COMM_ERR;
88}
Marek Vasut20255902012-07-06 21:25:56 +000089
Marek Vasut86983322012-07-06 21:25:55 +000090static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
91{
92 uint32_t data_count = data->blocksize * data->blocks;
Marek Vasut86983322012-07-06 21:25:55 +000093 int dmach;
Marek Vasutabb85be2012-07-06 21:25:57 +000094 struct mxs_dma_desc *desc = priv->desc;
Stephen Warren84d35b22012-11-06 11:27:29 +000095 void *addr;
96 unsigned int flags;
97 struct bounce_buffer bbstate;
Marek Vasutabb85be2012-07-06 21:25:57 +000098
99 memset(desc, 0, sizeof(struct mxs_dma_desc));
100 desc->address = (dma_addr_t)desc;
Marek Vasut86983322012-07-06 21:25:55 +0000101
Marek Vasut86983322012-07-06 21:25:55 +0000102 if (data->flags & MMC_DATA_READ) {
103 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000104 addr = data->dest;
105 flags = GEN_BB_WRITE;
Marek Vasut86983322012-07-06 21:25:55 +0000106 } else {
107 priv->desc->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000108 addr = (void *)data->src;
109 flags = GEN_BB_READ;
110 }
Marek Vasut86983322012-07-06 21:25:55 +0000111
Stephen Warren84d35b22012-11-06 11:27:29 +0000112 bounce_buffer_start(&bbstate, addr, data_count, flags);
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000113
Stephen Warren84d35b22012-11-06 11:27:29 +0000114 priv->desc->cmd.address = (dma_addr_t)bbstate.bounce_buffer;
Marek Vasut97ed12c2012-08-31 16:18:10 +0000115
Marek Vasut86983322012-07-06 21:25:55 +0000116 priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
117 (data_count << MXS_DMA_DESC_BYTES_OFFSET);
118
Marek Vasut3430e0b2013-02-23 02:42:58 +0000119 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
Marek Vasut86983322012-07-06 21:25:55 +0000120 mxs_dma_desc_append(dmach, priv->desc);
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000121 if (mxs_dma_go(dmach)) {
Stephen Warren84d35b22012-11-06 11:27:29 +0000122 bounce_buffer_stop(&bbstate);
Marek Vasut86983322012-07-06 21:25:55 +0000123 return COMM_ERR;
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000124 }
Marek Vasut86983322012-07-06 21:25:55 +0000125
Stephen Warren84d35b22012-11-06 11:27:29 +0000126 bounce_buffer_stop(&bbstate);
Marek Vasut4e6d81d2012-08-26 15:19:07 +0000127
Marek Vasut86983322012-07-06 21:25:55 +0000128 return 0;
129}
Marek Vasut86983322012-07-06 21:25:55 +0000130
Marek Vasut71a758e12011-11-08 23:18:09 +0000131/*
132 * Sends a command out on the bus. Takes the mmc pointer,
133 * a command pointer, and an optional data pointer.
134 */
135static int
136mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
137{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200138 struct mxsmmc_priv *priv = mmc->priv;
Otavio Salvador9c471142012-08-05 09:05:31 +0000139 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasut71a758e12011-11-08 23:18:09 +0000140 uint32_t reg;
141 int timeout;
Marek Vasut71a758e12011-11-08 23:18:09 +0000142 uint32_t ctrl0;
Marek Vasut86983322012-07-06 21:25:55 +0000143 int ret;
Marek Vasut71a758e12011-11-08 23:18:09 +0000144
145 debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
146
147 /* Check bus busy */
148 timeout = MXSMMC_MAX_TIMEOUT;
149 while (--timeout) {
150 udelay(1000);
151 reg = readl(&ssp_regs->hw_ssp_status);
152 if (!(reg &
153 (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
154 SSP_STATUS_CMD_BUSY))) {
155 break;
156 }
157 }
158
159 if (!timeout) {
160 printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
161 return TIMEOUT;
162 }
163
164 /* See if card is present */
Marek Vasut90bc2bf2013-01-22 15:01:03 +0000165 if (!mxsmmc_cd(priv)) {
Marek Vasut71a758e12011-11-08 23:18:09 +0000166 printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
167 return NO_CARD_ERR;
168 }
169
170 /* Start building CTRL0 contents */
171 ctrl0 = priv->buswidth;
172
173 /* Set up command */
174 if (!(cmd->resp_type & MMC_RSP_CRC))
175 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
176 if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
177 ctrl0 |= SSP_CTRL0_GET_RESP;
178 if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
179 ctrl0 |= SSP_CTRL0_LONG_RESP;
180
Marek Vasutabb85be2012-07-06 21:25:57 +0000181 if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER))
182 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
183 else
184 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
185
Marek Vasut71a758e12011-11-08 23:18:09 +0000186 /* Command index */
187 reg = readl(&ssp_regs->hw_ssp_cmd0);
188 reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
189 reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
190 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
191 reg |= SSP_CMD0_APPEND_8CYC;
192 writel(reg, &ssp_regs->hw_ssp_cmd0);
193
194 /* Command argument */
195 writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
196
197 /* Set up data */
198 if (data) {
199 /* READ or WRITE */
200 if (data->flags & MMC_DATA_READ) {
201 ctrl0 |= SSP_CTRL0_READ;
Marek Vasutc7527b72012-05-01 11:09:52 +0000202 } else if (priv->mmc_is_wp &&
203 priv->mmc_is_wp(mmc->block_dev.dev)) {
Marek Vasut71a758e12011-11-08 23:18:09 +0000204 printf("MMC%d: Can not write a locked card!\n",
205 mmc->block_dev.dev);
206 return UNUSABLE_ERR;
207 }
208
209 ctrl0 |= SSP_CTRL0_DATA_XFER;
Marek Vasute5b380a2013-01-22 15:01:04 +0000210
211 reg = data->blocksize * data->blocks;
212#if defined(CONFIG_MX23)
213 ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
214
215 clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
216 SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
217 ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
218 ((ffs(data->blocksize) - 1) <<
219 SSP_CMD0_BLOCK_SIZE_OFFSET));
220#elif defined(CONFIG_MX28)
221 writel(reg, &ssp_regs->hw_ssp_xfer_size);
222
Marek Vasut71a758e12011-11-08 23:18:09 +0000223 reg = ((data->blocks - 1) <<
224 SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
225 ((ffs(data->blocksize) - 1) <<
226 SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
227 writel(reg, &ssp_regs->hw_ssp_block_size);
Marek Vasute5b380a2013-01-22 15:01:04 +0000228#endif
Marek Vasut71a758e12011-11-08 23:18:09 +0000229 }
230
231 /* Kick off the command */
232 ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
233 writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
234
235 /* Wait for the command to complete */
236 timeout = MXSMMC_MAX_TIMEOUT;
237 while (--timeout) {
238 udelay(1000);
239 reg = readl(&ssp_regs->hw_ssp_status);
240 if (!(reg & SSP_STATUS_CMD_BUSY))
241 break;
242 }
243
244 if (!timeout) {
245 printf("MMC%d: Command %d busy\n",
246 mmc->block_dev.dev, cmd->cmdidx);
247 return TIMEOUT;
248 }
249
250 /* Check command timeout */
251 if (reg & SSP_STATUS_RESP_TIMEOUT) {
252 printf("MMC%d: Command %d timeout (status 0x%08x)\n",
253 mmc->block_dev.dev, cmd->cmdidx, reg);
254 return TIMEOUT;
255 }
256
257 /* Check command errors */
258 if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
259 printf("MMC%d: Command %d error (status 0x%08x)!\n",
260 mmc->block_dev.dev, cmd->cmdidx, reg);
261 return COMM_ERR;
262 }
263
264 /* Copy response to response buffer */
265 if (cmd->resp_type & MMC_RSP_136) {
266 cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
267 cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
268 cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
269 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
270 } else
271 cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
272
273 /* Return if no data to process */
274 if (!data)
275 return 0;
276
Marek Vasut20255902012-07-06 21:25:56 +0000277 if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) {
Marek Vasut20255902012-07-06 21:25:56 +0000278 ret = mxsmmc_send_cmd_pio(priv, data);
279 if (ret) {
280 printf("MMC%d: Data timeout with command %d "
281 "(status 0x%08x)!\n",
282 mmc->block_dev.dev, cmd->cmdidx, reg);
283 return ret;
284 }
Marek Vasutabb85be2012-07-06 21:25:57 +0000285 } else {
286 ret = mxsmmc_send_cmd_dma(priv, data);
287 if (ret) {
288 printf("MMC%d: DMA transfer failed\n",
289 mmc->block_dev.dev);
290 return ret;
291 }
Marek Vasut4cc76c62012-04-05 03:30:35 +0000292 }
Marek Vasut3687c412012-03-15 18:33:21 +0000293
Marek Vasut71a758e12011-11-08 23:18:09 +0000294 /* Check data errors */
295 reg = readl(&ssp_regs->hw_ssp_status);
296 if (reg &
297 (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
298 SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
299 printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
300 mmc->block_dev.dev, cmd->cmdidx, reg);
301 return COMM_ERR;
302 }
303
304 return 0;
305}
306
307static void mxsmmc_set_ios(struct mmc *mmc)
308{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200309 struct mxsmmc_priv *priv = mmc->priv;
Otavio Salvador9c471142012-08-05 09:05:31 +0000310 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasut71a758e12011-11-08 23:18:09 +0000311
312 /* Set the clock speed */
313 if (mmc->clock)
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +0000314 mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
Marek Vasut71a758e12011-11-08 23:18:09 +0000315
316 switch (mmc->bus_width) {
317 case 1:
318 priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
319 break;
320 case 4:
321 priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
322 break;
323 case 8:
324 priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
325 break;
326 }
327
328 /* Set the bus width */
329 clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
330 SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
331
332 debug("MMC%d: Set %d bits bus width\n",
333 mmc->block_dev.dev, mmc->bus_width);
334}
335
336static int mxsmmc_init(struct mmc *mmc)
337{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200338 struct mxsmmc_priv *priv = mmc->priv;
Otavio Salvador9c471142012-08-05 09:05:31 +0000339 struct mxs_ssp_regs *ssp_regs = priv->regs;
Marek Vasut71a758e12011-11-08 23:18:09 +0000340
341 /* Reset SSP */
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000342 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
Marek Vasut71a758e12011-11-08 23:18:09 +0000343
Otavio Salvador8000d8a2013-01-22 15:01:02 +0000344 /* Reconfigure the SSP block for MMC operation */
345 writel(SSP_CTRL1_SSP_MODE_SD_MMC |
346 SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
347 SSP_CTRL1_DMA_ENABLE |
348 SSP_CTRL1_POLARITY |
349 SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
350 SSP_CTRL1_DATA_CRC_IRQ_EN |
351 SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
352 SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
353 SSP_CTRL1_RESP_ERR_IRQ_EN,
354 &ssp_regs->hw_ssp_ctrl1_set);
Marek Vasut71a758e12011-11-08 23:18:09 +0000355
356 /* Set initial bit clock 400 KHz */
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +0000357 mxs_set_ssp_busclock(priv->id, 400);
Marek Vasut71a758e12011-11-08 23:18:09 +0000358
359 /* Send initial 74 clock cycles (185 us @ 400 KHz)*/
360 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
361 udelay(200);
362 writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
363
364 return 0;
365}
366
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200367static const struct mmc_ops mxsmmc_ops = {
368 .send_cmd = mxsmmc_send_cmd,
369 .set_ios = mxsmmc_set_ios,
370 .init = mxsmmc_init,
371};
372
Marek Vasut90bc2bf2013-01-22 15:01:03 +0000373int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
Marek Vasut71a758e12011-11-08 23:18:09 +0000374{
Marek Vasut71a758e12011-11-08 23:18:09 +0000375 struct mmc *mmc = NULL;
376 struct mxsmmc_priv *priv = NULL;
Marek Vasut96666a32012-04-08 17:34:46 +0000377 int ret;
Marek Vasut3430e0b2013-02-23 02:42:58 +0000378 const unsigned int mxsmmc_clk_id = mxs_ssp_clock_by_bus(id);
Marek Vasut1a3c5ff2013-01-11 03:19:14 +0000379
Marek Vasut3430e0b2013-02-23 02:42:58 +0000380 if (!mxs_ssp_bus_id_valid(id))
Marek Vasut1a3c5ff2013-01-11 03:19:14 +0000381 return -ENODEV;
Marek Vasut71a758e12011-11-08 23:18:09 +0000382
Marek Vasut71a758e12011-11-08 23:18:09 +0000383 priv = malloc(sizeof(struct mxsmmc_priv));
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200384 if (!priv)
Marek Vasut71a758e12011-11-08 23:18:09 +0000385 return -ENOMEM;
Marek Vasut71a758e12011-11-08 23:18:09 +0000386
Marek Vasut3687c412012-03-15 18:33:21 +0000387 priv->desc = mxs_dma_desc_alloc();
388 if (!priv->desc) {
389 free(priv);
Marek Vasut3687c412012-03-15 18:33:21 +0000390 return -ENOMEM;
391 }
392
Marek Vasut3430e0b2013-02-23 02:42:58 +0000393 ret = mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + id);
Marek Vasut96666a32012-04-08 17:34:46 +0000394 if (ret)
395 return ret;
396
Marek Vasut71a758e12011-11-08 23:18:09 +0000397 priv->mmc_is_wp = wp;
Marek Vasut90bc2bf2013-01-22 15:01:03 +0000398 priv->mmc_cd = cd;
Marek Vasut71a758e12011-11-08 23:18:09 +0000399 priv->id = id;
Marek Vasut14e26bc2013-01-11 03:19:02 +0000400 priv->regs = mxs_ssp_regs_by_bus(id);
Marek Vasut71a758e12011-11-08 23:18:09 +0000401
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200402 priv->cfg.name = "MXS MMC";
403 priv->cfg.ops = &mxsmmc_ops;
Marek Vasut71a758e12011-11-08 23:18:09 +0000404
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200405 priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
Marek Vasut71a758e12011-11-08 23:18:09 +0000406
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200407 priv->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
Rob Herring5a203972015-03-23 17:56:59 -0500408 MMC_MODE_HS_52MHz | MMC_MODE_HS;
Marek Vasut71a758e12011-11-08 23:18:09 +0000409
410 /*
411 * SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
412 * SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
413 * CLOCK_DIVIDE has to be an even value from 2 to 254, and
414 * CLOCK_RATE could be any integer from 0 to 255.
415 */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200416 priv->cfg.f_min = 400000;
417 priv->cfg.f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
418 priv->cfg.b_max = 0x20;
Marek Vasut71a758e12011-11-08 23:18:09 +0000419
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200420 mmc = mmc_create(&priv->cfg, priv);
421 if (mmc == NULL) {
422 mxs_dma_desc_free(priv->desc);
423 free(priv);
424 return -ENOMEM;
425 }
Marek Vasut71a758e12011-11-08 23:18:09 +0000426 return 0;
427}