blob: 0717156c6bd1331a9c5e51214a253c5666c69672 [file] [log] [blame]
Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
Paul Gortmaker2738bc82009-09-20 20:36:06 -04002 * Copyright 2007,2009 Wind River Systems <www.windriver.com>
Joe Hamman9e3ed392007-12-13 06:45:14 -06003 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Joe Hamman9e3ed392007-12-13 06:45:14 -06007 */
8
9/*
10 * sbc8548 board configuration file
Paul Gortmaker2738bc82009-09-20 20:36:06 -040011 * Please refer to doc/README.sbc8548 for more info.
Joe Hamman9e3ed392007-12-13 06:45:14 -060012 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Paul Gortmaker2bf42072014-08-14 10:42:52 -040016#define CONFIG_SYS_GENERIC_BOARD
17
Paul Gortmaker2738bc82009-09-20 20:36:06 -040018/*
19 * Top level Makefile configuration choices
20 */
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020021#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000022#define CONFIG_PCI_INDIRECT_BRIDGE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040023#define CONFIG_PCI1
24#endif
25
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020026#ifdef CONFIG_66
Paul Gortmaker2738bc82009-09-20 20:36:06 -040027#define CONFIG_SYS_CLK_DIV 1
28#endif
29
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020030#ifdef CONFIG_33
Paul Gortmaker2738bc82009-09-20 20:36:06 -040031#define CONFIG_SYS_CLK_DIV 2
32#endif
33
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020034#ifdef CONFIG_PCIE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040035#define CONFIG_PCIE1
36#endif
37
38/*
39 * High Level Configuration Options
40 */
Joe Hamman9e3ed392007-12-13 06:45:14 -060041#define CONFIG_BOOKE 1 /* BOOKE */
42#define CONFIG_E500 1 /* BOOKE e500 family */
Joe Hamman9e3ed392007-12-13 06:45:14 -060043#define CONFIG_MPC8548 1 /* MPC8548 specific */
44#define CONFIG_SBC8548 1 /* SBC8548 board specific */
45
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050046/*
47 * If you want to boot from the SODIMM flash, instead of the soldered
48 * on flash, set this, and change JP12, SW2:8 accordingly.
49 */
50#undef CONFIG_SYS_ALT_BOOT
51
Wolfgang Denk2ae18242010-10-06 09:05:45 +020052#ifndef CONFIG_SYS_TEXT_BASE
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050053#ifdef CONFIG_SYS_ALT_BOOT
54#define CONFIG_SYS_TEXT_BASE 0xfff00000
55#else
Wolfgang Denk2ae18242010-10-06 09:05:45 +020056#define CONFIG_SYS_TEXT_BASE 0xfffa0000
57#endif
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -050058#endif
Wolfgang Denk2ae18242010-10-06 09:05:45 +020059
Joe Hamman9e3ed392007-12-13 06:45:14 -060060#undef CONFIG_RIO
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040061
62#ifdef CONFIG_PCI
63#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
64#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
65#endif
66#ifdef CONFIG_PCIE1
67#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
68#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -060069
70#define CONFIG_TSEC_ENET /* tsec ethernet support */
71#define CONFIG_ENV_OVERWRITE
Joe Hamman9e3ed392007-12-13 06:45:14 -060072
Joe Hamman9e3ed392007-12-13 06:45:14 -060073#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
74
Kumar Galae2b159d2008-01-16 09:05:27 -060075#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060076
Paul Gortmaker2738bc82009-09-20 20:36:06 -040077/*
78 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
79 */
80#ifndef CONFIG_SYS_CLK_DIV
81#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
82#endif
83#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -060084
85/*
86 * These can be toggled for performance analysis, otherwise use default.
87 */
88#define CONFIG_L2_CACHE /* toggle L2 cache */
89#define CONFIG_BTB /* toggle branch predition */
Joe Hamman9e3ed392007-12-13 06:45:14 -060090
91/*
92 * Only possible on E500 Version 2 or newer cores.
93 */
94#define CONFIG_ENABLE_36BIT_PHYS 1
95
96#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
99#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
100#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600101
Timur Tabie46fedf2011-08-04 18:03:41 -0500102#define CONFIG_SYS_CCSRBAR 0xe0000000
103#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Joe Hamman9e3ed392007-12-13 06:45:14 -0600104
Kumar Gala33b90792008-08-26 23:15:28 -0500105/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700106#define CONFIG_SYS_FSL_DDR2
Kumar Gala33b90792008-08-26 23:15:28 -0500107#undef CONFIG_FSL_DDR_INTERACTIVE
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500108#undef CONFIG_DDR_ECC /* only for ECC DDR module */
109/*
110 * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
111 * to collide, meaning you couldn't reliably read either. So
112 * physically remove the LBC PC100 SDRAM module from the board
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500113 * before enabling the two SPD options below, or check that you
114 * have the hardware fix on your board via "i2c probe" and looking
115 * for a device at 0x53.
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500116 */
Kumar Gala33b90792008-08-26 23:15:28 -0500117#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
118#undef CONFIG_DDR_SPD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600119
Kumar Gala33b90792008-08-26 23:15:28 -0500120#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
121#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
124#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala33b90792008-08-26 23:15:28 -0500125#define CONFIG_VERY_BIG_RAM
126
127#define CONFIG_NUM_DDR_CONTROLLERS 1
128#define CONFIG_DIMM_SLOTS_PER_CTLR 1
129#define CONFIG_CHIP_SELECTS_PER_CTRL 2
130
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500131/*
132 * The hardware fix for the I2C address collision puts the DDR
133 * SPD at 0x53, but if we are running on an older board w/o the
134 * fix, it will still be at 0x51. We check 0x53 1st.
135 */
Kumar Gala33b90792008-08-26 23:15:28 -0500136#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500137#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600138
139/*
140 * Make sure required options are set
141 */
142#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Paul Gortmaker2a6b3b72011-12-30 23:53:11 -0500144 #define CONFIG_SYS_DDR_CONTROL 0xc300c000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600145#endif
146
147#undef CONFIG_CLOCKS_IN_MHZ
148
149/*
150 * FLASH on the Local Bus
151 * Two banks, one 8MB the other 64MB, using the CFI driver.
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500152 * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
153 * CS0 the 8MB boot flash, and CS6 the 64MB flash.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600154 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500155 * Default:
156 * ec00_0000 efff_ffff 64MB SODIMM
157 * ff80_0000 ffff_ffff 8MB soldered flash
158 *
159 * Alternate:
160 * ef80_0000 efff_ffff 8MB soldered flash
161 * fc00_0000 ffff_ffff 64MB SODIMM
162 *
163 * BR0_8M:
Joe Hamman9e3ed392007-12-13 06:45:14 -0600164 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
165 * Port Size = 8 bits = BRx[19:20] = 01
166 * Use GPCM = BRx[24:26] = 000
167 * Valid = BRx[31] = 1
168 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500169 * BR0_64M:
170 * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600171 * Port Size = 32 bits = BRx[19:20] = 11
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500172 *
173 * 0 4 8 12 16 20 24 28
174 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M
175 * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M
176 */
177#define CONFIG_SYS_BR0_8M 0xff800801
178#define CONFIG_SYS_BR0_64M 0xfc001801
179
180/*
181 * BR6_8M:
182 * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
183 * Port Size = 8 bits = BRx[19:20] = 01
Joe Hamman9e3ed392007-12-13 06:45:14 -0600184 * Use GPCM = BRx[24:26] = 000
185 * Valid = BRx[31] = 1
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500186
187 * BR6_64M:
188 * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
189 * Port Size = 32 bits = BRx[19:20] = 11
Joe Hamman9e3ed392007-12-13 06:45:14 -0600190 *
191 * 0 4 8 12 16 20 24 28
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500192 * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M
193 * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M
194 */
195#define CONFIG_SYS_BR6_8M 0xef800801
196#define CONFIG_SYS_BR6_64M 0xec001801
197
198/*
199 * OR0_8M:
Joe Hamman9e3ed392007-12-13 06:45:14 -0600200 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
201 * XAM = OR0[17:18] = 11
202 * CSNT = OR0[20] = 1
203 * ACS = half cycle delay = OR0[21:22] = 11
204 * SCY = 6 = OR0[24:27] = 0110
205 * TRLX = use relaxed timing = OR0[29] = 1
206 * EAD = use external address latch delay = OR0[31] = 1
207 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500208 * OR0_64M:
209 * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600210 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500211 *
212 * 0 4 8 12 16 20 24 28
213 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M
214 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M
215 */
216#define CONFIG_SYS_OR0_8M 0xff806e65
217#define CONFIG_SYS_OR0_64M 0xfc006e65
218
219/*
220 * OR6_8M:
221 * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600222 * XAM = OR6[17:18] = 11
223 * CSNT = OR6[20] = 1
224 * ACS = half cycle delay = OR6[21:22] = 11
225 * SCY = 6 = OR6[24:27] = 0110
226 * TRLX = use relaxed timing = OR6[29] = 1
227 * EAD = use external address latch delay = OR6[31] = 1
228 *
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500229 * OR6_64M:
230 * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
231 *
Joe Hamman9e3ed392007-12-13 06:45:14 -0600232 * 0 4 8 12 16 20 24 28
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500233 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M
234 * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M
Joe Hamman9e3ed392007-12-13 06:45:14 -0600235 */
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500236#define CONFIG_SYS_OR6_8M 0xff806e65
237#define CONFIG_SYS_OR6_64M 0xfc006e65
Joe Hamman9e3ed392007-12-13 06:45:14 -0600238
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500239#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
Paul Gortmaker3fd673c2011-12-30 23:53:07 -0500241#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600242
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500243#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M
244#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M
Joe Hamman9e3ed392007-12-13 06:45:14 -0600245
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500246#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M
247#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M
248#else /* JP12 in alternate position */
249#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */
250#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600251
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500252#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M
253#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M
254
255#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M
256#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M
257#endif
258
259#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400260#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
261 CONFIG_SYS_ALT_FLASH}
262#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
263#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#undef CONFIG_SYS_FLASH_CHECKSUM
265#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
266#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600267
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200268#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600269
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200270#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_FLASH_CFI
272#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600273
274/* CS5 = Local bus peripherals controlled by the EPLD */
275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_BR5_PRELIM 0xf8000801
277#define CONFIG_SYS_OR5_PRELIM 0xff006e65
278#define CONFIG_SYS_EPLD_BASE 0xf8000000
279#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
280#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
281#define CONFIG_SYS_BD_REV 0xf8300000
282#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600283
284/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400285 * SDRAM on the Local Bus (CS3 and CS4)
Paul Gortmaker7e44f2b2011-12-30 23:53:10 -0500286 * Note that most boards have a hardware errata where both the
287 * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
288 * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
Paul Gortmaker3e3262b2011-12-30 23:53:12 -0500289 * A hardware workaround is also available, see README.sbc8548 file.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400292#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600293
294/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400295 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600297 *
298 * For BR3, need:
299 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
300 * port-size = 32-bits = BR2[19:20] = 11
301 * no parity checking = BR2[21:22] = 00
302 * SDRAM for MSEL = BR2[24:26] = 011
303 * Valid = BR[31] = 1
304 *
305 * 0 4 8 12 16 20 24 28
306 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
307 *
308 */
309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_BR3_PRELIM 0xf0001861
Joe Hamman9e3ed392007-12-13 06:45:14 -0600311
312/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400313 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600314 *
315 * For OR3, need:
316 * 64MB mask for AM, OR3[0:7] = 1111 1100
317 * XAM, OR3[17:18] = 11
318 * 10 columns OR3[19-21] = 011
319 * 12 rows OR3[23-25] = 011
320 * EAD set for extra time OR[31] = 0
321 *
322 * 0 4 8 12 16 20 24 28
323 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
324 */
325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600327
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400328/*
329 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
330 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
331 *
332 * For BR4, need:
333 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
334 * port-size = 32-bits = BR2[19:20] = 11
335 * no parity checking = BR2[21:22] = 00
336 * SDRAM for MSEL = BR2[24:26] = 011
337 * Valid = BR[31] = 1
338 *
339 * 0 4 8 12 16 20 24 28
340 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
341 *
342 */
343
344#define CONFIG_SYS_BR4_PRELIM 0xf4001861
345
346/*
347 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
348 *
349 * For OR4, need:
350 * 64MB mask for AM, OR3[0:7] = 1111 1100
351 * XAM, OR3[17:18] = 11
352 * 10 columns OR3[19-21] = 011
353 * 12 rows OR3[23-25] = 011
354 * EAD set for extra time OR[31] = 0
355 *
356 * 0 4 8 12 16 20 24 28
357 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
358 */
359
360#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
363#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
364#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
365#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600366
367/*
Joe Hamman9e3ed392007-12-13 06:45:14 -0600368 * Common settings for all Local Bus SDRAM commands.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600369 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500370#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500371 | LSDMR_BSMA1516 \
372 | LSDMR_PRETOACT3 \
373 | LSDMR_ACTTORW3 \
374 | LSDMR_BUFCMD \
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500375 | LSDMR_BL8 \
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500376 | LSDMR_WRC2 \
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500377 | LSDMR_CL3 \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600378 )
379
Paul Gortmaker5f4c6f02011-12-30 23:53:09 -0500380#define CONFIG_SYS_LBC_LSDMR_PCHALL \
381 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
382#define CONFIG_SYS_LBC_LSDMR_ARFRSH \
383 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
384#define CONFIG_SYS_LBC_LSDMR_MRW \
385 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
386#define CONFIG_SYS_LBC_LSDMR_RFEN \
387 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
388
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_INIT_RAM_LOCK 1
390#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200391#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600392
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600394
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200395#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hamman9e3ed392007-12-13 06:45:14 -0600397
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400398/*
399 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200400 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400401 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200402 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400403 * thing for MONITOR_LEN in both cases.
404 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200405#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
Paul Gortmakerf0aec4e2011-12-30 23:53:08 -0500406#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600407
408/* Serial Port */
409#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_NS16550
411#define CONFIG_SYS_NS16550_SERIAL
412#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Gortmaker2738bc82009-09-20 20:36:06 -0400413#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600414
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600416 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
419#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600420
421/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_HUSH_PARSER
Joe Hamman9e3ed392007-12-13 06:45:14 -0600423
424/* pass open firmware flat tree */
425#define CONFIG_OF_LIBFDT 1
426#define CONFIG_OF_BOARD_SETUP 1
427#define CONFIG_OF_STDOUT_VIA_ALIAS 1
428
429/*
430 * I2C
431 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200432#define CONFIG_SYS_I2C
433#define CONFIG_SYS_I2C_FSL
434#define CONFIG_SYS_FSL_I2C_SPEED 400000
435#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
436#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
Joe Hamman9e3ed392007-12-13 06:45:14 -0600438
439/*
440 * General PCI
441 * Memory space is mapped 1-1, but I/O space must start from 0.
442 */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400443#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600445
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400446#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
447#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
448#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400450#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
451#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
452#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
453#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600454
455#ifdef CONFIG_PCIE1
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400456#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
457#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
458#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400460#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
461#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
462#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
463#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600464#endif
465
466#ifdef CONFIG_RIO
467/*
468 * RapidIO MMU
469 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
471#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600472#endif
473
Joe Hamman9e3ed392007-12-13 06:45:14 -0600474#if defined(CONFIG_PCI)
475
Joe Hamman9e3ed392007-12-13 06:45:14 -0600476#define CONFIG_PCI_PNP /* do pci plug-and-play */
477
478#undef CONFIG_EEPRO100
479#undef CONFIG_TULIP
480
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400481#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600482
Joe Hamman9e3ed392007-12-13 06:45:14 -0600483#endif /* CONFIG_PCI */
484
485
486#if defined(CONFIG_TSEC_ENET)
487
Joe Hamman9e3ed392007-12-13 06:45:14 -0600488#define CONFIG_MII 1 /* MII PHY management */
489#define CONFIG_TSEC1 1
490#define CONFIG_TSEC1_NAME "eTSEC0"
491#define CONFIG_TSEC2 1
492#define CONFIG_TSEC2_NAME "eTSEC1"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600493#undef CONFIG_MPC85XX_FEC
494
Paul Gortmaker58da8892008-12-11 15:47:50 -0500495#define TSEC1_PHY_ADDR 0x19
496#define TSEC2_PHY_ADDR 0x1a
Joe Hamman9e3ed392007-12-13 06:45:14 -0600497
498#define TSEC1_PHYIDX 0
499#define TSEC2_PHYIDX 0
Paul Gortmakerbd931052008-12-11 15:47:49 -0500500
Joe Hamman9e3ed392007-12-13 06:45:14 -0600501#define TSEC1_FLAGS TSEC_GIGABIT
502#define TSEC2_FLAGS TSEC_GIGABIT
Joe Hamman9e3ed392007-12-13 06:45:14 -0600503
504/* Options are: eTSEC[0-3] */
505#define CONFIG_ETHPRIME "eTSEC0"
506#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
507#endif /* CONFIG_TSEC_ENET */
508
509/*
510 * Environment
511 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200512#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200513#define CONFIG_ENV_SIZE 0x2000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200514#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400515#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
516#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200517#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400518#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
519#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
520#else
521#warning undefined environment size/location.
522#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -0600523
524#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200525#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600526
527/*
528 * BOOTP options
529 */
530#define CONFIG_BOOTP_BOOTFILESIZE
531#define CONFIG_BOOTP_BOOTPATH
532#define CONFIG_BOOTP_GATEWAY
533#define CONFIG_BOOTP_HOSTNAME
534
535
536/*
537 * Command line configuration.
538 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600539#define CONFIG_CMD_PING
540#define CONFIG_CMD_I2C
541#define CONFIG_CMD_MII
542#define CONFIG_CMD_ELF
Becky Bruce199e2622010-06-17 11:37:25 -0500543#define CONFIG_CMD_REGINFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600544
545#if defined(CONFIG_PCI)
546 #define CONFIG_CMD_PCI
547#endif
548
549
550#undef CONFIG_WATCHDOG /* watchdog disabled */
551
552/*
553 * Miscellaneous configurable options
554 */
Paul Gortmakerad22f922008-12-11 15:47:51 -0500555#define CONFIG_CMDLINE_EDITING /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500556#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_LONGHELP /* undef to save memory */
558#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600559#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600561#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600563#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
565#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
566#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600567
568/*
569 * For booting Linux, the board info and command line data
570 * have to be in the first 8 MB of memory, since this is
571 * the maximum mapped by the Linux kernel during initialization.
572 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600574
Joe Hamman9e3ed392007-12-13 06:45:14 -0600575#if defined(CONFIG_CMD_KGDB)
576#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600577#endif
578
579/*
580 * Environment Configuration
581 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600582#if defined(CONFIG_TSEC_ENET)
583#define CONFIG_HAS_ETH0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600584#define CONFIG_HAS_ETH1
Joe Hamman9e3ed392007-12-13 06:45:14 -0600585#endif
586
587#define CONFIG_IPADDR 192.168.0.55
588
589#define CONFIG_HOSTNAME sbc8548
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000590#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000591#define CONFIG_BOOTFILE "/uImage"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600592#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
593
594#define CONFIG_SERVERIP 192.168.0.2
595#define CONFIG_GATEWAYIP 192.168.0.1
596#define CONFIG_NETMASK 255.255.255.0
597
598#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
599
600#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
601#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
602
603#define CONFIG_BAUDRATE 115200
604
605#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200606"netdev=eth0\0" \
607"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
608"tftpflash=tftpboot $loadaddr $uboot; " \
609 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
610 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
611 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
612 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
613 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
614"consoledev=ttyS0\0" \
615"ramdiskaddr=2000000\0" \
616"ramdiskfile=uRamdisk\0" \
617"fdtaddr=c00000\0" \
618"fdtfile=sbc8548.dtb\0"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600619
620#define CONFIG_NFSBOOTCOMMAND \
621 "setenv bootargs root=/dev/nfs rw " \
622 "nfsroot=$serverip:$rootpath " \
623 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
624 "console=$consoledev,$baudrate $othbootargs;" \
625 "tftp $loadaddr $bootfile;" \
626 "tftp $fdtaddr $fdtfile;" \
627 "bootm $loadaddr - $fdtaddr"
628
629
630#define CONFIG_RAMBOOTCOMMAND \
631 "setenv bootargs root=/dev/ram rw " \
632 "console=$consoledev,$baudrate $othbootargs;" \
633 "tftp $ramdiskaddr $ramdiskfile;" \
634 "tftp $loadaddr $bootfile;" \
635 "tftp $fdtaddr $fdtfile;" \
636 "bootm $loadaddr $ramdiskaddr $fdtaddr"
637
638#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
639
640#endif /* __CONFIG_H */