blob: 61d7f3df69ee6532077074d4a28507d4f31aa17a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +00002/*------------------------------------------------------------------------
3 . smc91111.c
4 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
5 .
6 . (C) Copyright 2002
7 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 . Rolf Offermanns <rof@sysgo.de>
9 .
10 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
wdenk42dfe7a2004-03-14 22:25:36 +000011 . Developed by Simple Network Magic Corporation (SNMC)
wdenkfe8c2802002-11-03 00:38:21 +000012 . Copyright (C) 1996 by Erik Stahlman (ES)
13 .
wdenkfe8c2802002-11-03 00:38:21 +000014 .
15 . Information contained in this file was obtained from the LAN91C111
16 . manual from SMC. To get a copy, if you really want one, you can find
17 . information under www.smsc.com.
18 .
19 .
20 . "Features" of the SMC chip:
21 . Integrated PHY/MAC for 10/100BaseT Operation
22 . Supports internal and external MII
23 . Integrated 8K packet memory
24 . EEPROM interface for configuration
25 .
26 . Arguments:
wdenk42dfe7a2004-03-14 22:25:36 +000027 . io = for the base address
wdenkfe8c2802002-11-03 00:38:21 +000028 . irq = for the IRQ
29 .
30 . author:
wdenk42dfe7a2004-03-14 22:25:36 +000031 . Erik Stahlman ( erik@vt.edu )
32 . Daris A Nevil ( dnevil@snmc.com )
wdenkfe8c2802002-11-03 00:38:21 +000033 .
34 .
35 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
36 .
37 . Sources:
wdenk42dfe7a2004-03-14 22:25:36 +000038 . o SMSC LAN91C111 databook (www.smsc.com)
39 . o smc9194.c by Erik Stahlman
40 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
wdenkfe8c2802002-11-03 00:38:21 +000041 .
42 . History:
wdenk42dfe7a2004-03-14 22:25:36 +000043 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
wdenkfe8c2802002-11-03 00:38:21 +000044 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
wdenk42dfe7a2004-03-14 22:25:36 +000045 . 07/25/01 Woojung Huh Modify for ADS Bitsy
46 . 04/25/01 Daris A Nevil Initial public release through SMSC
47 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
wdenkfe8c2802002-11-03 00:38:21 +000048 ----------------------------------------------------------------------------*/
49
50#include <common.h>
51#include <command.h>
wdenkf39748a2004-06-09 13:37:52 +000052#include <config.h>
Ben Warren7194ab82009-10-04 22:37:03 -070053#include <malloc.h>
Simon Glassc05ed002020-05-10 11:40:11 -060054#include <linux/delay.h>
wdenkfe8c2802002-11-03 00:38:21 +000055#include "smc91111.h"
56#include <net.h>
57
wdenkfe8c2802002-11-03 00:38:21 +000058/* Use power-down feature of the chip */
59#define POWER_DOWN 0
60
61#define NO_AUTOPROBE
62
Wolfgang Denk0be248f2006-03-07 00:22:36 +010063#define SMC_DEBUG 0
wdenk8bf3b002003-12-06 23:20:41 +000064
65#if SMC_DEBUG > 1
wdenkfe8c2802002-11-03 00:38:21 +000066static const char version[] =
67 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
wdenk8bf3b002003-12-06 23:20:41 +000068#endif
wdenkfe8c2802002-11-03 00:38:21 +000069
wdenkf39748a2004-06-09 13:37:52 +000070/* Autonegotiation timeout in seconds */
71#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
72#define CONFIG_SMC_AUTONEG_TIMEOUT 10
73#endif
74
wdenkfe8c2802002-11-03 00:38:21 +000075/*------------------------------------------------------------------------
76 .
77 . Configuration options, for the experienced user to change.
78 .
79 -------------------------------------------------------------------------*/
80
81/*
82 . Wait time for memory to be free. This probably shouldn't be
83 . tuned that much, as waiting for this means nothing else happens
84 . in the system
85*/
86#define MEMORY_WAIT_TIME 16
87
88
89#if (SMC_DEBUG > 2 )
90#define PRINTK3(args...) printf(args)
91#else
92#define PRINTK3(args...)
93#endif
94
95#if SMC_DEBUG > 1
96#define PRINTK2(args...) printf(args)
97#else
98#define PRINTK2(args...)
99#endif
100
101#ifdef SMC_DEBUG
102#define PRINTK(args...) printf(args)
103#else
104#define PRINTK(args...)
105#endif
106
107
108/*------------------------------------------------------------------------
109 .
wdenk42dfe7a2004-03-14 22:25:36 +0000110 . The internal workings of the driver. If you are changing anything
wdenkfe8c2802002-11-03 00:38:21 +0000111 . here with the SMC stuff, you should have the datasheet and know
112 . what you are doing.
113 .
114 -------------------------------------------------------------------------*/
wdenkfe8c2802002-11-03 00:38:21 +0000115
116/* Memory sizing constant */
117#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
118
119#ifndef CONFIG_SMC91111_BASE
Ben Warren7194ab82009-10-04 22:37:03 -0700120#error "SMC91111 Base address must be passed to initialization funciton"
121/* #define CONFIG_SMC91111_BASE 0x20000300 */
wdenkfe8c2802002-11-03 00:38:21 +0000122#endif
123
wdenkfe8c2802002-11-03 00:38:21 +0000124#define SMC_DEV_NAME "SMC91111"
125#define SMC_PHY_ADDR 0x0000
126#define SMC_ALLOC_MAX_TRY 5
127#define SMC_TX_TIMEOUT 30
128
129#define SMC_PHY_CLOCK_DELAY 1000
130
131#define ETH_ZLEN 60
132
wdenk42dfe7a2004-03-14 22:25:36 +0000133#ifdef CONFIG_SMC_USE_32_BIT
wdenkfe8c2802002-11-03 00:38:21 +0000134#define USE_32_BIT 1
135#else
136#undef USE_32_BIT
137#endif
wdenkfe8c2802002-11-03 00:38:21 +0000138
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100139#ifdef SHARED_RESOURCES
Ben Warren7194ab82009-10-04 22:37:03 -0700140extern void swap_to(int device_id);
141#else
142# define swap_to(x)
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100143#endif
wdenkfe8c2802002-11-03 00:38:21 +0000144
wdenkfe8c2802002-11-03 00:38:21 +0000145#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700146static void smc_phy_configure(struct eth_device *dev);
wdenkfe8c2802002-11-03 00:38:21 +0000147#endif /* !CONFIG_SMC91111_EXT_PHY */
148
149/*
wdenkfe8c2802002-11-03 00:38:21 +0000150 ------------------------------------------------------------
151 .
152 . Internal routines
153 .
154 ------------------------------------------------------------
155*/
156
wdenkc3c7f862004-06-09 14:47:54 +0000157#ifdef CONFIG_SMC_USE_IOFUNCS
158/*
159 * input and output functions
160 *
161 * Implemented due to inx,outx macros accessing the device improperly
162 * and putting the device into an unkown state.
163 *
164 * For instance, on Sharp LPD7A400 SDK, affects were chip memory
165 * could not be free'd (hence the alloc failures), duplicate packets,
166 * packets being corrupt (shifted) on the wire, etc. Switching to the
167 * inx,outx functions fixed this problem.
168 */
wdenkc3c7f862004-06-09 14:47:54 +0000169
Ben Warren7194ab82009-10-04 22:37:03 -0700170static inline word SMC_inw(struct eth_device *dev, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000171{
172 word v;
Ben Warren7194ab82009-10-04 22:37:03 -0700173 v = *((volatile word*)(dev->iobase + offset));
wdenkc3c7f862004-06-09 14:47:54 +0000174 barrier(); *(volatile u32*)(0xc0000000);
175 return v;
176}
177
Ben Warren7194ab82009-10-04 22:37:03 -0700178static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000179{
Ben Warren7194ab82009-10-04 22:37:03 -0700180 *((volatile word*)(dev->iobase + offset)) = value;
wdenkc3c7f862004-06-09 14:47:54 +0000181 barrier(); *(volatile u32*)(0xc0000000);
182}
183
Ben Warren7194ab82009-10-04 22:37:03 -0700184static inline byte SMC_inb(struct eth_device *dev, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000185{
186 word _w;
187
Ben Warren7194ab82009-10-04 22:37:03 -0700188 _w = SMC_inw(dev, offset & ~((dword)1));
wdenkc3c7f862004-06-09 14:47:54 +0000189 return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
190}
191
Ben Warren7194ab82009-10-04 22:37:03 -0700192static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
wdenkc3c7f862004-06-09 14:47:54 +0000193{
194 word _w;
195
Ben Warren7194ab82009-10-04 22:37:03 -0700196 _w = SMC_inw(dev, offset & ~((dword)1));
wdenkc3c7f862004-06-09 14:47:54 +0000197 if (offset & 1)
Ben Warren7194ab82009-10-04 22:37:03 -0700198 *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
199 (value<<8) | (_w & 0x00ff);
wdenkc3c7f862004-06-09 14:47:54 +0000200 else
Ben Warren7194ab82009-10-04 22:37:03 -0700201 *((volatile word*)(dev->iobase + offset)) =
202 value | (_w & 0xff00);
wdenkc3c7f862004-06-09 14:47:54 +0000203}
204
Ben Warren7194ab82009-10-04 22:37:03 -0700205static inline void SMC_insw(struct eth_device *dev, dword offset,
206 volatile uchar* buf, dword len)
wdenkc3c7f862004-06-09 14:47:54 +0000207{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100208 volatile word *p = (volatile word *)buf;
209
wdenkc3c7f862004-06-09 14:47:54 +0000210 while (len-- > 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700211 *p++ = SMC_inw(dev, offset);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100212 barrier();
213 *((volatile u32*)(0xc0000000));
wdenkc3c7f862004-06-09 14:47:54 +0000214 }
215}
216
Ben Warren7194ab82009-10-04 22:37:03 -0700217static inline void SMC_outsw(struct eth_device *dev, dword offset,
218 uchar* buf, dword len)
wdenkc3c7f862004-06-09 14:47:54 +0000219{
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100220 volatile word *p = (volatile word *)buf;
221
wdenkc3c7f862004-06-09 14:47:54 +0000222 while (len-- > 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700223 SMC_outw(dev, *p++, offset);
Wolfgang Denkd52fb7e2006-03-11 22:53:33 +0100224 barrier();
225 *(volatile u32*)(0xc0000000);
wdenkc3c7f862004-06-09 14:47:54 +0000226 }
227}
228#endif /* CONFIG_SMC_USE_IOFUNCS */
229
wdenkfe8c2802002-11-03 00:38:21 +0000230/*
231 . A rather simple routine to print out a packet for debugging purposes.
232*/
233#if SMC_DEBUG > 2
234static void print_packet( byte *, int );
235#endif
236
237#define tx_done(dev) 1
238
Ben Warren7194ab82009-10-04 22:37:03 -0700239static int poll4int (struct eth_device *dev, byte mask, int timeout)
wdenkb56ddc62003-09-15 21:14:37 +0000240{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
wdenkb56ddc62003-09-15 21:14:37 +0000242 int is_timeout = 0;
Ben Warren7194ab82009-10-04 22:37:03 -0700243 word old_bank = SMC_inw (dev, BSR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000244
wdenkb56ddc62003-09-15 21:14:37 +0000245 PRINTK2 ("Polling...\n");
Ben Warren7194ab82009-10-04 22:37:03 -0700246 SMC_SELECT_BANK (dev, 2);
247 while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
wdenkb56ddc62003-09-15 21:14:37 +0000248 if (get_timer (0) >= tmo) {
249 is_timeout = 1;
250 break;
251 }
wdenkfe8c2802002-11-03 00:38:21 +0000252 }
wdenkfe8c2802002-11-03 00:38:21 +0000253
wdenkb56ddc62003-09-15 21:14:37 +0000254 /* restore old bank selection */
Ben Warren7194ab82009-10-04 22:37:03 -0700255 SMC_SELECT_BANK (dev, old_bank);
wdenkfe8c2802002-11-03 00:38:21 +0000256
wdenkb56ddc62003-09-15 21:14:37 +0000257 if (is_timeout)
258 return 1;
259 else
260 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000261}
262
wdenk487778b2003-06-06 11:20:01 +0000263/* Only one release command at a time, please */
Ben Warren7194ab82009-10-04 22:37:03 -0700264static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
wdenk487778b2003-06-06 11:20:01 +0000265{
266 int count = 0;
wdenkb56ddc62003-09-15 21:14:37 +0000267
wdenk487778b2003-06-06 11:20:01 +0000268 /* assume bank 2 selected */
Ben Warren7194ab82009-10-04 22:37:03 -0700269 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
Simon Glass07e11142020-05-10 11:40:10 -0600270 udelay(1); /* Wait until not busy */
wdenkb56ddc62003-09-15 21:14:37 +0000271 if (++count > 200)
272 break;
wdenk487778b2003-06-06 11:20:01 +0000273 }
274}
275
wdenkfe8c2802002-11-03 00:38:21 +0000276/*
277 . Function: smc_reset( void )
278 . Purpose:
wdenk42dfe7a2004-03-14 22:25:36 +0000279 . This sets the SMC91111 chip to its normal state, hopefully from whatever
280 . mess that any other DOS driver has put it in.
wdenkfe8c2802002-11-03 00:38:21 +0000281 .
282 . Maybe I should reset more registers to defaults in here? SOFTRST should
283 . do that for me.
284 .
285 . Method:
286 . 1. send a SOFT RESET
287 . 2. wait for it to finish
288 . 3. enable autorelease mode
289 . 4. reset the memory management unit
290 . 5. clear all interrupts
291 .
292*/
Ben Warren7194ab82009-10-04 22:37:03 -0700293static void smc_reset (struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000294{
wdenkf39748a2004-06-09 13:37:52 +0000295 PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000296
297 /* This resets the registers mostly to defaults, but doesn't
298 affect EEPROM. That seems unnecessary */
Ben Warren7194ab82009-10-04 22:37:03 -0700299 SMC_SELECT_BANK (dev, 0);
300 SMC_outw (dev, RCR_SOFTRST, RCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000301
302 /* Setup the Configuration Register */
303 /* This is necessary because the CONFIG_REG is not affected */
304 /* by a soft reset */
305
Ben Warren7194ab82009-10-04 22:37:03 -0700306 SMC_SELECT_BANK (dev, 1);
wdenkfe8c2802002-11-03 00:38:21 +0000307#if defined(CONFIG_SMC91111_EXT_PHY)
Ben Warren7194ab82009-10-04 22:37:03 -0700308 SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000309#else
Ben Warren7194ab82009-10-04 22:37:03 -0700310 SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000311#endif
312
313
314 /* Release from possible power-down state */
315 /* Configuration register is not affected by Soft Reset */
Ben Warren7194ab82009-10-04 22:37:03 -0700316 SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
317 CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000318
Ben Warren7194ab82009-10-04 22:37:03 -0700319 SMC_SELECT_BANK (dev, 0);
wdenkfe8c2802002-11-03 00:38:21 +0000320
321 /* this should pause enough for the chip to be happy */
Simon Glass07e11142020-05-10 11:40:10 -0600322 udelay(10);
wdenkfe8c2802002-11-03 00:38:21 +0000323
324 /* Disable transmit and receive functionality */
Ben Warren7194ab82009-10-04 22:37:03 -0700325 SMC_outw (dev, RCR_CLEAR, RCR_REG);
326 SMC_outw (dev, TCR_CLEAR, TCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000327
328 /* set the control register */
Ben Warren7194ab82009-10-04 22:37:03 -0700329 SMC_SELECT_BANK (dev, 1);
330 SMC_outw (dev, CTL_DEFAULT, CTL_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000331
332 /* Reset the MMU */
Ben Warren7194ab82009-10-04 22:37:03 -0700333 SMC_SELECT_BANK (dev, 2);
334 smc_wait_mmu_release_complete (dev);
335 SMC_outw (dev, MC_RESET, MMU_CMD_REG);
336 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
Simon Glass07e11142020-05-10 11:40:10 -0600337 udelay(1); /* Wait until not busy */
wdenkfe8c2802002-11-03 00:38:21 +0000338
339 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
340 but this is a place where future chipsets _COULD_ break. Be wary
wdenk8bde7f72003-06-27 21:31:46 +0000341 of issuing another MMU command right after this */
wdenkfe8c2802002-11-03 00:38:21 +0000342
343 /* Disable all interrupts */
Ben Warren7194ab82009-10-04 22:37:03 -0700344 SMC_outb (dev, 0, IM_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000345}
346
347/*
348 . Function: smc_enable
349 . Purpose: let the chip talk to the outside work
350 . Method:
351 . 1. Enable the transmitter
352 . 2. Enable the receiver
353 . 3. Enable interrupts
354*/
Ben Warren7194ab82009-10-04 22:37:03 -0700355static void smc_enable(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000356{
wdenkf39748a2004-06-09 13:37:52 +0000357 PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
Ben Warren7194ab82009-10-04 22:37:03 -0700358 SMC_SELECT_BANK( dev, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000359 /* see the header file for options in TCR/RCR DEFAULT*/
Ben Warren7194ab82009-10-04 22:37:03 -0700360 SMC_outw( dev, TCR_DEFAULT, TCR_REG );
361 SMC_outw( dev, RCR_DEFAULT, RCR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000362
363 /* clear MII_DIS */
364/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
365}
366
367/*
Ben Warren7194ab82009-10-04 22:37:03 -0700368 . Function: smc_halt
wdenkfe8c2802002-11-03 00:38:21 +0000369 . Purpose: closes down the SMC91xxx chip.
370 . Method:
371 . 1. zero the interrupt mask
372 . 2. clear the enable receive flag
373 . 3. clear the enable xmit flags
374 .
375 . TODO:
376 . (1) maybe utilize power down mode.
377 . Why not yet? Because while the chip will go into power down mode,
378 . the manual says that it will wake up in response to any I/O requests
wdenk42dfe7a2004-03-14 22:25:36 +0000379 . in the register space. Empirical results do not show this working.
wdenkfe8c2802002-11-03 00:38:21 +0000380*/
Ben Warren7194ab82009-10-04 22:37:03 -0700381static void smc_halt(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000382{
Ben Warren7194ab82009-10-04 22:37:03 -0700383 PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000384
385 /* no more interrupts for me */
Ben Warren7194ab82009-10-04 22:37:03 -0700386 SMC_SELECT_BANK( dev, 2 );
387 SMC_outb( dev, 0, IM_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000388
389 /* and tell the card to stay away from that nasty outside world */
Ben Warren7194ab82009-10-04 22:37:03 -0700390 SMC_SELECT_BANK( dev, 0 );
391 SMC_outb( dev, RCR_CLEAR, RCR_REG );
392 SMC_outb( dev, TCR_CLEAR, TCR_REG );
393
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100394 swap_to(FLASH);
wdenkfe8c2802002-11-03 00:38:21 +0000395}
396
397
398/*
Ben Warren7194ab82009-10-04 22:37:03 -0700399 . Function: smc_send(struct net_device * )
wdenkfe8c2802002-11-03 00:38:21 +0000400 . Purpose:
401 . This sends the actual packet to the SMC9xxx chip.
402 .
403 . Algorithm:
wdenk42dfe7a2004-03-14 22:25:36 +0000404 . First, see if a saved_skb is available.
wdenkfe8c2802002-11-03 00:38:21 +0000405 . ( this should NOT be called if there is no 'saved_skb'
406 . Now, find the packet number that the chip allocated
407 . Point the data pointers at it in memory
408 . Set the length word in the chip's memory
409 . Dump the packet to chip memory
410 . Check if a last byte is needed ( odd length packet )
411 . if so, set the control flag right
wdenk42dfe7a2004-03-14 22:25:36 +0000412 . Tell the card to send it
wdenkfe8c2802002-11-03 00:38:21 +0000413 . Enable the transmit interrupt, so I know if it failed
wdenk42dfe7a2004-03-14 22:25:36 +0000414 . Free the kernel data if I actually sent it.
wdenkfe8c2802002-11-03 00:38:21 +0000415*/
Joe Hershberger9f098642012-05-21 14:45:32 +0000416static int smc_send(struct eth_device *dev, void *packet, int packet_length)
wdenkfe8c2802002-11-03 00:38:21 +0000417{
wdenkb56ddc62003-09-15 21:14:37 +0000418 byte packet_no;
wdenkb56ddc62003-09-15 21:14:37 +0000419 byte *buf;
420 int length;
421 int numPages;
422 int try = 0;
423 int time_out;
424 byte status;
wdenk518e2e12004-03-25 14:59:05 +0000425 byte saved_pnr;
426 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000427
wdenk518e2e12004-03-25 14:59:05 +0000428 /* save PTR and PNR registers before manipulation */
Ben Warren7194ab82009-10-04 22:37:03 -0700429 SMC_SELECT_BANK (dev, 2);
430 saved_pnr = SMC_inb( dev, PN_REG );
431 saved_ptr = SMC_inw( dev, PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000432
wdenkf39748a2004-06-09 13:37:52 +0000433 PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000434
435 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
436
437 /* allocate memory
wdenkb56ddc62003-09-15 21:14:37 +0000438 ** The MMU wants the number of pages to be the number of 256 bytes
439 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
440 **
441 ** The 91C111 ignores the size bits, but the code is left intact
442 ** for backwards and future compatibility.
443 **
444 ** Pkt size for allocating is data length +6 (for additional status
445 ** words, length and ctl!)
446 **
447 ** If odd size then last byte is included in this header.
448 */
449 numPages = ((length & 0xfffe) + 6);
450 numPages >>= 8; /* Divide by 256 */
wdenkfe8c2802002-11-03 00:38:21 +0000451
wdenkb56ddc62003-09-15 21:14:37 +0000452 if (numPages > 7) {
453 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000454 return 0;
455 }
456
457 /* now, try to allocate the memory */
Ben Warren7194ab82009-10-04 22:37:03 -0700458 SMC_SELECT_BANK (dev, 2);
459 SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000460
wdenkdc7c9a12003-03-26 06:55:25 +0000461 /* FIXME: the ALLOC_INT bit never gets set *
wdenk42dfe7a2004-03-14 22:25:36 +0000462 * so the following will always give a *
463 * memory allocation error. *
464 * same code works in armboot though *
wdenkdc7c9a12003-03-26 06:55:25 +0000465 * -ro
466 */
467
wdenkfe8c2802002-11-03 00:38:21 +0000468again:
469 try++;
470 time_out = MEMORY_WAIT_TIME;
471 do {
Ben Warren7194ab82009-10-04 22:37:03 -0700472 status = SMC_inb (dev, SMC91111_INT_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000473 if (status & IM_ALLOC_INT) {
wdenkfe8c2802002-11-03 00:38:21 +0000474 /* acknowledge the interrupt */
Ben Warren7194ab82009-10-04 22:37:03 -0700475 SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
wdenk8bde7f72003-06-27 21:31:46 +0000476 break;
wdenkfe8c2802002-11-03 00:38:21 +0000477 }
wdenkb56ddc62003-09-15 21:14:37 +0000478 } while (--time_out);
wdenkfe8c2802002-11-03 00:38:21 +0000479
wdenkb56ddc62003-09-15 21:14:37 +0000480 if (!time_out) {
481 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
482 SMC_DEV_NAME, try);
483 if (try < SMC_ALLOC_MAX_TRY)
484 goto again;
485 else
486 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000487 }
488
wdenkb56ddc62003-09-15 21:14:37 +0000489 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
490 SMC_DEV_NAME, try);
wdenkfe8c2802002-11-03 00:38:21 +0000491
wdenkb56ddc62003-09-15 21:14:37 +0000492 buf = (byte *) packet;
wdenkfe8c2802002-11-03 00:38:21 +0000493
494 /* If I get here, I _know_ there is a packet slot waiting for me */
Ben Warren7194ab82009-10-04 22:37:03 -0700495 packet_no = SMC_inb (dev, AR_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000496 if (packet_no & AR_FAILED) {
wdenkfe8c2802002-11-03 00:38:21 +0000497 /* or isn't there? BAD CHIP! */
wdenkb56ddc62003-09-15 21:14:37 +0000498 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000499 return 0;
500 }
501
502 /* we have a packet address, so tell the card to use it */
Ben Warren7194ab82009-10-04 22:37:03 -0700503 SMC_outb (dev, packet_no, PN_REG);
Simon Glass1c87dd72015-08-30 19:19:34 -0600504
wdenkb79a11c2004-03-25 15:14:43 +0000505 /* do not write new ptr value if Write data fifo not empty */
506 while ( saved_ptr & PTR_NOTEMPTY )
wdenk518e2e12004-03-25 14:59:05 +0000507 printf ("Write data fifo not empty!\n");
508
wdenkfe8c2802002-11-03 00:38:21 +0000509 /* point to the beginning of the packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700510 SMC_outw (dev, PTR_AUTOINC, PTR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000511
wdenkb56ddc62003-09-15 21:14:37 +0000512 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
513 SMC_DEV_NAME, length);
wdenkfe8c2802002-11-03 00:38:21 +0000514
515#if SMC_DEBUG > 2
wdenkb56ddc62003-09-15 21:14:37 +0000516 printf ("Transmitting Packet\n");
517 print_packet (buf, length);
wdenkfe8c2802002-11-03 00:38:21 +0000518#endif
519
520 /* send the packet length ( +6 for status, length and ctl byte )
wdenk8bde7f72003-06-27 21:31:46 +0000521 and the status word ( set to zeros ) */
wdenkfe8c2802002-11-03 00:38:21 +0000522#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700523 SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000524#else
Ben Warren7194ab82009-10-04 22:37:03 -0700525 SMC_outw (dev, 0, SMC91111_DATA_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000526 /* send the packet length ( +6 for status words, length, and ctl */
Ben Warren7194ab82009-10-04 22:37:03 -0700527 SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000528#endif
529
530 /* send the actual data
wdenkb56ddc62003-09-15 21:14:37 +0000531 . I _think_ it's faster to send the longs first, and then
532 . mop up by sending the last word. It depends heavily
wdenk42dfe7a2004-03-14 22:25:36 +0000533 . on alignment, at least on the 486. Maybe it would be
wdenkb56ddc62003-09-15 21:14:37 +0000534 . a good idea to check which is optimal? But that could take
535 . almost as much time as is saved?
536 */
wdenkfe8c2802002-11-03 00:38:21 +0000537#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700538 SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
wdenkb56ddc62003-09-15 21:14:37 +0000539 if (length & 0x2)
Ben Warren7194ab82009-10-04 22:37:03 -0700540 SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
wdenkb56ddc62003-09-15 21:14:37 +0000541 SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000542#else
Ben Warren7194ab82009-10-04 22:37:03 -0700543 SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000544#endif /* USE_32_BIT */
545
wdenk42dfe7a2004-03-14 22:25:36 +0000546 /* Send the last byte, if there is one. */
wdenkb56ddc62003-09-15 21:14:37 +0000547 if ((length & 1) == 0) {
Ben Warren7194ab82009-10-04 22:37:03 -0700548 SMC_outw (dev, 0, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000549 } else {
Ben Warren7194ab82009-10-04 22:37:03 -0700550 SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000551 }
552
553 /* and let the chipset deal with it */
Ben Warren7194ab82009-10-04 22:37:03 -0700554 SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000555
556 /* poll for TX INT */
Ben Warren7194ab82009-10-04 22:37:03 -0700557 /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
wdenk518e2e12004-03-25 14:59:05 +0000558 /* poll for TX_EMPTY INT - autorelease enabled */
Ben Warren7194ab82009-10-04 22:37:03 -0700559 if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
wdenkfe8c2802002-11-03 00:38:21 +0000560 /* sending failed */
wdenkb56ddc62003-09-15 21:14:37 +0000561 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000562
563 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000564 /* no need to release, MMU does that now */
wdenkfe8c2802002-11-03 00:38:21 +0000565
wdenk8bde7f72003-06-27 21:31:46 +0000566 /* wait for MMU getting ready (low) */
Ben Warren7194ab82009-10-04 22:37:03 -0700567 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
Simon Glass07e11142020-05-10 11:40:10 -0600568 udelay(10);
wdenk8bde7f72003-06-27 21:31:46 +0000569 }
wdenkfe8c2802002-11-03 00:38:21 +0000570
wdenkb56ddc62003-09-15 21:14:37 +0000571 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000572
573
574 return 0;
575 } else {
576 /* ack. int */
Ben Warren7194ab82009-10-04 22:37:03 -0700577 SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
wdenk518e2e12004-03-25 14:59:05 +0000578 /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
wdenkb56ddc62003-09-15 21:14:37 +0000579 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
580 length);
wdenkfe8c2802002-11-03 00:38:21 +0000581
582 /* release packet */
wdenk518e2e12004-03-25 14:59:05 +0000583 /* no need to release, MMU does that now */
wdenkfe8c2802002-11-03 00:38:21 +0000584
wdenk8bde7f72003-06-27 21:31:46 +0000585 /* wait for MMU getting ready (low) */
Ben Warren7194ab82009-10-04 22:37:03 -0700586 while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
Simon Glass07e11142020-05-10 11:40:10 -0600587 udelay(10);
wdenk8bde7f72003-06-27 21:31:46 +0000588 }
wdenkfe8c2802002-11-03 00:38:21 +0000589
wdenkb56ddc62003-09-15 21:14:37 +0000590 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000591
592
593 }
594
wdenk518e2e12004-03-25 14:59:05 +0000595 /* restore previously saved registers */
Ben Warren7194ab82009-10-04 22:37:03 -0700596 SMC_outb( dev, saved_pnr, PN_REG );
Ben Warren7194ab82009-10-04 22:37:03 -0700597 SMC_outw( dev, saved_ptr, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000598
wdenkfe8c2802002-11-03 00:38:21 +0000599 return length;
600}
601
Thomas Chou1ca6d0d2010-10-06 09:16:10 +0800602static int smc_write_hwaddr(struct eth_device *dev)
603{
604 int i;
605
606 swap_to(ETHERNET);
607 SMC_SELECT_BANK (dev, 1);
608#ifdef USE_32_BIT
609 for (i = 0; i < 6; i += 2) {
610 word address;
611
612 address = dev->enetaddr[i + 1] << 8;
613 address |= dev->enetaddr[i];
614 SMC_outw(dev, address, (ADDR0_REG + i));
615 }
616#else
617 for (i = 0; i < 6; i++)
618 SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
619#endif
620 swap_to(FLASH);
621 return 0;
622}
623
wdenkfe8c2802002-11-03 00:38:21 +0000624/*
625 * Open and Initialize the board
626 *
627 * Set up everything, reset the card, etc ..
628 *
629 */
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900630static int smc_init(struct eth_device *dev, struct bd_info *bd)
wdenkfe8c2802002-11-03 00:38:21 +0000631{
Ben Warren7194ab82009-10-04 22:37:03 -0700632 swap_to(ETHERNET);
633
634 PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000635
636 /* reset the hardware */
Ben Warren7194ab82009-10-04 22:37:03 -0700637 smc_reset (dev);
638 smc_enable (dev);
wdenkfe8c2802002-11-03 00:38:21 +0000639
640 /* Configure the PHY */
641#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700642 smc_phy_configure (dev);
wdenkfe8c2802002-11-03 00:38:21 +0000643#endif
644
wdenkfe8c2802002-11-03 00:38:21 +0000645 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
Ben Warren7194ab82009-10-04 22:37:03 -0700646/* SMC_SELECT_BANK(dev, 0); */
647/* SMC_outw(dev, 0, RPC_REG); */
wdenkfe8c2802002-11-03 00:38:21 +0000648
Ben Warren7194ab82009-10-04 22:37:03 -0700649 printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
650
wdenkfe8c2802002-11-03 00:38:21 +0000651 return 0;
652}
653
wdenkfe8c2802002-11-03 00:38:21 +0000654/*-------------------------------------------------------------
655 .
656 . smc_rcv - receive a packet from the card
657 .
658 . There is ( at least ) a packet waiting to be read from
659 . chip-memory.
660 .
661 . o Read the status
662 . o If an error, record it
663 . o otherwise, read in the packet
664 --------------------------------------------------------------
665*/
Ben Warren7194ab82009-10-04 22:37:03 -0700666static int smc_rcv(struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +0000667{
wdenk42dfe7a2004-03-14 22:25:36 +0000668 int packet_number;
wdenkfe8c2802002-11-03 00:38:21 +0000669 word status;
670 word packet_length;
wdenk42dfe7a2004-03-14 22:25:36 +0000671 int is_error = 0;
wdenkfe8c2802002-11-03 00:38:21 +0000672#ifdef USE_32_BIT
673 dword stat_len;
674#endif
wdenk518e2e12004-03-25 14:59:05 +0000675 byte saved_pnr;
676 word saved_ptr;
wdenkfe8c2802002-11-03 00:38:21 +0000677
Ben Warren7194ab82009-10-04 22:37:03 -0700678 SMC_SELECT_BANK(dev, 2);
wdenk518e2e12004-03-25 14:59:05 +0000679 /* save PTR and PTR registers */
Ben Warren7194ab82009-10-04 22:37:03 -0700680 saved_pnr = SMC_inb( dev, PN_REG );
681 saved_ptr = SMC_inw( dev, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000682
Ben Warren7194ab82009-10-04 22:37:03 -0700683 packet_number = SMC_inw( dev, RXFIFO_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000684
685 if ( packet_number & RXFIFO_REMPTY ) {
686
687 return 0;
688 }
689
wdenkf39748a2004-06-09 13:37:52 +0000690 PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000691 /* start reading from the start of the packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700692 SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000693
694 /* First two words are status and packet_length */
695#ifdef USE_32_BIT
Ben Warren7194ab82009-10-04 22:37:03 -0700696 stat_len = SMC_inl(dev, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000697 status = stat_len & 0xffff;
698 packet_length = stat_len >> 16;
699#else
Ben Warren7194ab82009-10-04 22:37:03 -0700700 status = SMC_inw( dev, SMC91111_DATA_REG );
701 packet_length = SMC_inw( dev, SMC91111_DATA_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000702#endif
703
704 packet_length &= 0x07ff; /* mask off top bits */
705
706 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
707
708 if ( !(status & RS_ERRORS ) ){
709 /* Adjust for having already read the first two words */
710 packet_length -= 4; /*4; */
711
712
wdenkfe8c2802002-11-03 00:38:21 +0000713 /* set odd length for bug in LAN91C111, */
714 /* which never sets RS_ODDFRAME */
715 /* TODO ? */
716
717
718#ifdef USE_32_BIT
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500719 PRINTK3(" Reading %d dwords (and %d bytes)\n",
wdenkfe8c2802002-11-03 00:38:21 +0000720 packet_length >> 2, packet_length & 3 );
721 /* QUESTION: Like in the TX routine, do I want
722 to send the DWORDs or the bytes first, or some
723 mixture. A mixture might improve already slow PIO
wdenk42dfe7a2004-03-14 22:25:36 +0000724 performance */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500725 SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
726 packet_length >> 2);
wdenkfe8c2802002-11-03 00:38:21 +0000727 /* read the left over bytes */
728 if (packet_length & 3) {
729 int i;
730
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500731 byte *tail = (byte *)(net_rx_packets[0] +
Ben Warren7194ab82009-10-04 22:37:03 -0700732 (packet_length & ~3));
733 dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000734 for (i=0; i<(packet_length & 3); i++)
735 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
736 }
737#else
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500738 PRINTK3(" Reading %d words and %d byte(s)\n",
wdenkfe8c2802002-11-03 00:38:21 +0000739 (packet_length >> 1 ), packet_length & 1 );
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500740 SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
741 packet_length >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000742
743#endif /* USE_32_BIT */
744
745#if SMC_DEBUG > 2
746 printf("Receiving Packet\n");
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500747 print_packet(net_rx_packets[0], packet_length);
wdenkfe8c2802002-11-03 00:38:21 +0000748#endif
749 } else {
750 /* error ... */
751 /* TODO ? */
752 is_error = 1;
753 }
754
Ben Warren7194ab82009-10-04 22:37:03 -0700755 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
wdenkfe8c2802002-11-03 00:38:21 +0000756 udelay(1); /* Wait until not busy */
757
758 /* error or good, tell the card to get rid of this packet */
Ben Warren7194ab82009-10-04 22:37:03 -0700759 SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
wdenkfe8c2802002-11-03 00:38:21 +0000760
Ben Warren7194ab82009-10-04 22:37:03 -0700761 while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
wdenkfe8c2802002-11-03 00:38:21 +0000762 udelay(1); /* Wait until not busy */
763
wdenk518e2e12004-03-25 14:59:05 +0000764 /* restore saved registers */
Ben Warren7194ab82009-10-04 22:37:03 -0700765 SMC_outb( dev, saved_pnr, PN_REG );
Ben Warren7194ab82009-10-04 22:37:03 -0700766 SMC_outw( dev, saved_ptr, PTR_REG );
wdenk518e2e12004-03-25 14:59:05 +0000767
wdenkfe8c2802002-11-03 00:38:21 +0000768 if (!is_error) {
769 /* Pass the packet up to the protocol layers. */
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500770 net_process_received_packet(net_rx_packets[0], packet_length);
wdenkfe8c2802002-11-03 00:38:21 +0000771 return packet_length;
772 } else {
773 return 0;
774 }
775
776}
777
778
wdenkfe8c2802002-11-03 00:38:21 +0000779#if 0
780/*------------------------------------------------------------
781 . Modify a bit in the LAN91C111 register set
782 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700783static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
wdenkfe8c2802002-11-03 00:38:21 +0000784 unsigned int bit, int val)
785{
786 word regval;
787
Ben Warren7194ab82009-10-04 22:37:03 -0700788 SMC_SELECT_BANK( dev, bank );
wdenkfe8c2802002-11-03 00:38:21 +0000789
Ben Warren7194ab82009-10-04 22:37:03 -0700790 regval = SMC_inw( dev, reg );
wdenkfe8c2802002-11-03 00:38:21 +0000791 if (val)
792 regval |= bit;
793 else
794 regval &= ~bit;
795
Ben Warren7194ab82009-10-04 22:37:03 -0700796 SMC_outw( dev, regval, 0 );
wdenkfe8c2802002-11-03 00:38:21 +0000797 return(regval);
798}
799
800
801/*------------------------------------------------------------
802 . Retrieve a bit in the LAN91C111 register set
803 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700804static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
wdenkfe8c2802002-11-03 00:38:21 +0000805{
Ben Warren7194ab82009-10-04 22:37:03 -0700806 SMC_SELECT_BANK( dev, bank );
807 if ( SMC_inw( dev, reg ) & bit)
wdenkfe8c2802002-11-03 00:38:21 +0000808 return(1);
809 else
810 return(0);
811}
812
813
814/*------------------------------------------------------------
815 . Modify a LAN91C111 register (word access only)
816 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700817static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
wdenkfe8c2802002-11-03 00:38:21 +0000818{
Ben Warren7194ab82009-10-04 22:37:03 -0700819 SMC_SELECT_BANK( dev, bank );
820 SMC_outw( dev, val, reg );
wdenkfe8c2802002-11-03 00:38:21 +0000821}
822
823
824/*------------------------------------------------------------
825 . Retrieve a LAN91C111 register (word access only)
826 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -0700827static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
wdenkfe8c2802002-11-03 00:38:21 +0000828{
Ben Warren7194ab82009-10-04 22:37:03 -0700829 SMC_SELECT_BANK( dev, bank );
830 return(SMC_inw( dev, reg ));
wdenkfe8c2802002-11-03 00:38:21 +0000831}
832
833#endif /* 0 */
834
835/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
836
837#if (SMC_DEBUG > 2 )
838
839/*------------------------------------------------------------
840 . Debugging function for viewing MII Management serial bitstream
841 .-------------------------------------------------------------*/
wdenkb56ddc62003-09-15 21:14:37 +0000842static void smc_dump_mii_stream (byte * bits, int size)
wdenkfe8c2802002-11-03 00:38:21 +0000843{
844 int i;
845
wdenkb56ddc62003-09-15 21:14:37 +0000846 printf ("BIT#:");
847 for (i = 0; i < size; ++i) {
848 printf ("%d", i % 10);
849 }
wdenkfe8c2802002-11-03 00:38:21 +0000850
wdenkb56ddc62003-09-15 21:14:37 +0000851 printf ("\nMDOE:");
852 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000853 if (bits[i] & MII_MDOE)
wdenkb56ddc62003-09-15 21:14:37 +0000854 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000855 else
wdenkb56ddc62003-09-15 21:14:37 +0000856 printf ("0");
857 }
wdenkfe8c2802002-11-03 00:38:21 +0000858
wdenkb56ddc62003-09-15 21:14:37 +0000859 printf ("\nMDO :");
860 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000861 if (bits[i] & MII_MDO)
wdenkb56ddc62003-09-15 21:14:37 +0000862 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000863 else
wdenkb56ddc62003-09-15 21:14:37 +0000864 printf ("0");
865 }
wdenkfe8c2802002-11-03 00:38:21 +0000866
wdenkb56ddc62003-09-15 21:14:37 +0000867 printf ("\nMDI :");
868 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000869 if (bits[i] & MII_MDI)
wdenkb56ddc62003-09-15 21:14:37 +0000870 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000871 else
wdenkb56ddc62003-09-15 21:14:37 +0000872 printf ("0");
873 }
wdenkfe8c2802002-11-03 00:38:21 +0000874
wdenkb56ddc62003-09-15 21:14:37 +0000875 printf ("\n");
wdenkfe8c2802002-11-03 00:38:21 +0000876}
877#endif
878
879/*------------------------------------------------------------
880 . Reads a register from the MII Management serial interface
881 .-------------------------------------------------------------*/
882#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -0700883static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
wdenkfe8c2802002-11-03 00:38:21 +0000884{
885 int oldBank;
886 int i;
887 byte mask;
888 word mii_reg;
889 byte bits[64];
890 int clk_idx = 0;
891 int input_idx;
892 word phydata;
893 byte phyaddr = SMC_PHY_ADDR;
894
895 /* 32 consecutive ones on MDO to establish sync */
896 for (i = 0; i < 32; ++i)
897 bits[clk_idx++] = MII_MDOE | MII_MDO;
898
899 /* Start code <01> */
900 bits[clk_idx++] = MII_MDOE;
901 bits[clk_idx++] = MII_MDOE | MII_MDO;
902
903 /* Read command <10> */
904 bits[clk_idx++] = MII_MDOE | MII_MDO;
905 bits[clk_idx++] = MII_MDOE;
906
907 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000908 mask = (byte) 0x10;
909 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000910 if (phyaddr & mask)
911 bits[clk_idx++] = MII_MDOE | MII_MDO;
912 else
913 bits[clk_idx++] = MII_MDOE;
914
915 /* Shift to next lowest bit */
916 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000917 }
wdenkfe8c2802002-11-03 00:38:21 +0000918
919 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000920 mask = (byte) 0x10;
921 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000922 if (phyreg & mask)
923 bits[clk_idx++] = MII_MDOE | MII_MDO;
924 else
925 bits[clk_idx++] = MII_MDOE;
926
927 /* Shift to next lowest bit */
928 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000929 }
wdenkfe8c2802002-11-03 00:38:21 +0000930
931 /* Tristate and turnaround (2 bit times) */
932 bits[clk_idx++] = 0;
933 /*bits[clk_idx++] = 0; */
934
935 /* Input starts at this bit time */
936 input_idx = clk_idx;
937
938 /* Will input 16 bits */
939 for (i = 0; i < 16; ++i)
940 bits[clk_idx++] = 0;
941
942 /* Final clock bit */
943 bits[clk_idx++] = 0;
944
945 /* Save the current bank */
Ben Warren7194ab82009-10-04 22:37:03 -0700946 oldBank = SMC_inw (dev, BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +0000947
948 /* Select bank 3 */
Ben Warren7194ab82009-10-04 22:37:03 -0700949 SMC_SELECT_BANK (dev, 3);
wdenkfe8c2802002-11-03 00:38:21 +0000950
951 /* Get the current MII register value */
Ben Warren7194ab82009-10-04 22:37:03 -0700952 mii_reg = SMC_inw (dev, MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000953
954 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +0000955 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +0000956
957 /* Clock all 64 cycles */
wdenkb56ddc62003-09-15 21:14:37 +0000958 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000959 /* Clock Low - output data */
Ben Warren7194ab82009-10-04 22:37:03 -0700960 SMC_outw (dev, mii_reg | bits[i], MII_REG);
Simon Glass07e11142020-05-10 11:40:10 -0600961 udelay(SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +0000962
963
964 /* Clock Hi - input data */
Ben Warren7194ab82009-10-04 22:37:03 -0700965 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
Simon Glass07e11142020-05-10 11:40:10 -0600966 udelay(SMC_PHY_CLOCK_DELAY);
Ben Warren7194ab82009-10-04 22:37:03 -0700967 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
wdenkb56ddc62003-09-15 21:14:37 +0000968 }
wdenkfe8c2802002-11-03 00:38:21 +0000969
970 /* Return to idle state */
971 /* Set clock to low, data to low, and output tristated */
Ben Warren7194ab82009-10-04 22:37:03 -0700972 SMC_outw (dev, mii_reg, MII_REG);
Simon Glass07e11142020-05-10 11:40:10 -0600973 udelay(SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +0000974
975 /* Restore original bank select */
Ben Warren7194ab82009-10-04 22:37:03 -0700976 SMC_SELECT_BANK (dev, oldBank);
wdenkfe8c2802002-11-03 00:38:21 +0000977
978 /* Recover input data */
979 phydata = 0;
wdenkb56ddc62003-09-15 21:14:37 +0000980 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000981 phydata <<= 1;
982
983 if (bits[input_idx++] & MII_MDI)
984 phydata |= 0x0001;
wdenkb56ddc62003-09-15 21:14:37 +0000985 }
wdenkfe8c2802002-11-03 00:38:21 +0000986
987#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +0000988 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +0000989 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +0000990 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +0000991#endif
992
wdenkb56ddc62003-09-15 21:14:37 +0000993 return (phydata);
wdenkfe8c2802002-11-03 00:38:21 +0000994}
995
996
997/*------------------------------------------------------------
998 . Writes a register to the MII Management serial interface
999 .-------------------------------------------------------------*/
Ben Warren7194ab82009-10-04 22:37:03 -07001000static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
1001 word phydata)
wdenkfe8c2802002-11-03 00:38:21 +00001002{
1003 int oldBank;
1004 int i;
1005 word mask;
1006 word mii_reg;
1007 byte bits[65];
1008 int clk_idx = 0;
1009 byte phyaddr = SMC_PHY_ADDR;
1010
1011 /* 32 consecutive ones on MDO to establish sync */
1012 for (i = 0; i < 32; ++i)
1013 bits[clk_idx++] = MII_MDOE | MII_MDO;
1014
1015 /* Start code <01> */
1016 bits[clk_idx++] = MII_MDOE;
1017 bits[clk_idx++] = MII_MDOE | MII_MDO;
1018
1019 /* Write command <01> */
1020 bits[clk_idx++] = MII_MDOE;
1021 bits[clk_idx++] = MII_MDOE | MII_MDO;
1022
1023 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001024 mask = (byte) 0x10;
1025 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001026 if (phyaddr & mask)
1027 bits[clk_idx++] = MII_MDOE | MII_MDO;
1028 else
1029 bits[clk_idx++] = MII_MDOE;
1030
1031 /* Shift to next lowest bit */
1032 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001033 }
wdenkfe8c2802002-11-03 00:38:21 +00001034
1035 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001036 mask = (byte) 0x10;
1037 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001038 if (phyreg & mask)
1039 bits[clk_idx++] = MII_MDOE | MII_MDO;
1040 else
1041 bits[clk_idx++] = MII_MDOE;
1042
1043 /* Shift to next lowest bit */
1044 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001045 }
wdenkfe8c2802002-11-03 00:38:21 +00001046
1047 /* Tristate and turnaround (2 bit times) */
1048 bits[clk_idx++] = 0;
1049 bits[clk_idx++] = 0;
1050
1051 /* Write out 16 bits of data, msb first */
1052 mask = 0x8000;
wdenkb56ddc62003-09-15 21:14:37 +00001053 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001054 if (phydata & mask)
1055 bits[clk_idx++] = MII_MDOE | MII_MDO;
1056 else
1057 bits[clk_idx++] = MII_MDOE;
1058
1059 /* Shift to next lowest bit */
1060 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001061 }
wdenkfe8c2802002-11-03 00:38:21 +00001062
1063 /* Final clock bit (tristate) */
1064 bits[clk_idx++] = 0;
1065
1066 /* Save the current bank */
Ben Warren7194ab82009-10-04 22:37:03 -07001067 oldBank = SMC_inw (dev, BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001068
1069 /* Select bank 3 */
Ben Warren7194ab82009-10-04 22:37:03 -07001070 SMC_SELECT_BANK (dev, 3);
wdenkfe8c2802002-11-03 00:38:21 +00001071
1072 /* Get the current MII register value */
Ben Warren7194ab82009-10-04 22:37:03 -07001073 mii_reg = SMC_inw (dev, MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001074
1075 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001076 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001077
1078 /* Clock all cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001079 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001080 /* Clock Low - output data */
Ben Warren7194ab82009-10-04 22:37:03 -07001081 SMC_outw (dev, mii_reg | bits[i], MII_REG);
Simon Glass07e11142020-05-10 11:40:10 -06001082 udelay(SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001083
1084
1085 /* Clock Hi - input data */
Ben Warren7194ab82009-10-04 22:37:03 -07001086 SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
Simon Glass07e11142020-05-10 11:40:10 -06001087 udelay(SMC_PHY_CLOCK_DELAY);
Ben Warren7194ab82009-10-04 22:37:03 -07001088 bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
wdenkb56ddc62003-09-15 21:14:37 +00001089 }
wdenkfe8c2802002-11-03 00:38:21 +00001090
1091 /* Return to idle state */
1092 /* Set clock to low, data to low, and output tristated */
Ben Warren7194ab82009-10-04 22:37:03 -07001093 SMC_outw (dev, mii_reg, MII_REG);
Simon Glass07e11142020-05-10 11:40:10 -06001094 udelay(SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001095
1096 /* Restore original bank select */
Ben Warren7194ab82009-10-04 22:37:03 -07001097 SMC_SELECT_BANK (dev, oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001098
1099#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001100 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001101 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001102 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001103#endif
1104}
1105#endif /* !CONFIG_SMC91111_EXT_PHY */
1106
1107
wdenkfe8c2802002-11-03 00:38:21 +00001108/*------------------------------------------------------------
wdenkfe8c2802002-11-03 00:38:21 +00001109 . Configures the specified PHY using Autonegotiation. Calls
1110 . smc_phy_fixed() if the user has requested a certain config.
1111 .-------------------------------------------------------------*/
1112#ifndef CONFIG_SMC91111_EXT_PHY
Ben Warren7194ab82009-10-04 22:37:03 -07001113static void smc_phy_configure (struct eth_device *dev)
wdenkfe8c2802002-11-03 00:38:21 +00001114{
1115 int timeout;
wdenkb56ddc62003-09-15 21:14:37 +00001116 word my_phy_caps; /* My PHY capabilities */
1117 word my_ad_caps; /* My Advertised capabilities */
1118 word status = 0; /*;my status = 0 */
wdenkfe8c2802002-11-03 00:38:21 +00001119
wdenkf39748a2004-06-09 13:37:52 +00001120 PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001121
wdenkfe8c2802002-11-03 00:38:21 +00001122 /* Reset the PHY, setting all other bits to zero */
Ben Warren7194ab82009-10-04 22:37:03 -07001123 smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001124
1125 /* Wait for the reset to complete, or time out */
wdenkb56ddc62003-09-15 21:14:37 +00001126 timeout = 6; /* Wait up to 3 seconds */
1127 while (timeout--) {
Ben Warren7194ab82009-10-04 22:37:03 -07001128 if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
wdenkb56ddc62003-09-15 21:14:37 +00001129 & PHY_CNTL_RST)) {
wdenkfe8c2802002-11-03 00:38:21 +00001130 /* reset complete */
1131 break;
wdenkfe8c2802002-11-03 00:38:21 +00001132 }
1133
Mike Frysinger65029492012-03-05 13:46:51 +00001134 mdelay(500); /* wait 500 millisecs */
wdenkb56ddc62003-09-15 21:14:37 +00001135 }
1136
1137 if (timeout < 1) {
1138 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001139 goto smc_phy_configure_exit;
wdenkb56ddc62003-09-15 21:14:37 +00001140 }
wdenkfe8c2802002-11-03 00:38:21 +00001141
1142 /* Read PHY Register 18, Status Output */
1143 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1144
1145 /* Enable PHY Interrupts (for register 18) */
1146 /* Interrupts listed here are disabled */
Ben Warren7194ab82009-10-04 22:37:03 -07001147 smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
wdenkfe8c2802002-11-03 00:38:21 +00001148
1149 /* Configure the Receive/Phy Control register */
Ben Warren7194ab82009-10-04 22:37:03 -07001150 SMC_SELECT_BANK (dev, 0);
1151 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001152
1153 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
Ben Warren7194ab82009-10-04 22:37:03 -07001154 my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001155 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
wdenkfe8c2802002-11-03 00:38:21 +00001156
1157 if (my_phy_caps & PHY_STAT_CAP_T4)
1158 my_ad_caps |= PHY_AD_T4;
1159
1160 if (my_phy_caps & PHY_STAT_CAP_TXF)
1161 my_ad_caps |= PHY_AD_TX_FDX;
1162
1163 if (my_phy_caps & PHY_STAT_CAP_TXH)
1164 my_ad_caps |= PHY_AD_TX_HDX;
1165
1166 if (my_phy_caps & PHY_STAT_CAP_TF)
1167 my_ad_caps |= PHY_AD_10_FDX;
1168
1169 if (my_phy_caps & PHY_STAT_CAP_TH)
1170 my_ad_caps |= PHY_AD_10_HDX;
1171
1172 /* Update our Auto-Neg Advertisement Register */
Ben Warren7194ab82009-10-04 22:37:03 -07001173 smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001174
wdenk518e2e12004-03-25 14:59:05 +00001175 /* Read the register back. Without this, it appears that when */
1176 /* auto-negotiation is restarted, sometimes it isn't ready and */
1177 /* the link does not come up. */
Ben Warren7194ab82009-10-04 22:37:03 -07001178 smc_read_phy_register(dev, PHY_AD_REG);
wdenk518e2e12004-03-25 14:59:05 +00001179
wdenkf39748a2004-06-09 13:37:52 +00001180 PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1181 PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001182
1183 /* Restart auto-negotiation process in order to advertise my caps */
Ben Warren7194ab82009-10-04 22:37:03 -07001184 smc_write_phy_register (dev, PHY_CNTL_REG,
wdenkb56ddc62003-09-15 21:14:37 +00001185 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001186
1187 /* Wait for the auto-negotiation to complete. This may take from */
1188 /* 2 to 3 seconds. */
1189 /* Wait for the reset to complete, or time out */
wdenkf39748a2004-06-09 13:37:52 +00001190 timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
wdenkb56ddc62003-09-15 21:14:37 +00001191 while (timeout--) {
wdenkf39748a2004-06-09 13:37:52 +00001192
Ben Warren7194ab82009-10-04 22:37:03 -07001193 status = smc_read_phy_register (dev, PHY_STAT_REG);
wdenkb56ddc62003-09-15 21:14:37 +00001194 if (status & PHY_STAT_ANEG_ACK) {
wdenkfe8c2802002-11-03 00:38:21 +00001195 /* auto-negotiate complete */
1196 break;
wdenkb56ddc62003-09-15 21:14:37 +00001197 }
wdenkfe8c2802002-11-03 00:38:21 +00001198
Mike Frysinger65029492012-03-05 13:46:51 +00001199 mdelay(500); /* wait 500 millisecs */
wdenkfe8c2802002-11-03 00:38:21 +00001200
1201 /* Restart auto-negotiation if remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001202 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001203 printf ("%s: PHY remote fault detected\n",
wdenkb56ddc62003-09-15 21:14:37 +00001204 SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001205
1206 /* Restart auto-negotiation */
wdenkf39748a2004-06-09 13:37:52 +00001207 printf ("%s: PHY restarting auto-negotiation\n",
wdenkfe8c2802002-11-03 00:38:21 +00001208 SMC_DEV_NAME);
Ben Warren7194ab82009-10-04 22:37:03 -07001209 smc_write_phy_register (dev, PHY_CNTL_REG,
wdenkb56ddc62003-09-15 21:14:37 +00001210 PHY_CNTL_ANEG_EN |
1211 PHY_CNTL_ANEG_RST |
1212 PHY_CNTL_SPEED |
1213 PHY_CNTL_DPLX);
wdenkfe8c2802002-11-03 00:38:21 +00001214 }
wdenkb56ddc62003-09-15 21:14:37 +00001215 }
wdenkfe8c2802002-11-03 00:38:21 +00001216
wdenkb56ddc62003-09-15 21:14:37 +00001217 if (timeout < 1) {
wdenkf39748a2004-06-09 13:37:52 +00001218 printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
wdenkb56ddc62003-09-15 21:14:37 +00001219 }
wdenkfe8c2802002-11-03 00:38:21 +00001220
1221 /* Fail if we detected an auto-negotiate remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001222 if (status & PHY_STAT_REM_FLT) {
wdenkf39748a2004-06-09 13:37:52 +00001223 printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
wdenkb56ddc62003-09-15 21:14:37 +00001224 }
wdenkfe8c2802002-11-03 00:38:21 +00001225
1226 /* Re-Configure the Receive/Phy Control register */
Ben Warren7194ab82009-10-04 22:37:03 -07001227 SMC_outw (dev, RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001228
wdenk26238132004-07-09 22:51:01 +00001229smc_phy_configure_exit: ;
wdenkfe8c2802002-11-03 00:38:21 +00001230
1231}
1232#endif /* !CONFIG_SMC91111_EXT_PHY */
1233
1234
1235#if SMC_DEBUG > 2
1236static void print_packet( byte * buf, int length )
1237{
wdenk8bde7f72003-06-27 21:31:46 +00001238 int i;
1239 int remainder;
1240 int lines;
wdenkfe8c2802002-11-03 00:38:21 +00001241
wdenk8bde7f72003-06-27 21:31:46 +00001242 printf("Packet of length %d \n", length );
wdenkfe8c2802002-11-03 00:38:21 +00001243
1244#if SMC_DEBUG > 3
wdenk8bde7f72003-06-27 21:31:46 +00001245 lines = length / 16;
1246 remainder = length % 16;
wdenkfe8c2802002-11-03 00:38:21 +00001247
wdenk8bde7f72003-06-27 21:31:46 +00001248 for ( i = 0; i < lines ; i ++ ) {
1249 int cur;
wdenkfe8c2802002-11-03 00:38:21 +00001250
wdenk8bde7f72003-06-27 21:31:46 +00001251 for ( cur = 0; cur < 8; cur ++ ) {
1252 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001253
wdenk8bde7f72003-06-27 21:31:46 +00001254 a = *(buf ++ );
1255 b = *(buf ++ );
1256 printf("%02x%02x ", a, b );
1257 }
1258 printf("\n");
1259 }
1260 for ( i = 0; i < remainder/2 ; i++ ) {
1261 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001262
wdenk8bde7f72003-06-27 21:31:46 +00001263 a = *(buf ++ );
1264 b = *(buf ++ );
1265 printf("%02x%02x ", a, b );
1266 }
1267 printf("\n");
wdenkfe8c2802002-11-03 00:38:21 +00001268#endif
wdenkfe8c2802002-11-03 00:38:21 +00001269}
1270#endif
1271
Peter Hoyesb8da46f2021-07-09 10:52:06 +01001272int smc91111_initialize(u8 dev_num, phys_addr_t base_addr)
wdenk0b97ab12003-06-19 23:58:30 +00001273{
Ben Warren7194ab82009-10-04 22:37:03 -07001274 struct smc91111_priv *priv;
1275 struct eth_device *dev;
wdenk3d3befa2004-03-14 15:06:13 +00001276 int i;
wdenkf39748a2004-06-09 13:37:52 +00001277
Ben Warren7194ab82009-10-04 22:37:03 -07001278 priv = malloc(sizeof(*priv));
1279 if (!priv)
1280 return 0;
1281 dev = malloc(sizeof(*dev));
1282 if (!dev) {
1283 free(priv);
1284 return 0;
wdenkb56ddc62003-09-15 21:14:37 +00001285 }
wdenkf39748a2004-06-09 13:37:52 +00001286
Thomas Chou1ca6d0d2010-10-06 09:16:10 +08001287 memset(dev, 0, sizeof(*dev));
Ben Warren7194ab82009-10-04 22:37:03 -07001288 priv->dev_num = dev_num;
1289 dev->priv = priv;
1290 dev->iobase = base_addr;
1291
1292 swap_to(ETHERNET);
1293 SMC_SELECT_BANK(dev, 1);
1294 for (i = 0; i < 6; ++i)
1295 dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
1296 swap_to(FLASH);
1297
1298 dev->init = smc_init;
1299 dev->halt = smc_halt;
1300 dev->send = smc_send;
1301 dev->recv = smc_rcv;
Thomas Chou1ca6d0d2010-10-06 09:16:10 +08001302 dev->write_hwaddr = smc_write_hwaddr;
Ben Warren7194ab82009-10-04 22:37:03 -07001303 sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
1304
1305 eth_register(dev);
1306 return 0;
wdenk0b97ab12003-06-19 23:58:30 +00001307}