Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Renesas R7780MP board |
| 4 | * |
Nobuhiro Iwamatsu | ec39d47 | 2008-06-17 16:28:01 +0900 | [diff] [blame] | 5 | * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 6 | * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __R7780RP_H |
| 10 | #define __R7780RP_H |
| 11 | |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 12 | #define CONFIG_CPU_SH7780 1 |
| 13 | #define CONFIG_R7780MP 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 14 | #define CONFIG_SYS_R7780MP_OLD_FLASH 1 |
Nobuhiro Iwamatsu | ec39d47 | 2008-06-17 16:28:01 +0900 | [diff] [blame] | 15 | #define __LITTLE_ENDIAN__ 1 |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 16 | |
Vladimir Zapolskiy | 18a40e8 | 2016-11-28 00:15:30 +0200 | [diff] [blame] | 17 | #define CONFIG_DISPLAY_BOARDINFO |
| 18 | |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 19 | #define CONFIG_CONS_SCIF0 1 |
| 20 | |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 21 | #define CONFIG_ENV_OVERWRITE 1 |
| 22 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | #define CONFIG_SYS_SDRAM_BASE (0x08000000) |
| 24 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 25 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 26 | #define CONFIG_SYS_PBSIZE 256 |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 27 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 28 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 29 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 30 | |
Nobuhiro Iwamatsu | ec39d47 | 2008-06-17 16:28:01 +0900 | [diff] [blame] | 31 | /* Flash board support */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | #define CONFIG_SYS_FLASH_BASE (0xA0000000) |
| 33 | #ifdef CONFIG_SYS_R7780MP_OLD_FLASH |
Nobuhiro Iwamatsu | ec39d47 | 2008-06-17 16:28:01 +0900 | [diff] [blame] | 34 | /* NOR Flash (S29PL127J60TFI130) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 35 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
| 36 | # define CONFIG_SYS_MAX_FLASH_BANKS (2) |
| 37 | # define CONFIG_SYS_MAX_FLASH_SECT 270 |
| 38 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ |
| 39 | CONFIG_SYS_FLASH_BASE + 0x100000,\ |
| 40 | CONFIG_SYS_FLASH_BASE + 0x400000,\ |
| 41 | CONFIG_SYS_FLASH_BASE + 0x700000, } |
| 42 | #else /* CONFIG_SYS_R7780MP_OLD_FLASH */ |
Nobuhiro Iwamatsu | ec39d47 | 2008-06-17 16:28:01 +0900 | [diff] [blame] | 43 | /* NOR Flash (Spantion S29GL256P) */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | # define CONFIG_SYS_MAX_FLASH_BANKS (1) |
| 45 | # define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 46 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
| 47 | #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 48 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 50 | /* Address of u-boot image in Flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 51 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) |
| 52 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 53 | /* Size of DRAM reserved for malloc() use */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 54 | #define CONFIG_SYS_MALLOC_LEN (1204 * 1024) |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 55 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 56 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
| 57 | #define CONFIG_SYS_RX_ETH_BUFFER (8) |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 58 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 59 | #define CONFIG_SYS_FLASH_CFI |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 60 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE |
| 62 | #undef CONFIG_SYS_FLASH_QUIET_TEST |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 63 | /* print 'E' for empty sector on flinfo */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 64 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 65 | |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 66 | #define CONFIG_ENV_SECT_SIZE (256 * 1024) |
| 67 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 69 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 |
| 70 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 71 | |
| 72 | /* Board Clock */ |
| 73 | #define CONFIG_SYS_CLK_FREQ 33333333 |
Nobuhiro Iwamatsu | 684a501 | 2013-08-21 16:11:21 +0900 | [diff] [blame] | 74 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
| 75 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
Jean-Christophe PLAGNIOL-VILLARD | be45c63 | 2009-06-04 12:06:48 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 77 | |
| 78 | /* PCI Controller */ |
| 79 | #if defined(CONFIG_CMD_PCI) |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 80 | #define CONFIG_SH4_PCI |
Nobuhiro Iwamatsu | ab8f4d4 | 2008-03-24 02:11:26 +0900 | [diff] [blame] | 81 | #define CONFIG_SH7780_PCI |
Yoshihiro Shimoda | 06b1816 | 2009-02-25 14:26:42 +0900 | [diff] [blame] | 82 | #define CONFIG_SH7780_PCI_LSR 0x07f00001 |
| 83 | #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE |
| 84 | #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 85 | #define CONFIG_PCI_SCAN_SHOW 1 |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 86 | #define __mem_pci |
| 87 | |
| 88 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ |
| 89 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
| 90 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ |
| 91 | |
| 92 | #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ |
| 93 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
| 94 | #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ |
Nobuhiro Iwamatsu | 04366d0 | 2009-07-08 11:42:19 +0900 | [diff] [blame] | 95 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE |
| 96 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE |
| 97 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 98 | #endif /* CONFIG_CMD_PCI */ |
| 99 | |
| 100 | #if defined(CONFIG_CMD_NET) |
Marcel Ziswiler | c7c1dbb | 2009-09-09 21:09:00 +0200 | [diff] [blame] | 101 | /* AX88796L Support(NE2000 base chip) */ |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 102 | #define CONFIG_DRIVER_AX88796L |
| 103 | #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 |
| 104 | #endif |
| 105 | |
| 106 | /* Compact flash Support */ |
Simon Glass | fc843a0 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 107 | #if defined(CONFIG_IDE) |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 108 | #define CONFIG_IDE_RESET 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 109 | #define CONFIG_SYS_PIO_MODE 1 |
| 110 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ |
| 111 | #define CONFIG_SYS_IDE_MAXDEVICE 1 |
| 112 | #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 |
| 113 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ |
| 114 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ |
| 115 | #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ |
| 116 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ |
Albert Aribaud | f2a37fc | 2010-08-08 05:17:05 +0530 | [diff] [blame] | 117 | #define CONFIG_IDE_SWAP_IO |
Simon Glass | fc843a0 | 2017-05-17 03:25:30 -0600 | [diff] [blame] | 118 | #endif /* CONFIG_IDE */ |
Yusuke Goda | c133c1f | 2008-03-11 12:55:12 +0900 | [diff] [blame] | 119 | |
| 120 | #endif /* __R7780RP_H */ |