blob: b14a3d34b1f66abf794d39cad2518dc31e746f4b [file] [log] [blame]
Wolfgang Denkb20d0032005-08-05 12:19:30 +02001/*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003,Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
5 *
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
28#include <common.h>
29#include <pci.h>
30#include <asm/processor.h>
Kumar Gala6bfa8f72008-08-26 23:52:07 -050031#include <asm/mmu.h>
Wolfgang Denkb20d0032005-08-05 12:19:30 +020032#include <asm/immap_85xx.h>
Kumar Gala6bfa8f72008-08-26 23:52:07 -050033#include <asm/fsl_ddr_sdram.h>
Wolfgang Denkb20d0032005-08-05 12:19:30 +020034#include <ioports.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060035#include <spd_sdram.h>
Wolfgang Denkb20d0032005-08-05 12:19:30 +020036#include <miiphy.h>
Ben Warren10efa022008-08-31 20:37:00 -070037#include <netdev.h>
Wolfgang Denkb20d0032005-08-05 12:19:30 +020038
39#if defined(CONFIG_DDR_ECC)
40extern void ddr_enable_ecc(unsigned int dram_size);
41#endif
42
Wolfgang Denkb20d0032005-08-05 12:19:30 +020043void local_bus_init(void);
44long int fixed_sdram(void);
45
46/*
47 * I/O Port configuration table
48 *
49 * if conf is 1, then that port pin will be configured at boot time
50 * according to the five values podr/pdir/ppar/psor/pdat for that entry
51 */
52
53const iop_conf_t iop_conf_tab[4][32] = {
54
55 /* Port A configuration */
56 { /* conf ppar psor pdir podr pdat */
57 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
58 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
59 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
60 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
61 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
62 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
63 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
64 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
65 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
66 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
67 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
68 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
69 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
70 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
71 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
72 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
73 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
74 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
75 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
76 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
77 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
78 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
79 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
80 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
81 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
82 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
83 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
84 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
85 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
86 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
87 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */
88 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
89 },
90
91 /* Port B configuration */
92 { /* conf ppar psor pdir podr pdat */
93 /* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
94 /* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
95 /* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
96 /* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
97 /* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
98 /* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
99 /* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
100 /* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
101 /* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
102 /* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
103 /* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
104 /* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
105 /* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
106 /* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
107 /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
108 /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
109 /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
110 /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
111 /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */
112 /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
113 /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
115 /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
116 /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
117 /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
119 /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
120 /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
121 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
122 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
123 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
124 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
125 },
126
127 /* Port C */
128 { /* conf ppar psor pdir podr pdat */
129 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
130 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
131 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
132 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
133 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
134 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
135 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
136 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
137 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
138 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
139 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
140 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
141 /* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
142 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
143 /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
144 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
145 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
146 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
147 /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
148 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
149 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
150 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
151 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
152 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
153 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
154 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
155 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
156 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
157 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
158 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
159 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
160 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
161 },
162
163 /* Port D */
164 { /* conf ppar psor pdir podr pdat */
165 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
166 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
167 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
168 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */
169 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */
170 /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */
171 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
172 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
173 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
174 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
175 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
176 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
177 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
178 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
179 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
180 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
181 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
182 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
183 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
184 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
185 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
186 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
187 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
188 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
189 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
190 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
191 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
192 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
193 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
194 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
195 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
196 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
197 }
198};
199
200
201int board_early_init_f (void)
202{
203 return 0;
204}
205
206void reset_phy (void)
207{
208}
209
210
211int checkboard (void)
212{
213 puts("Board: MicroSys PM856\n");
214
215#ifdef CONFIG_PCI
216 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
217 CONFIG_SYS_CLK_FREQ / 1000000);
218#else
219 printf(" PCI1: disabled\n");
220#endif
221
222 /*
223 * Initialize local bus.
224 */
225 local_bus_init();
226
227 return 0;
228}
229
230
Becky Bruce9973e3c2008-06-09 16:03:40 -0500231phys_size_t
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200232initdram(int board_type)
233{
234 long dram_size = 0;
Jon Loeligera30a5492008-03-04 10:03:03 -0600235
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200236
237 puts("Initializing\n");
238
239#if defined(CONFIG_DDR_DLL)
240 {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200242 int i,x;
243
244 x = 10;
245
246 /*
247 * Work around to stabilize DDR DLL
248 */
249 gur->ddrdllcr = 0x81000000;
250 asm("sync;isync;msync");
251 udelay (200);
252 while (gur->ddrdllcr != 0x81000100)
253 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200254 gur->devdisr = gur->devdisr | 0x00010000;
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200255 asm("sync;isync;msync");
256 for (i=0; i<x; i++)
257 ;
258 gur->devdisr = gur->devdisr & 0xfff7ffff;
259 asm("sync;isync;msync");
260 x++;
261 }
262 }
263#endif
264
265#if defined(CONFIG_SPD_EEPROM)
Kumar Gala6bfa8f72008-08-26 23:52:07 -0500266 dram_size = fsl_ddr_sdram();
267 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
268 dram_size *= 0x100000;
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200269#else
270 dram_size = fixed_sdram ();
271#endif
272
273#if defined(CONFIG_DDR_ECC)
274 /*
275 * Initialize and enable DDR ECC.
276 */
277 ddr_enable_ecc(dram_size);
278#endif
279
280 puts(" DDR: ");
281 return dram_size;
282}
283
284
285/*
286 * Initialize Local Bus
287 */
288
289void
290local_bus_init(void)
291{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
293 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200294
295 uint clkdiv;
296 uint lbc_hz;
297 sys_info_t sysinfo;
298
299 /*
300 * Errata LBC11.
301 * Fix Local Bus clock glitch when DLL is enabled.
302 *
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200303 * If localbus freq is < 66MHz, DLL bypass mode must be used.
304 * If localbus freq is > 133MHz, DLL can be safely enabled.
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200305 * Between 66 and 133, the DLL is enabled with an override workaround.
306 */
307
308 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800309 clkdiv = lbc->lcrr & LCRR_CLKDIV;
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200310 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
311
312 if (lbc_hz < 66) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313 lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000; /* DLL Bypass */
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200314
315 } else if (lbc_hz >= 133) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200317
318 } else {
319 /*
320 * On REV1 boards, need to change CLKDIV before enable DLL.
321 * Default CLKDIV is 8, change it to 4 temporarily.
322 */
323 uint pvr = get_pvr();
324 uint temp_lbcdll = 0;
325
326 if (pvr == PVR_85xx_REV1) {
327 /* FIXME: Justify the high bit here. */
328 lbc->lcrr = 0x10000004;
329 }
330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200332 udelay(200);
333
334 /*
335 * Sample LBC DLL ctrl reg, upshift it to set the
336 * override bits.
337 */
338 temp_lbcdll = gur->lbcdllcr;
339 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
340 asm("sync;isync;msync");
341 }
342}
343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#if defined(CONFIG_SYS_DRAM_TEST)
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200345int testdram (void)
346{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
348 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200349 uint *p;
350
351 printf("SDRAM test phase 1:\n");
352 for (p = pstart; p < pend; p++)
353 *p = 0xaaaaaaaa;
354
355 for (p = pstart; p < pend; p++) {
356 if (*p != 0xaaaaaaaa) {
357 printf ("SDRAM test fails at: %08x\n", (uint) p);
358 return 1;
359 }
360 }
361
362 printf("SDRAM test phase 2:\n");
363 for (p = pstart; p < pend; p++)
364 *p = 0x55555555;
365
366 for (p = pstart; p < pend; p++) {
367 if (*p != 0x55555555) {
368 printf ("SDRAM test fails at: %08x\n", (uint) p);
369 return 1;
370 }
371 }
372
373 printf("SDRAM test passed.\n");
374 return 0;
375}
376#endif
377
378
379#if !defined(CONFIG_SPD_EEPROM)
380/*************************************************************************
381 * fixed sdram init -- doesn't use serial presence detect.
382 ************************************************************************/
383long int fixed_sdram (void)
384{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385 #ifndef CONFIG_SYS_RAMBOOT
386 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200387
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
389 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
390 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
391 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
392 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
393 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200394 #if defined (CONFIG_DDR_ECC)
395 ddr->err_disable = 0x0000000D;
396 ddr->err_sbe = 0x00ff0000;
397 #endif
398 asm("sync;isync;msync");
399 udelay(500);
400 #if defined (CONFIG_DDR_ECC)
401 /* Enable ECC checking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200403 #else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200405 #endif
406 asm("sync; isync; msync");
407 udelay(500);
408 #endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200410}
411#endif /* !defined(CONFIG_SPD_EEPROM) */
412
413
414#if defined(CONFIG_PCI)
415/*
416 * Initialize PCI Devices, report devices found.
417 */
418
419#ifndef CONFIG_PCI_PNP
420static struct pci_config_table pci_mpc85xxads_config_table[] = {
421 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
422 PCI_IDSEL_NUMBER, PCI_ANY_ID,
423 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
424 PCI_ENET0_MEMADDR,
425 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
426 } },
427 { }
428};
429#endif
430
431
432static struct pci_controller hose = {
433#ifndef CONFIG_PCI_PNP
434 config_table: pci_mpc85xxads_config_table,
435#endif
436};
437
438#endif /* CONFIG_PCI */
439
440
441void
442pci_init_board(void)
443{
444#ifdef CONFIG_PCI
Wolfgang Denkb20d0032005-08-05 12:19:30 +0200445 pci_mpc85xx_init(&hose);
446#endif /* CONFIG_PCI */
447}
Ben Warren10efa022008-08-31 20:37:00 -0700448
449int board_eth_init(bd_t *bis)
450{
451 cpu_eth_init(bis); /* Intialize TSECs first */
452 return pci_eth_init(bis);
453}