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wdenk47d1a6e2002-11-03 00:01:44 +00001/*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2001 Josh Huber <huber@mclx.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/* U-Boot - Startup Code for PowerPC based Embedded Boards
27 *
28 *
29 * The processor starts at 0xfff00100 and the code is executed
30 * from flash. The code is organized to be at an other address
31 * in memory, but as long we don't jump around before relocating.
32 * board_init lies at a quite high address and when the cpu has
33 * jumped there, everything is ok.
34 */
35#include <config.h>
36#include <74xx_7xx.h>
Peter Tyser561858e2008-11-03 09:30:59 -060037#include <timestamp.h>
wdenk47d1a6e2002-11-03 00:01:44 +000038#include <version.h>
39
40#include <ppc_asm.tmpl>
41#include <ppc_defs.h>
42
43#include <asm/cache.h>
44#include <asm/mmu.h>
45
wdenk3a473b22004-01-03 00:43:19 +000046#if !defined(CONFIG_DB64360) && \
stroese0912e482004-12-16 18:10:54 +000047 !defined(CONFIG_DB64460) && \
Stefan Roese1eac2a72006-11-29 15:42:37 +010048 !defined(CONFIG_CPCI750) && \
49 !defined(CONFIG_P3Mx)
wdenk47d1a6e2002-11-03 00:01:44 +000050#include <galileo/gt64260R.h>
wdenk3a473b22004-01-03 00:43:19 +000051#endif
wdenk47d1a6e2002-11-03 00:01:44 +000052
53#ifndef CONFIG_IDENT_STRING
54#define CONFIG_IDENT_STRING ""
55#endif
56
57/* We don't want the MMU yet.
58*/
59#undef MSR_KERNEL
60/* Machine Check and Recoverable Interr. */
61#define MSR_KERNEL ( MSR_ME | MSR_RI )
62
63/*
64 * Set up GOT: Global Offset Table
65 *
66 * Use r14 to access the GOT
67 */
68 START_GOT
69 GOT_ENTRY(_GOT2_TABLE_)
70 GOT_ENTRY(_FIXUP_TABLE_)
71
72 GOT_ENTRY(_start)
73 GOT_ENTRY(_start_of_vectors)
74 GOT_ENTRY(_end_of_vectors)
75 GOT_ENTRY(transfer_to_handler)
76
wdenk3b57fe02003-05-30 12:48:29 +000077 GOT_ENTRY(__init_end)
wdenk47d1a6e2002-11-03 00:01:44 +000078 GOT_ENTRY(_end)
wdenk5d232d02003-05-22 22:52:13 +000079 GOT_ENTRY(__bss_start)
wdenk47d1a6e2002-11-03 00:01:44 +000080 END_GOT
81
82/*
83 * r3 - 1st arg to board_init(): IMMP pointer
84 * r4 - 2nd arg to board_init(): boot flag
85 */
86 .text
87 .long 0x27051956 /* U-Boot Magic Number */
88 .globl version_string
89version_string:
90 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -060091 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
wdenk47d1a6e2002-11-03 00:01:44 +000092 .ascii CONFIG_IDENT_STRING, "\0"
93
94 . = EXC_OFF_SYS_RESET
95 .globl _start
96_start:
97 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
98 b boot_cold
99 sync
100
101 . = EXC_OFF_SYS_RESET + 0x10
102
103 .globl _start_warm
104_start_warm:
105 li r21, BOOTFLAG_WARM /* Software reboot */
106 b boot_warm
107 sync
108
109 /* the boot code is located below the exception table */
110
111 .globl _start_of_vectors
112_start_of_vectors:
113
114/* Machine check */
115 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
116
117/* Data Storage exception. "Never" generated on the 860. */
118 STD_EXCEPTION(0x300, DataStorage, UnknownException)
119
120/* Instruction Storage exception. "Never" generated on the 860. */
121 STD_EXCEPTION(0x400, InstStorage, UnknownException)
122
123/* External Interrupt exception. */
124 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
125
126/* Alignment exception. */
127 . = 0x600
128Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200129 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk47d1a6e2002-11-03 00:01:44 +0000130 mfspr r4,DAR
131 stw r4,_DAR(r21)
132 mfspr r5,DSISR
133 stw r5,_DSISR(r21)
134 addi r3,r1,STACK_FRAME_OVERHEAD
135 li r20,MSR_KERNEL
136 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
137 lwz r6,GOT(transfer_to_handler)
138 mtlr r6
139 blrl
140.L_Alignment:
141 .long AlignmentException - _start + EXC_OFF_SYS_RESET
142 .long int_return - _start + EXC_OFF_SYS_RESET
143
144/* Program check exception */
145 . = 0x700
146ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200147 EXCEPTION_PROLOG(SRR0, SRR1)
wdenk47d1a6e2002-11-03 00:01:44 +0000148 addi r3,r1,STACK_FRAME_OVERHEAD
149 li r20,MSR_KERNEL
150 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
151 lwz r6,GOT(transfer_to_handler)
152 mtlr r6
153 blrl
154.L_ProgramCheck:
155 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
156 .long int_return - _start + EXC_OFF_SYS_RESET
157
158 /* No FPU on MPC8xx. This exception is not supposed to happen.
159 */
160 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
161
162 /* I guess we could implement decrementer, and may have
163 * to someday for timekeeping.
164 */
165 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
166 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
167 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
wdenk27b207f2003-07-24 23:38:38 +0000168 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
wdenk47d1a6e2002-11-03 00:01:44 +0000169 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
170
171 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
172 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
173
wdenk8bde7f72003-06-27 21:31:46 +0000174 /*
175 * On the MPC8xx, this is a software emulation interrupt. It
176 * occurs for all unimplemented and illegal instructions.
wdenk47d1a6e2002-11-03 00:01:44 +0000177 */
178 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
179
180 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
181 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
182 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
183 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
184
185 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
186 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
187 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
188 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
189 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
190 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
191 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
192
193 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
194 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
195 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
196 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
197
198 .globl _end_of_vectors
199_end_of_vectors:
200
201 . = 0x2000
202
203boot_cold:
204boot_warm:
205 /* disable everything */
206 li r0, 0
207 mtspr HID0, r0
208 sync
209 mtmsr 0
210 bl invalidate_bats
211 sync
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#ifdef CONFIG_SYS_L2
wdenk47d1a6e2002-11-03 00:01:44 +0000214 /* init the L2 cache */
215 addis r3, r0, L2_INIT@h
216 ori r3, r3, L2_INIT@l
217 sync
218 mtspr l2cr, r3
219#endif
220#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
221 .long 0x7e00066c
222 /*
wdenk8bde7f72003-06-27 21:31:46 +0000223 * dssall instruction, gas doesn't have it yet
224 * ...for altivec, data stream stop all this probably
225 * isn't needed unless we warm (software) reboot U-Boot
wdenk47d1a6e2002-11-03 00:01:44 +0000226 */
227#endif
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#ifdef CONFIG_SYS_L2
wdenk47d1a6e2002-11-03 00:01:44 +0000230 /* invalidate the L2 cache */
231 bl l2cache_invalidate
232 sync
233#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#ifdef CONFIG_SYS_BOARD_ASM_INIT
wdenk47d1a6e2002-11-03 00:01:44 +0000235 /* do early init */
236 bl board_asm_init
237#endif
238
239 /*
240 * Calculate absolute address in FLASH and jump there
241 *------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 lis r3, CONFIG_SYS_MONITOR_BASE@h
243 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
wdenk47d1a6e2002-11-03 00:01:44 +0000244 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
245 mtlr r3
246 blr
247
248in_flash:
249 /* let the C-code set up the rest */
250 /* */
251 /* Be careful to keep code relocatable ! */
252 /*------------------------------------------------------*/
253
254 /* perform low-level init */
255 /* sdram init, galileo init, etc */
256 /* r3: NHR bit from HID0 */
257
258 /* setup the bats */
259 bl setup_bats
260 sync
261
262 /*
263 * Cache must be enabled here for stack-in-cache trick.
264 * This means we need to enable the BATS.
265 * This means:
wdenk8bde7f72003-06-27 21:31:46 +0000266 * 1) for the EVB, original gt regs need to be mapped
wdenk47d1a6e2002-11-03 00:01:44 +0000267 * 2) need to have an IBAT for the 0xf region,
268 * we are running there!
wdenk8bde7f72003-06-27 21:31:46 +0000269 * Cache should be turned on after BATs, since by default
270 * everything is write-through.
271 * The init-mem BAT can be reused after reloc. The old
272 * gt-regs BAT can be reused after board_init_f calls
wdenkc837dcb2004-01-20 23:12:12 +0000273 * board_early_init_f (EVB only).
wdenk8bde7f72003-06-27 21:31:46 +0000274 */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100275#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
wdenk47d1a6e2002-11-03 00:01:44 +0000276 /* enable address translation */
277 bl enable_addr_trans
278 sync
279
280 /* enable and invalidate the data cache */
281 bl l1dcache_enable
282 sync
283#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#ifdef CONFIG_SYS_INIT_RAM_LOCK
wdenk47d1a6e2002-11-03 00:01:44 +0000285 bl lock_ram_in_cache
286 sync
287#endif
288
289 /* set up the stack pointer in our newly created
290 * cache-ram (r1) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
292 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
wdenk47d1a6e2002-11-03 00:01:44 +0000293
294 li r0, 0 /* Make room for stack frame header and */
295 stwu r0, -4(r1) /* clear final stack frame so that */
296 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
297
298 GET_GOT /* initialize GOT access */
299
300 /* run low-level CPU init code (from Flash) */
301 bl cpu_init_f
302 sync
303
304 mr r3, r21
305
306 /* r3: BOOTFLAG */
307 /* run 1st part of board init code (from Flash) */
308 bl board_init_f
309 sync
310
311 /* NOTREACHED */
312
313 .globl invalidate_bats
314invalidate_bats:
315 /* invalidate BATs */
316 mtspr IBAT0U, r0
317 mtspr IBAT1U, r0
318 mtspr IBAT2U, r0
319 mtspr IBAT3U, r0
Becky Bruce31d82672008-05-08 19:02:12 -0500320#ifdef CONFIG_HIGH_BATS
wdenk72755c72003-06-20 23:10:58 +0000321 mtspr IBAT4U, r0
322 mtspr IBAT5U, r0
323 mtspr IBAT6U, r0
324 mtspr IBAT7U, r0
325#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000326 isync
327 mtspr DBAT0U, r0
328 mtspr DBAT1U, r0
329 mtspr DBAT2U, r0
330 mtspr DBAT3U, r0
Becky Bruce31d82672008-05-08 19:02:12 -0500331#ifdef CONFIG_HIGH_BATS
wdenk8bde7f72003-06-27 21:31:46 +0000332 mtspr DBAT4U, r0
333 mtspr DBAT5U, r0
334 mtspr DBAT6U, r0
335 mtspr DBAT7U, r0
wdenk72755c72003-06-20 23:10:58 +0000336#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000337 isync
338 sync
339 blr
340
341 /* setup_bats - set them up to some initial state */
342 .globl setup_bats
343setup_bats:
344 addis r0, r0, 0x0000
345
346 /* IBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347 addis r4, r0, CONFIG_SYS_IBAT0L@h
348 ori r4, r4, CONFIG_SYS_IBAT0L@l
349 addis r3, r0, CONFIG_SYS_IBAT0U@h
350 ori r3, r3, CONFIG_SYS_IBAT0U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000351 mtspr IBAT0L, r4
352 mtspr IBAT0U, r3
353 isync
354
355 /* DBAT 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356 addis r4, r0, CONFIG_SYS_DBAT0L@h
357 ori r4, r4, CONFIG_SYS_DBAT0L@l
358 addis r3, r0, CONFIG_SYS_DBAT0U@h
359 ori r3, r3, CONFIG_SYS_DBAT0U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000360 mtspr DBAT0L, r4
361 mtspr DBAT0U, r3
362 isync
363
364 /* IBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365 addis r4, r0, CONFIG_SYS_IBAT1L@h
366 ori r4, r4, CONFIG_SYS_IBAT1L@l
367 addis r3, r0, CONFIG_SYS_IBAT1U@h
368 ori r3, r3, CONFIG_SYS_IBAT1U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000369 mtspr IBAT1L, r4
370 mtspr IBAT1U, r3
371 isync
372
373 /* DBAT 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374 addis r4, r0, CONFIG_SYS_DBAT1L@h
375 ori r4, r4, CONFIG_SYS_DBAT1L@l
376 addis r3, r0, CONFIG_SYS_DBAT1U@h
377 ori r3, r3, CONFIG_SYS_DBAT1U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000378 mtspr DBAT1L, r4
379 mtspr DBAT1U, r3
380 isync
381
382 /* IBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383 addis r4, r0, CONFIG_SYS_IBAT2L@h
384 ori r4, r4, CONFIG_SYS_IBAT2L@l
385 addis r3, r0, CONFIG_SYS_IBAT2U@h
386 ori r3, r3, CONFIG_SYS_IBAT2U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000387 mtspr IBAT2L, r4
388 mtspr IBAT2U, r3
389 isync
390
391 /* DBAT 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392 addis r4, r0, CONFIG_SYS_DBAT2L@h
393 ori r4, r4, CONFIG_SYS_DBAT2L@l
394 addis r3, r0, CONFIG_SYS_DBAT2U@h
395 ori r3, r3, CONFIG_SYS_DBAT2U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000396 mtspr DBAT2L, r4
397 mtspr DBAT2U, r3
398 isync
399
400 /* IBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401 addis r4, r0, CONFIG_SYS_IBAT3L@h
402 ori r4, r4, CONFIG_SYS_IBAT3L@l
403 addis r3, r0, CONFIG_SYS_IBAT3U@h
404 ori r3, r3, CONFIG_SYS_IBAT3U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000405 mtspr IBAT3L, r4
406 mtspr IBAT3U, r3
407 isync
408
409 /* DBAT 3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410 addis r4, r0, CONFIG_SYS_DBAT3L@h
411 ori r4, r4, CONFIG_SYS_DBAT3L@l
412 addis r3, r0, CONFIG_SYS_DBAT3U@h
413 ori r3, r3, CONFIG_SYS_DBAT3U@l
wdenk47d1a6e2002-11-03 00:01:44 +0000414 mtspr DBAT3L, r4
415 mtspr DBAT3U, r3
416 isync
417
Becky Bruce31d82672008-05-08 19:02:12 -0500418#ifdef CONFIG_HIGH_BATS
wdenk72755c72003-06-20 23:10:58 +0000419 /* IBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420 addis r4, r0, CONFIG_SYS_IBAT4L@h
421 ori r4, r4, CONFIG_SYS_IBAT4L@l
422 addis r3, r0, CONFIG_SYS_IBAT4U@h
423 ori r3, r3, CONFIG_SYS_IBAT4U@l
wdenk8bde7f72003-06-27 21:31:46 +0000424 mtspr IBAT4L, r4
425 mtspr IBAT4U, r3
426 isync
wdenk72755c72003-06-20 23:10:58 +0000427
428 /* DBAT 4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429 addis r4, r0, CONFIG_SYS_DBAT4L@h
430 ori r4, r4, CONFIG_SYS_DBAT4L@l
431 addis r3, r0, CONFIG_SYS_DBAT4U@h
432 ori r3, r3, CONFIG_SYS_DBAT4U@l
wdenk8bde7f72003-06-27 21:31:46 +0000433 mtspr DBAT4L, r4
434 mtspr DBAT4U, r3
435 isync
wdenk72755c72003-06-20 23:10:58 +0000436
wdenk8bde7f72003-06-27 21:31:46 +0000437 /* IBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438 addis r4, r0, CONFIG_SYS_IBAT5L@h
439 ori r4, r4, CONFIG_SYS_IBAT5L@l
440 addis r3, r0, CONFIG_SYS_IBAT5U@h
441 ori r3, r3, CONFIG_SYS_IBAT5U@l
wdenk8bde7f72003-06-27 21:31:46 +0000442 mtspr IBAT5L, r4
443 mtspr IBAT5U, r3
444 isync
wdenk72755c72003-06-20 23:10:58 +0000445
446 /* DBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447 addis r4, r0, CONFIG_SYS_DBAT5L@h
448 ori r4, r4, CONFIG_SYS_DBAT5L@l
449 addis r3, r0, CONFIG_SYS_DBAT5U@h
450 ori r3, r3, CONFIG_SYS_DBAT5U@l
wdenk8bde7f72003-06-27 21:31:46 +0000451 mtspr DBAT5L, r4
452 mtspr DBAT5U, r3
453 isync
wdenk72755c72003-06-20 23:10:58 +0000454
wdenk8bde7f72003-06-27 21:31:46 +0000455 /* IBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456 addis r4, r0, CONFIG_SYS_IBAT6L@h
457 ori r4, r4, CONFIG_SYS_IBAT6L@l
458 addis r3, r0, CONFIG_SYS_IBAT6U@h
459 ori r3, r3, CONFIG_SYS_IBAT6U@l
wdenk8bde7f72003-06-27 21:31:46 +0000460 mtspr IBAT6L, r4
461 mtspr IBAT6U, r3
462 isync
wdenk72755c72003-06-20 23:10:58 +0000463
464 /* DBAT 6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465 addis r4, r0, CONFIG_SYS_DBAT6L@h
466 ori r4, r4, CONFIG_SYS_DBAT6L@l
467 addis r3, r0, CONFIG_SYS_DBAT6U@h
468 ori r3, r3, CONFIG_SYS_DBAT6U@l
wdenk8bde7f72003-06-27 21:31:46 +0000469 mtspr DBAT6L, r4
470 mtspr DBAT6U, r3
471 isync
wdenk72755c72003-06-20 23:10:58 +0000472
wdenk8bde7f72003-06-27 21:31:46 +0000473 /* IBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474 addis r4, r0, CONFIG_SYS_IBAT7L@h
475 ori r4, r4, CONFIG_SYS_IBAT7L@l
476 addis r3, r0, CONFIG_SYS_IBAT7U@h
477 ori r3, r3, CONFIG_SYS_IBAT7U@l
wdenk8bde7f72003-06-27 21:31:46 +0000478 mtspr IBAT7L, r4
479 mtspr IBAT7U, r3
480 isync
wdenk72755c72003-06-20 23:10:58 +0000481
482 /* DBAT 7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483 addis r4, r0, CONFIG_SYS_DBAT7L@h
484 ori r4, r4, CONFIG_SYS_DBAT7L@l
485 addis r3, r0, CONFIG_SYS_DBAT7U@h
486 ori r3, r3, CONFIG_SYS_DBAT7U@l
wdenk8bde7f72003-06-27 21:31:46 +0000487 mtspr DBAT7L, r4
488 mtspr DBAT7U, r3
489 isync
wdenk72755c72003-06-20 23:10:58 +0000490#endif
491
wdenk47d1a6e2002-11-03 00:01:44 +0000492 /* bats are done, now invalidate the TLBs */
493
494 addis r3, 0, 0x0000
495 addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
496
497 isync
498
499tlblp:
500 tlbie r3
501 sync
502 addi r3, r3, 0x1000
503 cmp 0, 0, r3, r5
504 blt tlblp
505
506 blr
507
508 .globl enable_addr_trans
509enable_addr_trans:
510 /* enable address translation */
511 mfmsr r5
512 ori r5, r5, (MSR_IR | MSR_DR)
513 mtmsr r5
514 isync
515 blr
516
517 .globl disable_addr_trans
518disable_addr_trans:
519 /* disable address translation */
520 mflr r4
521 mfmsr r3
522 andi. r0, r3, (MSR_IR | MSR_DR)
523 beqlr
524 andc r3, r3, r0
525 mtspr SRR0, r4
526 mtspr SRR1, r3
527 rfi
528
529/*
530 * This code finishes saving the registers to the exception frame
531 * and jumps to the appropriate handler for the exception.
532 * Register r21 is pointer into trap frame, r1 has new stack pointer.
533 */
534 .globl transfer_to_handler
535transfer_to_handler:
536 stw r22,_NIP(r21)
537 lis r22,MSR_POW@h
538 andc r23,r23,r22
539 stw r23,_MSR(r21)
540 SAVE_GPR(7, r21)
541 SAVE_4GPRS(8, r21)
542 SAVE_8GPRS(12, r21)
543 SAVE_8GPRS(24, r21)
544 mflr r23
545 andi. r24,r23,0x3f00 /* get vector offset */
546 stw r24,TRAP(r21)
547 li r22,0
548 stw r22,RESULT(r21)
549 mtspr SPRG2,r22 /* r1 is now kernel sp */
550 lwz r24,0(r23) /* virtual address of handler */
551 lwz r23,4(r23) /* where to go when done */
552 mtspr SRR0,r24
553 mtspr SRR1,r20
554 mtlr r23
555 SYNC
556 rfi /* jump to handler, enable MMU */
557
558int_return:
559 mfmsr r28 /* Disable interrupts */
560 li r4,0
561 ori r4,r4,MSR_EE
562 andc r28,r28,r4
563 SYNC /* Some chip revs need this... */
564 mtmsr r28
565 SYNC
566 lwz r2,_CTR(r1)
567 lwz r0,_LINK(r1)
568 mtctr r2
569 mtlr r0
570 lwz r2,_XER(r1)
571 lwz r0,_CCR(r1)
572 mtspr XER,r2
573 mtcrf 0xFF,r0
574 REST_10GPRS(3, r1)
575 REST_10GPRS(13, r1)
576 REST_8GPRS(23, r1)
577 REST_GPR(31, r1)
578 lwz r2,_NIP(r1) /* Restore environment */
579 lwz r0,_MSR(r1)
580 mtspr SRR0,r2
581 mtspr SRR1,r0
582 lwz r0,GPR0(r1)
583 lwz r2,GPR2(r1)
584 lwz r1,GPR1(r1)
585 SYNC
586 rfi
587
588 .globl dc_read
589dc_read:
590 blr
591
592 .globl get_pvr
593get_pvr:
594 mfspr r3, PVR
595 blr
596
597/*-----------------------------------------------------------------------*/
598/*
599 * void relocate_code (addr_sp, gd, addr_moni)
600 *
601 * This "function" does not return, instead it continues in RAM
602 * after relocating the monitor code.
603 *
604 * r3 = dest
605 * r4 = src
606 * r5 = length in bytes
607 * r6 = cachelinesize
608 */
609 .globl relocate_code
610relocate_code:
611 mr r1, r3 /* Set new stack pointer */
612 mr r9, r4 /* Save copy of Global Data pointer */
613 mr r10, r5 /* Save copy of Destination Address */
614
615 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200616 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
617 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +0000618 lwz r5, GOT(__init_end)
619 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
wdenk47d1a6e2002-11-03 00:01:44 +0000621
622 /*
623 * Fix GOT pointer:
624 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200625 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
wdenk47d1a6e2002-11-03 00:01:44 +0000626 *
627 * Offset:
628 */
629 sub r15, r10, r4
630
631 /* First our own GOT */
632 add r14, r14, r15
633 /* then the one used by the C code */
634 add r30, r30, r15
635
636 /*
637 * Now relocate code
638 */
639#ifdef CONFIG_ECC
640 bl board_relocate_rom
641 sync
642 mr r3, r10 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200643 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
644 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
wdenk3b57fe02003-05-30 12:48:29 +0000645 lwz r5, GOT(__init_end)
646 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200647 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
wdenk47d1a6e2002-11-03 00:01:44 +0000648#else
649 cmplw cr1,r3,r4
650 addi r0,r5,3
651 srwi. r0,r0,2
652 beq cr1,4f /* In place copy is not necessary */
653 beq 7f /* Protect against 0 count */
654 mtctr r0
655 bge cr1,2f
656
657 la r8,-4(r4)
658 la r7,-4(r3)
6591: lwzu r0,4(r8)
660 stwu r0,4(r7)
661 bdnz 1b
662 b 4f
663
6642: slwi r0,r0,2
665 add r8,r4,r0
666 add r7,r3,r0
6673: lwzu r0,-4(r8)
668 stwu r0,-4(r7)
669 bdnz 3b
670#endif
671/*
672 * Now flush the cache: note that we must start from a cache aligned
673 * address. Otherwise we might miss one cache line.
674 */
6754: cmpwi r6,0
676 add r5,r3,r5
677 beq 7f /* Always flush prefetch queue in any case */
678 subi r0,r6,1
679 andc r3,r3,r0
680 mr r4,r3
6815: dcbst 0,r4
682 add r4,r4,r6
683 cmplw r4,r5
684 blt 5b
685 sync /* Wait for all dcbst to complete on bus */
686 mr r4,r3
6876: icbi 0,r4
688 add r4,r4,r6
689 cmplw r4,r5
690 blt 6b
6917: sync /* Wait for all icbi to complete on bus */
692 isync
693
694/*
695 * We are done. Do not return, instead branch to second part of board
696 * initialization, now running from RAM.
697 */
698 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
699 mtlr r0
700 blr
701
702in_ram:
703#ifdef CONFIG_ECC
704 bl board_init_ecc
705#endif
706 /*
707 * Relocation Function, r14 point to got2+0x8000
708 *
wdenk8bde7f72003-06-27 21:31:46 +0000709 * Adjust got2 pointers, no need to check for 0, this code
710 * already puts a few entries in the table.
wdenk47d1a6e2002-11-03 00:01:44 +0000711 */
712 li r0,__got2_entries@sectoff@l
713 la r3,GOT(_GOT2_TABLE_)
714 lwz r11,GOT(_GOT2_TABLE_)
715 mtctr r0
716 sub r11,r3,r11
717 addi r3,r3,-4
7181: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200719 cmpwi r0,0
720 beq- 2f
wdenk47d1a6e2002-11-03 00:01:44 +0000721 add r0,r0,r11
722 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02007232: bdnz 1b
wdenk47d1a6e2002-11-03 00:01:44 +0000724
725 /*
wdenk8bde7f72003-06-27 21:31:46 +0000726 * Now adjust the fixups and the pointers to the fixups
wdenk47d1a6e2002-11-03 00:01:44 +0000727 * in case we need to move ourselves again.
728 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200729 li r0,__fixup_entries@sectoff@l
wdenk47d1a6e2002-11-03 00:01:44 +0000730 lwz r3,GOT(_FIXUP_TABLE_)
731 cmpwi r0,0
732 mtctr r0
733 addi r3,r3,-4
734 beq 4f
7353: lwzu r4,4(r3)
736 lwzux r0,r4,r11
737 add r0,r0,r11
738 stw r10,0(r3)
739 stw r0,0(r4)
740 bdnz 3b
7414:
742/* clear_bss: */
743 /*
744 * Now clear BSS segment
745 */
wdenk5d232d02003-05-22 22:52:13 +0000746 lwz r3,GOT(__bss_start)
wdenk47d1a6e2002-11-03 00:01:44 +0000747 lwz r4,GOT(_end)
748
749 cmplw 0, r3, r4
750 beq 6f
751
752 li r0, 0
7535:
754 stw r0, 0(r3)
755 addi r3, r3, 4
756 cmplw 0, r3, r4
757 bne 5b
7586:
759 mr r3, r10 /* Destination Address */
wdenk3a473b22004-01-03 00:43:19 +0000760#if defined(CONFIG_AMIGAONEG3SE) || \
761 defined(CONFIG_DB64360) || \
stroese0912e482004-12-16 18:10:54 +0000762 defined(CONFIG_DB64460) || \
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200763 defined(CONFIG_CPCI750) || \
Stefan Roese1eac2a72006-11-29 15:42:37 +0100764 defined(CONFIG_PPMC7XX) || \
765 defined(CONFIG_P3Mx)
wdenk7c7a23b2002-12-07 00:20:59 +0000766 mr r4, r9 /* Use RAM copy of the global data */
767#endif
wdenk47d1a6e2002-11-03 00:01:44 +0000768 bl after_reloc
769
770 /* not reached - end relocate_code */
771/*-----------------------------------------------------------------------*/
772
wdenk47d1a6e2002-11-03 00:01:44 +0000773 /*
774 * Copy exception vector code to low memory
775 *
776 * r3: dest_addr
777 * r7: source address, r8: end address, r9: target address
778 */
779 .globl trap_init
780trap_init:
781 lwz r7, GOT(_start)
782 lwz r8, GOT(_end_of_vectors)
783
wdenk682011f2003-06-03 23:54:09 +0000784 li r9, 0x100 /* reset vector always at 0x100 */
wdenk47d1a6e2002-11-03 00:01:44 +0000785
786 cmplw 0, r7, r8
787 bgelr /* return if r7>=r8 - just in case */
788
789 mflr r4 /* save link register */
7901:
791 lwz r0, 0(r7)
792 stw r0, 0(r9)
793 addi r7, r7, 4
794 addi r9, r9, 4
795 cmplw 0, r7, r8
796 bne 1b
797
798 /*
799 * relocate `hdlr' and `int_return' entries
800 */
801 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
802 li r8, Alignment - _start + EXC_OFF_SYS_RESET
8032:
804 bl trap_reloc
805 addi r7, r7, 0x100 /* next exception vector */
806 cmplw 0, r7, r8
807 blt 2b
808
809 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
810 bl trap_reloc
811
812 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
813 bl trap_reloc
814
815 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
816 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
8173:
818 bl trap_reloc
819 addi r7, r7, 0x100 /* next exception vector */
820 cmplw 0, r7, r8
821 blt 3b
822
823 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
824 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
8254:
826 bl trap_reloc
827 addi r7, r7, 0x100 /* next exception vector */
828 cmplw 0, r7, r8
829 blt 4b
830
831 /* enable execptions from RAM vectors */
832 mfmsr r7
833 li r8,MSR_IP
834 andc r7,r7,r8
835 mtmsr r7
836
837 mtlr r4 /* restore link register */
838 blr
839
840 /*
841 * Function: relocate entries for one exception vector
842 */
843trap_reloc:
844 lwz r0, 0(r7) /* hdlr ... */
845 add r0, r0, r3 /* ... += dest_addr */
846 stw r0, 0(r7)
847
848 lwz r0, 4(r7) /* int_return ... */
849 add r0, r0, r3 /* ... += dest_addr */
850 stw r0, 4(r7)
851
852 sync
853 isync
854
855 blr
856
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200857#ifdef CONFIG_SYS_INIT_RAM_LOCK
wdenk47d1a6e2002-11-03 00:01:44 +0000858lock_ram_in_cache:
859 /* Allocate Initial RAM in data cache.
860 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200861 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
862 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Dave Liud685b742008-10-23 21:59:35 +0800863 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200864 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Dave Liud685b742008-10-23 21:59:35 +0800865 mtctr r4
wdenk47d1a6e2002-11-03 00:01:44 +00008661:
867 dcbz r0, r3
868 addi r3, r3, 32
869 bdnz 1b
870
871 /* Lock the data cache */
872 mfspr r0, HID0
873 ori r0, r0, 0x1000
874 sync
875 mtspr HID0, r0
876 sync
877 blr
878
879.globl unlock_ram_in_cache
880unlock_ram_in_cache:
881 /* invalidate the INIT_RAM section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200882 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
883 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Dave Liud685b742008-10-23 21:59:35 +0800884 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200885 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Dave Liud685b742008-10-23 21:59:35 +0800886 mtctr r4
wdenk47d1a6e2002-11-03 00:01:44 +00008871: icbi r0, r3
888 addi r3, r3, 32
889 bdnz 1b
890 sync /* Wait for all icbi to complete on bus */
891 isync
892
893 /* Unlock the data cache and invalidate it */
894 mfspr r0, HID0
895 li r3,0x1000
896 andc r0,r0,r3
897 li r3,0x0400
898 or r0,r0,r3
899 sync
900 mtspr HID0, r0
901 sync
902 blr
903#endif