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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 29c6fbe0471afd7ffa41fcb2103eec5b53294897 / . / include / configs / pcm030.h
blob: c663b544d19bbea8b8655709d64c6469e366bf81 [file] [log] [blame]
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]1/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
34
35/*-----------------------------------------------------------------------------
36High Level Configuration Options
37(easy to change)
38-----------------------------------------------------------------------------*/
39#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
40#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
41#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
42#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
43 /* FEC configuration and IDE */
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200[diff] [blame]44
45/*
46 * Valid values for CONFIG_SYS_TEXT_BASE are:
47 * 0xFFF00000 boot high (standard configuration)
48 * 0xFF000000 boot low
49 * 0x00100000 boot from RAM (for testing only)
50 */
51#ifndef CONFIG_SYS_TEXT_BASE
52#define CONFIG_SYS_TEXT_BASE 0xFFF00000
53#endif
54
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]55#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
56#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
57#define BOOTFLAG_WARM 0x02 /* Software reboot */
58
59/*-----------------------------------------------------------------------------
60Serial console configuration
61-----------------------------------------------------------------------------*/
62#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
63 /*define gps port conf. */
64 /* register later on to */
65 /*enable UART function! */
66#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
67#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
68
69/*
70 * Command line configuration.
71 */
72#include <config_cmd_default.h>
73
74#define CONFIG_CMD_DATE
75#define CONFIG_CMD_DHCP
76#define CONFIG_CMD_EEPROM
77#define CONFIG_CMD_I2C
78#define CONFIG_CMD_JFFS2
79#define CONFIG_CMD_MII
80#define CONFIG_CMD_NFS
81#define CONFIG_CMD_PCI
82
83#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
84
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]85#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low */
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]86#define CONFIG_SYS_LOWBOOT 1
87#endif
88/* RAMBOOT will be defined automatically in memory section */
89
90#define CONFIG_JFFS2_CMDLINE
91#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
92#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
93 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
94
95/*-----------------------------------------------------------------------------
96Autobooting
97-----------------------------------------------------------------------------*/
98#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
99#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
100 /* even with bootdelay=0 */
101#undef CONFIG_BOOTARGS
102
103
104#define CONFIG_PREBOOT "echo;" \
105 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
106 "mount root filesystem over NFS;" \
107 "echo"
108
109#define CONFIG_EXTRA_ENV_SETTINGS \
110 "netdev=eth0\0" \
111 "uimage=uImage-pcm030\0" \
112 "oftree=oftree-pcm030.dtb\0" \
113 "jffs2=root-pcm030.jffs2\0" \
114 "uboot=u-boot-pcm030.bin\0" \
115 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
116 " $(mtdparts) rw\0" \
117 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
118 " rootfstype=jffs2\0" \
119 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
120 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
121 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
122 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
123 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
124 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
125 "0xfff40000\0" \
126 " cp.b 0x400000 0xff040000 $(filesize)\0" \
127 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
128 "cp.b 0x400000 0xff200000 $(filesize)\0" \
129 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
130 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
131 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
132 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
133 "unlock=yes\0" \
134 ""
135
136#define CONFIG_BOOTCOMMAND "run bcmd_flash"
137
138/*--------------------------------------------------------------------------
139IPB Bus clocking configuration.
140 ---------------------------------------------------------------------------*/
141#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
142
143/*-------------------------------------------------------------------------
144 * PCI Mapping:
145 * 0x40000000 - 0x4fffffff - PCI Memory
146 * 0x50000000 - 0x50ffffff - PCI IO Space
147 * -----------------------------------------------------------------------*/
148#define CONFIG_PCI 1
149#define CONFIG_PCI_PNP 1
150#define CONFIG_PCI_SCAN_SHOW 1
151#define CONFIG_PCI_MEM_BUS 0x40000000
152#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
153#define CONFIG_PCI_MEM_SIZE 0x10000000
154#define CONFIG_PCI_IO_BUS 0x50000000
155#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
156#define CONFIG_PCI_IO_SIZE 0x01000000
157#define CONFIG_SYS_XLB_PIPELINING 1
158
159/*---------------------------------------------------------------------------
160 I2C configuration
161---------------------------------------------------------------------------*/
162#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
163#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
164#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
165#define CONFIG_SYS_I2C_SLAVE 0x7F
166
167/*---------------------------------------------------------------------------
168 EEPROM CAT24WC32 configuration
169---------------------------------------------------------------------------*/
170#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
171#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
172#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
173#define CONFIG_SYS_EEPROM_SIZE 2048
174#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
175#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
176
177/*---------------------------------------------------------------------------
178RTC configuration
179---------------------------------------------------------------------------*/
180#define RTC
181#define CONFIG_RTC_PCF8563 1
182#define CONFIG_SYS_I2C_RTC_ADDR 0x51
183
184/*---------------------------------------------------------------------------
185 Flash configuration
186---------------------------------------------------------------------------*/
187
188#define CONFIG_SYS_FLASH_BASE 0xff000000
189#define CONFIG_SYS_FLASH_SIZE 0x01000000
190#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
191
192#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
193#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
194#define CONFIG_SYS_FLASH_EMPTY_INFO
195#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
196#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
197 /* (= chip selects) */
198#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
199
200/*
201 * Use also hardware protection. This seems required, as the BDI uses
202 * hardware protection. Without this, U-Boot can't work with this sectors,
203 * as its protection is software only by default
204 */
205#define CONFIG_SYS_FLASH_PROTECTION 1
206
207/*---------------------------------------------------------------------------
208 Environment settings
209---------------------------------------------------------------------------*/
210
211/* pcm030 ships with environment is EEPROM by default */
212#define CONFIG_ENV_IS_IN_EEPROM 1
213#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
214 /*beginning of the EEPROM */
215#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
216
217#define CONFIG_ENV_OVERWRITE 1
218
219/*-----------------------------------------------------------------------------
220 Memory map
221-----------------------------------------------------------------------------*/
222#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
223 /* bootloader or debugger config */
224#define CONFIG_SYS_SDRAM_BASE 0x00000000
225#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
226/* Use SRAM until RAM will be available */
227#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
228#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used */
229 /* area in DPRAM */
230#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes */
231 /* reserved for initial data */
232#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
233 CONFIG_SYS_GBL_DATA_SIZE)
234#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
235
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]236#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]237#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
238# define CONFIG_SYS_RAMBOOT 1
239#endif
240
241#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
242#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
243#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
244
245/*-----------------------------------------------------------------------------
246 Ethernet configuration
247-----------------------------------------------------------------------------*/
248#define CONFIG_MPC5xxx_FEC 1
249#define CONFIG_MPC5xxx_FEC_MII100
250#define CONFIG_PHY_ADDR 0x01
251
252/*---------------------------------------------------------------------------
253 GPIO configuration
254 ---------------------------------------------------------------------------*/
255
256/* GPIO port configuration
257 *
258 * Pin mapping:
259 *
260 * [29:31] = 01x
261 * PSC1_0 -> AC97 SDATA out
262 * PSC1_1 -> AC97 SDTA in
263 * PSC1_2 -> AC97 SYNC out
264 * PSC1_3 -> AC97 bitclock out
265 * PSC1_4 -> AC97 reset out
266 *
267 * [25:27] = 001
268 * PSC2_0 -> CAN 1 Tx out
269 * PSC2_1 -> CAN 1 Rx in
270 * PSC2_2 -> CAN 2 Tx out
271 * PSC2_3 -> CAN 2 Rx in
272 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
273 *
274 *
275 * [20:23] = 1100
276 * PSC3_0 -> UART Tx out
277 * PSC3_1 -> UART Rx in
278 * PSC3_2 -> UART RTS (in/out FIXME)
279 * PSC3_3 -> UART CTS (in/out FIXME)
280 * PSC3_4 -> LocalPlus Bus CS6 \
281 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
282 * PSC3_6 -> dedicated SPI MOSI out (master case)
283 * PSC3_7 -> dedicated SPI MISO in (master case)
284 * PSC3_8 -> dedicated SPI SS out (master case)
285 * PSC3_9 -> dedicated SPI CLK out (master case)
286 *
287 * [18:19] = 01
288 * USB_0 -> USB OE out
289 * USB_1 -> USB Tx- out
290 * USB_2 -> USB Tx+ out
291 * USB_3 -> USB RxD (in/out FIXME)
292 * USB_4 -> USB Rx+ in
293 * USB_5 -> USB Rx- in
294 * USB_6 -> USB PortPower out
295 * USB_7 -> USB speed out
296 * USB_8 -> USB suspend (in/out FIXME)
297 * USB_9 -> USB overcurrent in
298 *
299 * [17] = 0
300 * USB differential mode
301 *
302 * [16] = 0
303 * PCI enabled
304 *
305 * [12:15] = 0101
306 * ETH_0 -> ETH Txen
307 * ETH_1 -> ETH TxD0
308 * ETH_2 -> ETH TxD1
309 * ETH_3 -> ETH TxD2
310 * ETH_4 -> ETH TxD3
311 * ETH_5 -> ETH Txerr
312 * ETH_6 -> ETH MDC
313 * ETH_7 -> ETH MDIO
314 * ETH_8 -> ETH RxDv
315 * ETH_9 -> ETH RxCLK
316 * ETH_10 -> ETH Collision
317 * ETH_11 -> ETH TxD
318 * ETH_12 -> ETH RxD0
319 * ETH_13 -> ETH RxD1
320 * ETH_14 -> ETH RxD2
321 * ETH_15 -> ETH RxD3
322 * ETH_16 -> ETH Rxerr
323 * ETH_17 -> ETH CRS
324 *
325 * [9:11] = 101
326 * PSC6_0 -> UART RxD in
327 * PSC6_1 -> UART CTS (in/out FIXME)
328 * PSC6_2 -> UART TxD out
329 * PSC6_3 -> UART RTS (in/out FIXME)
330 *
331 * [2:3/6:7] = 00/11
332 * TMR_0 -> ATA_CS0 out
333 * TMR_1 -> ATA_CS1 out
334 * TMR_2 -> GPIO
335 * TMR_3 -> GPIO
336 * TMR_4 -> GPIO
337 * TMR_5 -> GPIO
338 * TMR_6 -> GPIO
339 * TMR_7 -> GPIO
340 * I2C_0 -> I2C 1 Clock out
341 * I2C_1 -> I2C 1 IO in/out
342 * I2C_2 -> I2C 2 Clock out
343 * I2C_3 -> I2C 2 IO in/out
344 *
345 * [4] = 1
346 * PSC3_5 is used as CS7
347 *
348 * [5] = 1
349 * PSC3_4 is used as CS6
350 *
351 * [1] = 0
352 * gpio_wkup_7 is GPIO
353 *
354 * [0] = 0
355 * gpio_wkup_6 is GPIO
356 *
357 */
358#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
359
360/*-----------------------------------------------------------------------------
361 Miscellaneous configurable options
362-------------------------------------------------------------------------------*/
363#define CONFIG_SYS_LONGHELP /* undef to save memory */
364#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
365
366#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
367
368#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
369#if defined(CONFIG_CMD_KGDB)
370#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
371#endif
372
373#if defined(CONFIG_CMD_KGDB)
374#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
375#else
376#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
377#endif
378#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
379 /* Print Buffer Size */
380#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
381#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
382
383#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
384#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
385
386#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
387#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
388
389#define CONFIG_DISPLAY_BOARDINFO 1
390
391/*-----------------------------------------------------------------------------
392 Various low-level settings
393-----------------------------------------------------------------------------*/
394#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
395#define CONFIG_SYS_HID0_FINAL HID0_ICE
396
397/* no burst access on the LPB */
398#define CONFIG_SYS_CS_BURST 0x00000000
399/* one deadcycle for the 33MHz statemachine */
400#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
401/* one additional waitstate for the 33MHz statemachine */
402#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
403#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
404#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
405
406#define CONFIG_SYS_RESET_ADDRESS 0xff000000
407
408/*-----------------------------------------------------------------------
409 * USB stuff
410 *-----------------------------------------------------------------------
411 */
412#define CONFIG_USB_CLOCK 0x0001BBBB
413#define CONFIG_USB_CONFIG 0x00001000
414
415/*---------------------------------------------------------------------------
416 IDE/ATA stuff Supports IDE harddisk
417----------------------------------------------------------------------------*/
418
419#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
420#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
421#undef CONFIG_IDE_LED /* LED for ide not supported */
422#define CONFIG_SYS_ATA_CS_ON_TIMER01
423#define CONFIG_IDE_RESET 1 /* reset for ide supported */
424#define CONFIG_IDE_PREINIT
425#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
426#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
427#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
428#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
429/* Offset for data I/O */
430#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
431/* Offset for normal register accesses */
432#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
433/* Offset for alternate registers */
434#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
435/* Interval between registers */
436#define CONFIG_SYS_ATA_STRIDE 4
437#define CONFIG_ATAPI 1
438
439/* we enable IDE and FAT support, so we also need partition support */
440#define CONFIG_DOS_PARTITION 1
441
442/* USB */
443#define CONFIG_USB_OHCI
444#define CONFIG_USB_STORAGE
445
446/* pass open firmware flat tree */
447#define CONFIG_OF_LIBFDT 1
448#define CONFIG_OF_BOARD_SETUP 1
449
450#define OF_CPU "PowerPC,5200@0"
451#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
452#define OF_SOC "soc5200@f0000000"
453#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
454
455#endif /* __CONFIG_H */