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wdenk8ed96042005-01-09 23:16:25 +00001/*
2 * (C) Copyright 2004
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
6 *
7 * Configuration settings for the 242x TI H4 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 */
34#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
35#define CONFIG_OMAP 1 /* in a TI OMAP core */
36#define CONFIG_OMAP2420 1 /* which is in a 2420 */
37#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
wdenk082acfd2005-01-10 00:01:04 +000038/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
39/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
wdenk8ed96042005-01-09 23:16:25 +000040
Wolfgang Denk8ae86b72011-02-04 14:25:17 +010041#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
42
wdenk289f9322005-01-12 00:15:14 +000043/* Clock config to target*/
Wolfgang Denk49a75812005-09-25 18:41:04 +020044#define PRCM_CONFIG_II 1
Wolfgang Denk716c1dc2005-09-25 18:49:35 +020045/* #define PRCM_CONFIG_III 1 */
wdenk8ed96042005-01-09 23:16:25 +000046
47#include <asm/arch/omap2420.h> /* get chip and board defs */
48
wdenk289f9322005-01-12 00:15:14 +000049/* On H4, NOR and NAND flash are mutual exclusive.
50 Define this if you want to use NAND
51 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052/*#define CONFIG_SYS_NAND_BOOT */
wdenk289f9322005-01-12 00:15:14 +000053
wdenk8ed96042005-01-09 23:16:25 +000054#ifdef CONFIG_APTIX
55#define V_SCLK 1500000
56#else
57#define V_SCLK 12000000
58#endif
59
60/* input clock of PLL */
61/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
62#define CONFIG_SYS_CLK_FREQ V_SCLK
63
wdenk8ed96042005-01-09 23:16:25 +000064#define CONFIG_MISC_INIT_R
65
66#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
67#define CONFIG_SETUP_MEMORY_TAGS 1
68#define CONFIG_INITRD_TAG 1
wdenk289f9322005-01-12 00:15:14 +000069#define CONFIG_REVISION_TAG 1
Hunter, Jonfaad9c02013-04-03 09:35:35 +000070#define CONFIG_OF_LIBFDT
wdenk8ed96042005-01-09 23:16:25 +000071
72/*
73 * Size of malloc() pool
74 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020075#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
wdenk8ed96042005-01-09 23:16:25 +000077
78/*
79 * Hardware drivers
80 */
wdenk082acfd2005-01-10 00:01:04 +000081
wdenk8ed96042005-01-09 23:16:25 +000082/*
83 * SMC91c96 Etherent
84 */
Nishanth Menonac6b3622009-10-16 00:06:37 -050085#define CONFIG_LAN91C96
wdenk8ed96042005-01-09 23:16:25 +000086#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
87#define CONFIG_LAN91C96_EXT_PHY
88
89/*
90 * NS16550 Configuration
91 */
92#ifdef CONFIG_APTIX
93#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
94#else
95#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
96#endif
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_NS16550
99#define CONFIG_SYS_NS16550_SERIAL
100#define CONFIG_SYS_NS16550_REG_SIZE (-4)
101#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
102#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
wdenk8ed96042005-01-09 23:16:25 +0000103
104/*
105 * select serial console configuration
106 */
107#define CONFIG_SERIAL1 1 /* UART1 on H4 */
108
109 /*
110 * I2C configuration
111 */
112#define CONFIG_HARD_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_I2C_SPEED 100000
114#define CONFIG_SYS_I2C_SLAVE 1
wdenk8ed96042005-01-09 23:16:25 +0000115#define CONFIG_DRIVER_OMAP24XX_I2C
116
117/* allow to overwrite serial and ethaddr */
118#define CONFIG_ENV_OVERWRITE
119#define CONFIG_CONS_INDEX 1
120#define CONFIG_BAUDRATE 115200
wdenk8ed96042005-01-09 23:16:25 +0000121
Jon Loeligera5cb2302007-07-04 22:33:13 -0500122/*
123 * Command line configuration.
124 */
125#include <config_cmd_default.h>
126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#ifdef CONFIG_SYS_NAND_BOOT
Jon Loeligera5cb2302007-07-04 22:33:13 -0500128 #define CONFIG_CMD_DHCP
129 #define CONFIG_CMD_I2C
130 #define CONFIG_CMD_NAND
131 #define CONFIG_CMD_JFFS2
132#else
133 #define CONFIG_CMD_DHCP
134 #define CONFIG_CMD_I2C
135 #define CONFIG_CMD_JFFS2
136
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200137 #undef CONFIG_CMD_SOURCE
Jon Loeligera5cb2302007-07-04 22:33:13 -0500138#endif
139
140
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500141/*
142 * BOOTP options
143 */
144#define CONFIG_BOOTP_SUBNETMASK
145#define CONFIG_BOOTP_GATEWAY
146#define CONFIG_BOOTP_HOSTNAME
147#define CONFIG_BOOTP_BOOTPATH
148
wdenk8ed96042005-01-09 23:16:25 +0000149#define CONFIG_BOOTDELAY 3
150
151#ifdef NFS_BOOT_DEFAULTS
152#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
153#else
154#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
155#endif
156
157#define CONFIG_NETMASK 255.255.254.0
158#define CONFIG_IPADDR 128.247.77.90
159#define CONFIG_SERVERIP 128.247.77.158
160#define CONFIG_BOOTFILE "uImage"
161
162/*
163 * Miscellaneous configurable options
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LONGHELP /* undef to save memory */
Robert P. J. Day1270ec12009-12-12 12:10:33 -0500166#ifdef CONFIG_APTIX
167# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # "
168#else
169# define CONFIG_SYS_PROMPT "OMAP242x H4 # "
170#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk8ed96042005-01-09 23:16:25 +0000172/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
174#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
175#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk8ed96042005-01-09 23:16:25 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
178#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
wdenk8ed96042005-01-09 23:16:25 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
wdenk8ed96042005-01-09 23:16:25 +0000181
182/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
183 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
184 */
185#ifdef CONFIG_APTIX
Ladislav Michl81472d82009-03-30 18:58:41 +0200186#define V_PTV 3
wdenk8ed96042005-01-09 23:16:25 +0000187#else
Ladislav Michl81472d82009-03-30 18:58:41 +0200188#define V_PTV 7 /* use with 12MHz/128 */
wdenk8ed96042005-01-09 23:16:25 +0000189#endif
190
Ladislav Michl81472d82009-03-30 18:58:41 +0200191#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
192#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
Hunter, Jond1da76e2013-04-03 09:35:36 +0000193#define CONFIG_SYS_HZ 1000
wdenk8ed96042005-01-09 23:16:25 +0000194
195/*-----------------------------------------------------------------------
wdenk8ed96042005-01-09 23:16:25 +0000196 * Physical Memory Map
197 */
198#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
199#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
200#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
201#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
202
Wolfgang Denk49a75812005-09-25 18:41:04 +0200203#define PHYS_FLASH_SECT_SIZE SZ_128K
wdenk8ed96042005-01-09 23:16:25 +0000204#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
205#define PHYS_FLASH_SIZE_1 SZ_32M
206#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
207#define PHYS_FLASH_SIZE_2 SZ_32M
wdenk8ed96042005-01-09 23:16:25 +0000208
Aneesh V37129822011-06-09 08:54:55 -0400209#define PHYS_SRAM 0x4020F800
wdenk8ed96042005-01-09 23:16:25 +0000210/*-----------------------------------------------------------------------
211 * FLASH and environment organization
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
214#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
215#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
216#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
217#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */
218#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
wdenk8ed96042005-01-09 23:16:25 +0000219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#ifdef CONFIG_SYS_NAND_BOOT
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200221#define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200222#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */
wdenk289f9322005-01-12 00:15:14 +0000223#else
Hunter, Jon47f58a72013-04-03 09:35:34 +0000224#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_256K)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200225#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200226#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
wdenk289f9322005-01-12 00:15:14 +0000228#endif
wdenk8ed96042005-01-09 23:16:25 +0000229
Wolfgang Denk49a75812005-09-25 18:41:04 +0200230/*-----------------------------------------------------------------------
231 * CFI FLASH driver setup
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200234#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
236#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
Wolfgang Denk49a75812005-09-25 18:41:04 +0200237
wdenk8ed96042005-01-09 23:16:25 +0000238/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
240#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk289f9322005-01-12 00:15:14 +0000241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_JFFS2_MEM_NAND
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200243
244/*
245 * JFFS2 partitions
246 */
247/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100248#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200249#define CONFIG_JFFS2_DEV "nor1"
250#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
251#define CONFIG_JFFS2_PART_OFFSET 0x00000000
252
253/* mtdparts command line support */
254/* Note: fake mtd_id used, no linux mtd map file */
255/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100256#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200257#define MTDIDS_DEFAULT "nor1=omap2420-1"
258#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
259*/
wdenk8ed96042005-01-09 23:16:25 +0000260
Aneesh V37129822011-06-09 08:54:55 -0400261#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
262#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
263
wdenk8ed96042005-01-09 23:16:25 +0000264#endif /* __CONFIG_H */