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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * FPGA support
27 */
28#include <common.h>
29#include <command.h>
Jon Loeligerbaa26db2007-07-08 17:51:39 -050030#if defined(CONFIG_CMD_NET)
wdenk4a9cbbe2002-08-27 09:48:53 +000031#include <net.h>
32#endif
wdenk8bde7f72003-06-27 21:31:46 +000033#include <fpga.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000034#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000035
36#if 0
37#define FPGA_DEBUG
38#endif
39
40#ifdef FPGA_DEBUG
41#define PRINTF(fmt,args...) printf (fmt ,##args)
42#else
43#define PRINTF(fmt,args...)
44#endif
45
wdenk4a9cbbe2002-08-27 09:48:53 +000046/* Local functions */
wdenkd4ca31c2004-01-02 14:00:00 +000047static void fpga_usage (cmd_tbl_t * cmdtp);
48static int fpga_get_op (char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000049
50/* Local defines */
51#define FPGA_NONE -1
52#define FPGA_INFO 0
53#define FPGA_LOAD 1
wdenk30ce5ab2005-01-09 18:12:51 +000054#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000055#define FPGA_DUMP 3
Stefan Roesef0ff4692006-08-15 14:15:51 +020056#define FPGA_LOADMK 4
wdenk4a9cbbe2002-08-27 09:48:53 +000057
wdenk30ce5ab2005-01-09 18:12:51 +000058/* Convert bitstream data and load into the fpga */
59int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
60{
Matthias Fuchs01335022007-12-27 17:12:34 +010061#if defined(CONFIG_FPGA_XILINX)
Wolfgang Denk8b019da2005-08-08 00:14:41 +020062 unsigned int length;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020063 unsigned int swapsize;
wdenk30ce5ab2005-01-09 18:12:51 +000064 char buffer[80];
Wolfgang Denk8b019da2005-08-08 00:14:41 +020065 unsigned char *dataptr;
Wolfgang Denk8b019da2005-08-08 00:14:41 +020066 unsigned int i;
wdenk30ce5ab2005-01-09 18:12:51 +000067 int rc;
68
Wolfgang Denk77ddac92005-10-13 16:45:02 +020069 dataptr = (unsigned char *)fpgadata;
wdenk30ce5ab2005-01-09 18:12:51 +000070
Wolfgang Denk8b019da2005-08-08 00:14:41 +020071 /* skip the first bytes of the bitsteam, their meaning is unknown */
72 length = (*dataptr << 8) + *(dataptr+1);
73 dataptr+=2;
74 dataptr+=length;
wdenk30ce5ab2005-01-09 18:12:51 +000075
76 /* get design name (identifier, length, string) */
Wolfgang Denk8b019da2005-08-08 00:14:41 +020077 length = (*dataptr << 8) + *(dataptr+1);
78 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +000079 if (*dataptr++ != 0x61) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020080 PRINTF ("%s: Design name identifier not recognized in bitstream\n",
81 __FUNCTION__ );
wdenk30ce5ab2005-01-09 18:12:51 +000082 return FPGA_FAIL;
83 }
84
wdenka562e1b2005-01-09 18:21:42 +000085 length = (*dataptr << 8) + *(dataptr+1);
wdenk30ce5ab2005-01-09 18:12:51 +000086 dataptr+=2;
87 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +020088 buffer[i] = *dataptr++;
wdenka562e1b2005-01-09 18:21:42 +000089
Wolfgang Denk8b019da2005-08-08 00:14:41 +020090 printf(" design filename = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +000091
92 /* get part number (identifier, length, string) */
93 if (*dataptr++ != 0x62) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +020094 printf("%s: Part number identifier not recognized in bitstream\n",
95 __FUNCTION__ );
wdenk30ce5ab2005-01-09 18:12:51 +000096 return FPGA_FAIL;
97 }
wdenka562e1b2005-01-09 18:21:42 +000098
Wolfgang Denk8b019da2005-08-08 00:14:41 +020099 length = (*dataptr << 8) + *(dataptr+1);
100 dataptr+=2;
wdenka562e1b2005-01-09 18:21:42 +0000101 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200102 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200103 printf(" part number = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000104
wdenk30ce5ab2005-01-09 18:12:51 +0000105 /* get date (identifier, length, string) */
106 if (*dataptr++ != 0x63) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200107 printf("%s: Date identifier not recognized in bitstream\n",
108 __FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000109 return FPGA_FAIL;
110 }
wdenka562e1b2005-01-09 18:21:42 +0000111
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200112 length = (*dataptr << 8) + *(dataptr+1);
113 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000114 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200115 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200116 printf(" date = \"%s\"\n", buffer);
wdenk30ce5ab2005-01-09 18:12:51 +0000117
118 /* get time (identifier, length, string) */
119 if (*dataptr++ != 0x64) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200120 printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000121 return FPGA_FAIL;
122 }
wdenka562e1b2005-01-09 18:21:42 +0000123
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200124 length = (*dataptr << 8) + *(dataptr+1);
125 dataptr+=2;
wdenk30ce5ab2005-01-09 18:12:51 +0000126 for(i=0;i<length;i++)
Wolfgang Denkd0ff51b2008-07-14 15:19:07 +0200127 buffer[i] = *dataptr++;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200128 printf(" time = \"%s\"\n", buffer);
wdenka562e1b2005-01-09 18:21:42 +0000129
wdenk30ce5ab2005-01-09 18:12:51 +0000130 /* get fpga data length (identifier, length) */
131 if (*dataptr++ != 0x65) {
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200132 printf("%s: Data length identifier not recognized in bitstream\n",
133 __FUNCTION__);
wdenk30ce5ab2005-01-09 18:12:51 +0000134 return FPGA_FAIL;
135 }
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200136 swapsize = ((unsigned int) *dataptr <<24) +
137 ((unsigned int) *(dataptr+1) <<16) +
138 ((unsigned int) *(dataptr+2) <<8 ) +
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200139 ((unsigned int) *(dataptr+3) ) ;
wdenk30ce5ab2005-01-09 18:12:51 +0000140 dataptr+=4;
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200141 printf(" bytes in bitstream = %d\n", swapsize);
wdenka562e1b2005-01-09 18:21:42 +0000142
Matthias Fuchsc26acc12007-12-27 17:13:11 +0100143 rc = fpga_load(dev, dataptr, swapsize);
wdenk30ce5ab2005-01-09 18:12:51 +0000144 return rc;
145#else
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200146 printf("Bitstream support only for Xilinx devices\n");
wdenk30ce5ab2005-01-09 18:12:51 +0000147 return FPGA_FAIL;
148#endif
149}
150
wdenk4a9cbbe2002-08-27 09:48:53 +0000151/* ------------------------------------------------------------------------- */
152/* command form:
153 * fpga <op> <device number> <data addr> <datasize>
154 * where op is 'load', 'dump', or 'info'
155 * If there is no device number field, the fpga environment variable is used.
156 * If there is no data addr field, the fpgadata environment variable is used.
157 * The info command requires no data address field.
158 */
wdenkd4ca31c2004-01-02 14:00:00 +0000159int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000160{
wdenkd4ca31c2004-01-02 14:00:00 +0000161 int op, dev = FPGA_INVALID_DEVICE;
162 size_t data_size = 0;
163 void *fpga_data = NULL;
164 char *devstr = getenv ("fpga");
165 char *datastr = getenv ("fpgadata");
166 int rc = FPGA_FAIL;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100167#if defined (CONFIG_FIT)
168 const char *fit_uname = NULL;
169 ulong fit_addr;
170#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000171
wdenkd4ca31c2004-01-02 14:00:00 +0000172 if (devstr)
173 dev = (int) simple_strtoul (devstr, NULL, 16);
174 if (datastr)
175 fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +0000176
wdenkd4ca31c2004-01-02 14:00:00 +0000177 switch (argc) {
178 case 5: /* fpga <op> <dev> <data> <datasize> */
179 data_size = simple_strtoul (argv[4], NULL, 16);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100180
wdenkd4ca31c2004-01-02 14:00:00 +0000181 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100182#if defined(CONFIG_FIT)
183 if (fit_parse_subimage (argv[3], (ulong)fpga_data,
184 &fit_addr, &fit_uname)) {
185 fpga_data = (void *)fit_addr;
186 debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
187 fit_uname, fit_addr);
188 } else
189#endif
190 {
191 fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
192 debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
193 }
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200194 PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100195
wdenkd4ca31c2004-01-02 14:00:00 +0000196 case 3: /* fpga <op> <dev | data addr> */
197 dev = (int) simple_strtoul (argv[2], NULL, 16);
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200198 PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000199 /* FIXME - this is a really weak test */
200 if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
Wolfgang Denk8f79e4c2005-08-10 15:14:32 +0200201 PRINTF ("%s: Assuming buffer pointer in arg 3\n",
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200202 __FUNCTION__);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100203
204#if defined(CONFIG_FIT)
205 if (fit_parse_subimage (argv[2], (ulong)fpga_data,
206 &fit_addr, &fit_uname)) {
207 fpga_data = (void *)fit_addr;
208 debug ("* fpga: subimage '%s' from FIT image at 0x%08lx\n",
209 fit_uname, fit_addr);
210 } else
211#endif
212 {
213 fpga_data = (void *) dev;
214 debug ("* fpga: cmdline image address = 0x%08lx\n", (ulong)fpga_data);
215 }
216
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200217 PRINTF ("%s: fpga_data = 0x%x\n",
218 __FUNCTION__, (uint) fpga_data);
wdenkd4ca31c2004-01-02 14:00:00 +0000219 dev = FPGA_INVALID_DEVICE; /* reset device num */
220 }
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100221
wdenkd4ca31c2004-01-02 14:00:00 +0000222 case 2: /* fpga <op> */
223 op = (int) fpga_get_op (argv[1]);
224 break;
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100225
wdenkd4ca31c2004-01-02 14:00:00 +0000226 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200227 PRINTF ("%s: Too many or too few args (%d)\n",
228 __FUNCTION__, argc);
wdenkd4ca31c2004-01-02 14:00:00 +0000229 op = FPGA_NONE; /* force usage display */
230 break;
231 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000232
wdenkd4ca31c2004-01-02 14:00:00 +0000233 switch (op) {
234 case FPGA_NONE:
235 fpga_usage (cmdtp);
236 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000237
wdenkd4ca31c2004-01-02 14:00:00 +0000238 case FPGA_INFO:
239 rc = fpga_info (dev);
240 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000241
wdenkd4ca31c2004-01-02 14:00:00 +0000242 case FPGA_LOAD:
243 rc = fpga_load (dev, fpga_data, data_size);
244 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000245
wdenk30ce5ab2005-01-09 18:12:51 +0000246 case FPGA_LOADB:
247 rc = fpga_loadbitstream(dev, fpga_data, data_size);
248 break;
249
Stefan Roesef0ff4692006-08-15 14:15:51 +0200250 case FPGA_LOADMK:
Marian Balakowicz9a4daad2008-02-29 14:58:34 +0100251 switch (genimg_get_format (fpga_data)) {
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100252 case IMAGE_FORMAT_LEGACY:
253 {
254 image_header_t *hdr = (image_header_t *)fpga_data;
255 ulong data;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200256
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100257 data = (ulong)image_get_data (hdr);
258 data_size = image_get_data_size (hdr);
259 rc = fpga_load (dev, (void *)data, data_size);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200260 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100261 break;
262#if defined(CONFIG_FIT)
263 case IMAGE_FORMAT_FIT:
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100264 {
265 const void *fit_hdr = (const void *)fpga_data;
266 int noffset;
267 void *fit_data;
268
269 if (fit_uname == NULL) {
270 puts ("No FIT subimage unit name\n");
271 return 1;
272 }
273
274 if (!fit_check_format (fit_hdr)) {
275 puts ("Bad FIT image format\n");
276 return 1;
277 }
278
279 /* get fpga component image node offset */
280 noffset = fit_image_get_node (fit_hdr, fit_uname);
281 if (noffset < 0) {
282 printf ("Can't find '%s' FIT subimage\n", fit_uname);
283 return 1;
284 }
285
286 /* verify integrity */
287 if (!fit_image_check_hashes (fit_hdr, noffset)) {
288 puts ("Bad Data Hash\n");
289 return 1;
290 }
291
292 /* get fpga subimage data address and length */
293 if (fit_image_get_data (fit_hdr, noffset, &fit_data, &data_size)) {
294 puts ("Could not find fpga subimage data\n");
295 return 1;
296 }
297
298 rc = fpga_load (dev, fit_data, data_size);
299 }
Marian Balakowiczd5934ad2008-02-04 08:28:09 +0100300 break;
301#endif
302 default:
303 puts ("** Unknown image type\n");
304 rc = FPGA_FAIL;
305 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200306 }
307 break;
308
wdenkd4ca31c2004-01-02 14:00:00 +0000309 case FPGA_DUMP:
310 rc = fpga_dump (dev, fpga_data, data_size);
311 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000312
wdenkd4ca31c2004-01-02 14:00:00 +0000313 default:
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200314 printf ("Unknown operation\n");
wdenkd4ca31c2004-01-02 14:00:00 +0000315 fpga_usage (cmdtp);
316 break;
317 }
318 return (rc);
wdenk4a9cbbe2002-08-27 09:48:53 +0000319}
320
wdenkd4ca31c2004-01-02 14:00:00 +0000321static void fpga_usage (cmd_tbl_t * cmdtp)
wdenk4a9cbbe2002-08-27 09:48:53 +0000322{
Peter Tyser62c3ae72009-01-27 18:03:10 -0600323 cmd_usage(cmdtp);
wdenk4a9cbbe2002-08-27 09:48:53 +0000324}
325
326/*
327 * Map op to supported operations. We don't use a table since we
328 * would just have to relocate it from flash anyway.
329 */
wdenkd4ca31c2004-01-02 14:00:00 +0000330static int fpga_get_op (char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000331{
332 int op = FPGA_NONE;
333
334 if (!strcmp ("info", opstr)) {
335 op = FPGA_INFO;
wdenk30ce5ab2005-01-09 18:12:51 +0000336 } else if (!strcmp ("loadb", opstr)) {
337 op = FPGA_LOADB;
wdenkd4ca31c2004-01-02 14:00:00 +0000338 } else if (!strcmp ("load", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000339 op = FPGA_LOAD;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200340 } else if (!strcmp ("loadmk", opstr)) {
341 op = FPGA_LOADMK;
wdenkd4ca31c2004-01-02 14:00:00 +0000342 } else if (!strcmp ("dump", opstr)) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000343 op = FPGA_DUMP;
344 }
345
wdenkd4ca31c2004-01-02 14:00:00 +0000346 if (op == FPGA_NONE) {
wdenk4a9cbbe2002-08-27 09:48:53 +0000347 printf ("Unknown fpga operation \"%s\"\n", opstr);
348 }
349 return op;
350}
351
wdenkd4ca31c2004-01-02 14:00:00 +0000352U_BOOT_CMD (fpga, 6, 1, do_fpga,
Peter Tyser2fb26042009-01-27 18:03:12 -0600353 "loadable FPGA image support",
wdenkd4ca31c2004-01-02 14:00:00 +0000354 "fpga [operation type] [device number] [image address] [image size]\n"
355 "fpga operations:\n"
Wolfgang Denk8b019da2005-08-08 00:14:41 +0200356 "\tinfo\tlist known device information\n"
357 "\tload\tLoad device from memory buffer\n"
358 "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
Stefan Roesef0ff4692006-08-15 14:15:51 +0200359 "\tloadmk\tLoad device generated with mkimage\n"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100360 "\tdump\tLoad device to memory buffer\n"
361#if defined(CONFIG_FIT)
362 "\tFor loadmk operating on FIT format uImage address must include\n"
363 "\tsubimage unit name in the form of addr:<subimg_uname>\n"
364#endif
365);