blob: 576aa740625fab9c8ae55dbcfd076a51c21899b4 [file] [log] [blame]
wdenk983fda82004-10-28 00:09:35 +00001/*
2 * (C) Copyright 2004
3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31#define CONFIG_MPC8220 1
32#define CONFIG_ALASKA8220 1 /* ... on Alaska board */
33
Becky Bruce31d82672008-05-08 19:02:12 -050034#define CONFIG_HIGH_BATS 1 /* High BATs supported */
35
wdenk983fda82004-10-28 00:09:35 +000036/* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
37 determine the CPU speed. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_MPC8220_CLKIN 30000000/* ... running at 30MHz */
39#define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
wdenk983fda82004-10-28 00:09:35 +000040
41#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
42#define BOOTFLAG_WARM 0x02 /* Software reboot */
43
wdenk983fda82004-10-28 00:09:35 +000044/*
45 * Serial console configuration
46 */
wdenk7680c142005-05-16 15:23:22 +000047
48/* Define this for PSC console
49#define CONFIG_PSC_CONSOLE 1
50*/
51
wdenk983fda82004-10-28 00:09:35 +000052#define CONFIG_EXTUART_CONSOLE 1
53
54#ifdef CONFIG_EXTUART_CONSOLE
wdenk7680c142005-05-16 15:23:22 +000055# define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056# define CONFIG_SYS_NS16550_SERIAL
57# define CONFIG_SYS_NS16550
58# define CONFIG_SYS_NS16550_REG_SIZE 1
59# define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CPLD_BASE + 0x1008)
60# define CONFIG_SYS_NS16550_CLK 18432000
wdenk983fda82004-10-28 00:09:35 +000061#endif
62
63#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk983fda82004-10-28 00:09:35 +000066
wdenk7680c142005-05-16 15:23:22 +000067#define CONFIG_TIMESTAMP /* Print image info with timestamp */
wdenk414eec32005-04-02 22:37:54 +000068
Jon Loeliger498ff9a2007-07-05 19:13:52 -050069
wdenk983fda82004-10-28 00:09:35 +000070/*
Jon Loeliger11799432007-07-10 09:02:57 -050071 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78
79/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -050080 * Command line configuration.
wdenk983fda82004-10-28 00:09:35 +000081 */
Jon Loeliger498ff9a2007-07-05 19:13:52 -050082#include <config_cmd_default.h>
83
84#define CONFIG_CMD_BOOTD
85#define CONFIG_CMD_CACHE
86#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_DIAG
88#define CONFIG_CMD_EEPROM
89#define CONFIG_CMD_ELF
90#define CONFIG_CMD_I2C
91#define CONFIG_CMD_NET
92#define CONFIG_CMD_NFS
93#define CONFIG_CMD_PCI
94#define CONFIG_CMD_PING
95#define CONFIG_CMD_REGINFO
96#define CONFIG_CMD_SDRAM
97#define CONFIG_CMD_SNTP
98
wdenk983fda82004-10-28 00:09:35 +000099
wdenk414eec32005-04-02 22:37:54 +0000100#define CONFIG_NET_MULTI
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200101#define CONFIG_MII
wdenk983fda82004-10-28 00:09:35 +0000102
wdenk983fda82004-10-28 00:09:35 +0000103/*
104 * Autobooting
105 */
106#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
107#define CONFIG_BOOTARGS "root=/dev/ram rw"
108#define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
wdenke2ffd592004-12-31 09:32:47 +0000109#define CONFIG_HAS_ETH1
wdenk983fda82004-10-28 00:09:35 +0000110#define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
111#define CONFIG_IPADDR 192.162.1.2
112#define CONFIG_NETMASK 255.255.255.0
113#define CONFIG_SERVERIP 192.162.1.1
114#define CONFIG_GATEWAYIP 192.162.1.1
115#define CONFIG_HOSTNAME Alaska
116#define CONFIG_OVERWRITE_ETHADDR_ONCE
117
118
119/*
120 * I2C configuration
121 */
122#define CONFIG_HARD_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_I2C_MODULE 1
wdenk983fda82004-10-28 00:09:35 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
126#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk983fda82004-10-28 00:09:35 +0000127
128/*
129 * EEPROM configuration
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
132#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
133#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
134#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenk983fda82004-10-28 00:09:35 +0000135/*
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200136#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200137#define CONFIG_ENV_OFFSET 0
138#define CONFIG_ENV_SIZE 256
wdenk983fda82004-10-28 00:09:35 +0000139*/
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141/* If CONFIG_SYS_AMD_BOOT is defined, the the system will boot from AMD.
wdenk983fda82004-10-28 00:09:35 +0000142 else undefined it will boot from Intel Strata flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_AMD_BOOT 1
wdenk983fda82004-10-28 00:09:35 +0000144
145/*
146 * Flexbus Chipselect configuration
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#if defined (CONFIG_SYS_AMD_BOOT)
149#define CONFIG_SYS_CS0_BASE 0xfff0
150#define CONFIG_SYS_CS0_MASK 0x00080000 /* 512 KB */
151#define CONFIG_SYS_CS0_CTRL 0x003f0d40
wdenk983fda82004-10-28 00:09:35 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_CS1_BASE 0xfe00
154#define CONFIG_SYS_CS1_MASK 0x01000000 /* 16 MB */
155#define CONFIG_SYS_CS1_CTRL 0x003f1540
wdenk983fda82004-10-28 00:09:35 +0000156#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_CS0_BASE 0xff00
158#define CONFIG_SYS_CS0_MASK 0x01000000 /* 16 MB */
159#define CONFIG_SYS_CS0_CTRL 0x003f1540
wdenk983fda82004-10-28 00:09:35 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_CS1_BASE 0xfe08
162#define CONFIG_SYS_CS1_MASK 0x00080000 /* 512 KB */
163#define CONFIG_SYS_CS1_CTRL 0x003f0d40
wdenk983fda82004-10-28 00:09:35 +0000164#endif
165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_CS2_BASE 0xf100
167#define CONFIG_SYS_CS2_MASK 0x00040000
168#define CONFIG_SYS_CS2_CTRL 0x003f1140
wdenk983fda82004-10-28 00:09:35 +0000169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_CS3_BASE 0xf200
171#define CONFIG_SYS_CS3_MASK 0x00040000
172#define CONFIG_SYS_CS3_CTRL 0x003f1100
wdenk983fda82004-10-28 00:09:35 +0000173
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
176#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_CS1_BASE << 16)
wdenk983fda82004-10-28 00:09:35 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#if defined (CONFIG_SYS_AMD_BOOT)
179#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH0_BASE
180#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH1_BASE + 0xf00000
181#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_AMD_BASE
wdenk983fda82004-10-28 00:09:35 +0000182#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_INTEL_BASE CONFIG_SYS_FLASH0_BASE + 0xf00000
184#define CONFIG_SYS_AMD_BASE CONFIG_SYS_FLASH1_BASE
185#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_INTEL_BASE
wdenk983fda82004-10-28 00:09:35 +0000186#endif
187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_CPLD_BASE (CONFIG_SYS_CS2_BASE << 16)
189#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_CS3_BASE << 16)
wdenk983fda82004-10-28 00:09:35 +0000190
191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max num of memory banks */
193#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk983fda82004-10-28 00:09:35 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
196#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
197#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
198#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
199#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
wdenk983fda82004-10-28 00:09:35 +0000200
201#define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
202#define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_CHECKSUM
wdenk983fda82004-10-28 00:09:35 +0000205/*
206 * Environment settings
207 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200208#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#if defined (CONFIG_SYS_AMD_BOOT)
210#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_AMD_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200211#define CONFIG_ENV_SIZE PHYS_AMD_SECT_SIZE
212#define CONFIG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_INTEL_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200214#define CONFIG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
215#define CONFIG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
wdenk983fda82004-10-28 00:09:35 +0000216#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_CS0_MASK - PHYS_INTEL_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218#define CONFIG_ENV_SIZE PHYS_INTEL_SECT_SIZE
219#define CONFIG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_ENV1_ADDR (CONFIG_SYS_FLASH1_BASE + CONFIG_SYS_CS1_MASK - PHYS_AMD_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200221#define CONFIG_ENV1_SIZE PHYS_AMD_SECT_SIZE
222#define CONFIG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
wdenk983fda82004-10-28 00:09:35 +0000223#endif
224
225#define CONFIG_ENV_OVERWRITE 1
226
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200227#if defined CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200228#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200229#undef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200230#elif defined CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200231#undef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200232#undef CONFIG_ENV_IS_IN_EEPROM
233#elif defined CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200234#undef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200235#undef CONFIG_ENV_IS_IN_FLASH
wdenk983fda82004-10-28 00:09:35 +0000236#endif
237
wdenk983fda82004-10-28 00:09:35 +0000238/*
239 * Memory map
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_MBAR 0xF0000000
242#define CONFIG_SYS_SDRAM_BASE 0x00000000
243#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
244#define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
245#define CONFIG_SYS_SRAM_SIZE 0x8000
wdenk983fda82004-10-28 00:09:35 +0000246
247/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
249#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
wdenk983fda82004-10-28 00:09:35 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
252#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk983fda82004-10-28 00:09:35 +0000254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
256#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
257# define CONFIG_SYS_RAMBOOT 1
wdenk983fda82004-10-28 00:09:35 +0000258#endif
259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
261#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
262#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk983fda82004-10-28 00:09:35 +0000263
wdenk12b43d52005-04-05 21:57:18 +0000264/* SDRAM configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_SDRAM_TOTAL_BANKS 2
266#define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
267#define CONFIG_SYS_SDRAM_SPD_SIZE 0x40
268#define CONFIG_SYS_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
wdenk7680c142005-05-16 15:23:22 +0000269
270/* SDRAM drive strength register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
wdenk7680c142005-05-16 15:23:22 +0000272 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
273 (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
274 (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
275 (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
wdenk12b43d52005-04-05 21:57:18 +0000276
wdenk983fda82004-10-28 00:09:35 +0000277/*
278 * Ethernet configuration
279 */
280#define CONFIG_MPC8220_FEC 1
281#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
282#define CONFIG_PHY_ADDR 0x18
283
284
285/*
286 * Miscellaneous configurable options
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_LONGHELP /* undef to save memory */
289#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500290#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk983fda82004-10-28 00:09:35 +0000292#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk983fda82004-10-28 00:09:35 +0000294#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
296#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
297#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk983fda82004-10-28 00:09:35 +0000298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
300#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk983fda82004-10-28 00:09:35 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk983fda82004-10-28 00:09:35 +0000303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk983fda82004-10-28 00:09:35 +0000305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500307#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500309#endif
310
wdenk983fda82004-10-28 00:09:35 +0000311/*
312 * Various low-level settings
313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
315#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenk983fda82004-10-28 00:09:35 +0000316
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200317/*
318 * JFFS2 partitions
319 */
320
321/* No command line, one static partition */
322/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100323#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200324#define CONFIG_JFFS2_DEV "nor0"
325#define CONFIG_JFFS2_PART_SIZE 0x00400000
326#define CONFIG_JFFS2_PART_OFFSET 0x00000000
327*/
328
329/* mtdparts command line support */
330/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100331#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200332#define MTDIDS_DEFAULT "nor0=alaska-0"
333#define MTDPARTS_DEFAULT "mtdparts=alaska-0:4m(user)"
334*/
335
wdenk983fda82004-10-28 00:09:35 +0000336#endif /* __CONFIG_H */