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wdenka522fa02004-01-04 22:51:12 +00001/*
Wolfgang Denk7c803be2008-09-16 18:02:19 +02002 * (C) Copyright 2000-2008
wdenka522fa02004-01-04 22:51:12 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk1c437712004-01-16 00:30:56 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenka522fa02004-01-04 22:51:12 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
wdenkc40b2952004-03-13 23:29:43 +000036#define CONFIG_HMI10
wdenka522fa02004-01-04 22:51:12 +000037#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
38#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
39
40#define CONFIG_LCD
41#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */
42
43#ifdef CONFIG_LCD /* with LCD controller ? */
wdenk1c437712004-01-16 00:30:56 +000044#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
wdenka522fa02004-01-04 22:51:12 +000045#endif
46
wdenk1c437712004-01-16 00:30:56 +000047#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
wdenka522fa02004-01-04 22:51:12 +000048#undef CONFIG_8xx_CONS_SMC2
49#undef CONFIG_8xx_CONS_NONE
50#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
51
wdenk1c437712004-01-16 00:30:56 +000052#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
wdenkc837dcb2004-01-20 23:12:12 +000053#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
wdenk1c437712004-01-16 00:30:56 +000054#define CONFIG_PS2SERIAL 2 /* .. on COM3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
wdenk1c437712004-01-16 00:30:56 +000056
57#define CONFIG_BOOTCOUNT_LIMIT
wdenka522fa02004-01-04 22:51:12 +000058
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
61#define CONFIG_BOARD_TYPES 1 /* support board types */
62
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010063#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenka522fa02004-01-04 22:51:12 +000064
65#undef CONFIG_BOOTARGS
66
wdenk1c437712004-01-16 00:30:56 +000067#define CONFIG_EXTRA_ENV_SETTINGS \
wdenka522fa02004-01-04 22:51:12 +000068 "netdev=eth0\0" \
69 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010070 "nfsroot=${serverip}:${rootpath}\0" \
wdenka522fa02004-01-04 22:51:12 +000071 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010072 "addip=setenv bootargs ${bootargs} " \
73 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
74 ":${hostname}:${netdev}:off panic=1\0" \
wdenka522fa02004-01-04 22:51:12 +000075 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010076 "bootm ${kernel_addr}\0" \
wdenka522fa02004-01-04 22:51:12 +000077 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010078 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
79 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenka522fa02004-01-04 22:51:12 +000080 "rootpath=/opt/eldk/ppc_8xx\0" \
wdenkc40b2952004-03-13 23:29:43 +000081 "bootfile=/tftpboot/HMI10/uImage\0" \
wdenka522fa02004-01-04 22:51:12 +000082 "kernel_addr=40040000\0" \
83 "ramdisk_addr=40100000\0" \
84 ""
85#define CONFIG_BOOTCOMMAND "run flash_self"
86
wdenkc837dcb2004-01-20 23:12:12 +000087#define CONFIG_BOARD_EARLY_INIT_R 1
88#define CONFIG_MISC_INIT_R 1
wdenk1c437712004-01-16 00:30:56 +000089
wdenka522fa02004-01-04 22:51:12 +000090#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenka522fa02004-01-04 22:51:12 +000092
93/* enable I2C and select the hardware/software driver */
94#undef CONFIG_HARD_I2C /* I2C with hardware support */
95#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */
98#define CONFIG_SYS_I2C_SLAVE 0xFE
wdenka522fa02004-01-04 22:51:12 +000099
100/* Software (bit-bang) I2C driver configuration */
101#define PB_SCL 0x00000020 /* PB 26 */
102#define PB_SDA 0x00000010 /* PB 27 */
103
104#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
105#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
106#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
107#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
108#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenk1c437712004-01-16 00:30:56 +0000109 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenka522fa02004-01-04 22:51:12 +0000110#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenk1c437712004-01-16 00:30:56 +0000111 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenka522fa02004-01-04 22:51:12 +0000112#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
113
114#undef CONFIG_WATCHDOG /* watchdog disabled */
115
116#define CONFIG_STATUS_LED 1 /* Status LED enabled */
117
118#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
119
Jon Loeliger7be044e2007-07-09 21:24:19 -0500120/*
121 * BOOTP options
122 */
123#define CONFIG_BOOTP_SUBNETMASK
124#define CONFIG_BOOTP_GATEWAY
125#define CONFIG_BOOTP_HOSTNAME
126#define CONFIG_BOOTP_BOOTPATH
127#define CONFIG_BOOTP_BOOTFILESIZE
128
wdenka522fa02004-01-04 22:51:12 +0000129
130#define CONFIG_MAC_PARTITION
131#define CONFIG_DOS_PARTITION
132
133#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
wdenka522fa02004-01-04 22:51:12 +0000135
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500136
137/*
138 * Command line configuration.
139 */
140#include <config_cmd_default.h>
141
142#define CONFIG_CMD_ASKENV
143#define CONFIG_CMD_DATE
144#define CONFIG_CMD_DHCP
145#define CONFIG_CMD_FAT
146#define CONFIG_CMD_I2C
147#define CONFIG_CMD_IDE
148#define CONFIG_CMD_NFS
149#define CONFIG_CMD_SNTP
150
wdenka522fa02004-01-04 22:51:12 +0000151#ifdef CONFIG_SPLASH_SCREEN
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500152 #define CONFIG_CMD_BMP
wdenka522fa02004-01-04 22:51:12 +0000153#endif
154
wdenka522fa02004-01-04 22:51:12 +0000155
156/*
157 * Miscellaneous configurable options
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_LONGHELP /* undef to save memory */
160#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenka522fa02004-01-04 22:51:12 +0000161
162#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenka522fa02004-01-04 22:51:12 +0000164#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#ifdef CONFIG_SYS_HUSH_PARSER
166#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenka522fa02004-01-04 22:51:12 +0000167#endif
168
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500169#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenka522fa02004-01-04 22:51:12 +0000171#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenka522fa02004-01-04 22:51:12 +0000173#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
175#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
176#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenka522fa02004-01-04 22:51:12 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
179#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenka522fa02004-01-04 22:51:12 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenka522fa02004-01-04 22:51:12 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenka522fa02004-01-04 22:51:12 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenka522fa02004-01-04 22:51:12 +0000186
187/*
188 * Low Level Configuration Settings
189 * (address mappings, register initial values, etc.)
190 * You should know what you are doing if you make changes here.
191 */
192/*-----------------------------------------------------------------------
193 * Internal Memory Mapped Register
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_IMMR 0xFFF00000
wdenka522fa02004-01-04 22:51:12 +0000196
197/*-----------------------------------------------------------------------
198 * Definitions for initial stack pointer and data area (in DPRAM)
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
201#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
202#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
203#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
204#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenka522fa02004-01-04 22:51:12 +0000205
206/*-----------------------------------------------------------------------
207 * Start addresses for the final memory configuration
208 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenka522fa02004-01-04 22:51:12 +0000210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_SDRAM_BASE 0x00000000
212#define CONFIG_SYS_FLASH_BASE 0x40000000
213#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
214#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
215#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenka522fa02004-01-04 22:51:12 +0000216
217/*
218 * For booting Linux, the board info and command line data
219 * have to be in the first 8 MB of memory, since this is
220 * the maximum mapped by the Linux kernel during initialization.
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka522fa02004-01-04 22:51:12 +0000223
224/*-----------------------------------------------------------------------
225 * FLASH organization
226 */
wdenka522fa02004-01-04 22:51:12 +0000227
Martin Krausee318d9e2007-09-27 11:10:08 +0200228/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200230#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
232#define CONFIG_SYS_FLASH_EMPTY_INFO
233#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
234#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
235#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenka522fa02004-01-04 22:51:12 +0000236
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200237#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200238#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
239#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenka522fa02004-01-04 22:51:12 +0000240
241/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200242#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
243#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenka522fa02004-01-04 22:51:12 +0000244
245/*-----------------------------------------------------------------------
246 * Hardware Information Block
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
249#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
250#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenka522fa02004-01-04 22:51:12 +0000251
252/*-----------------------------------------------------------------------
253 * Cache Configuration
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500256#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenka522fa02004-01-04 22:51:12 +0000258#endif
259
260/*-----------------------------------------------------------------------
261 * SYPCR - System Protection Control 11-9
262 * SYPCR can only be written once after reset!
263 *-----------------------------------------------------------------------
264 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
265 */
266#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenka522fa02004-01-04 22:51:12 +0000268 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
269#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenka522fa02004-01-04 22:51:12 +0000271#endif
272
273/*-----------------------------------------------------------------------
274 * SIUMCR - SIU Module Configuration 11-6
275 *-----------------------------------------------------------------------
276 * PCMCIA config., multi-function pin tri-state
277 */
wdenk1c437712004-01-16 00:30:56 +0000278#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenka522fa02004-01-04 22:51:12 +0000280#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenka522fa02004-01-04 22:51:12 +0000282#endif /* CONFIG_CAN_DRIVER */
283
284/*-----------------------------------------------------------------------
285 * TBSCR - Time Base Status and Control 11-26
286 *-----------------------------------------------------------------------
287 * Clear Reference Interrupt Status, Timebase freezing enabled
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenka522fa02004-01-04 22:51:12 +0000290
291/*-----------------------------------------------------------------------
292 * RTCSC - Real-Time Clock Status and Control Register 11-27
293 *-----------------------------------------------------------------------
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenka522fa02004-01-04 22:51:12 +0000296
297/*-----------------------------------------------------------------------
298 * PISCR - Periodic Interrupt Status and Control 11-31
299 *-----------------------------------------------------------------------
300 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenka522fa02004-01-04 22:51:12 +0000303
304/*-----------------------------------------------------------------------
305 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
306 *-----------------------------------------------------------------------
307 * Reset PLL lock status sticky bit, timer expired status bit and timer
308 * interrupt status bit
309 *
310 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenka522fa02004-01-04 22:51:12 +0000313
314/*-----------------------------------------------------------------------
315 * SCCR - System Clock and reset Control Register 15-27
316 *-----------------------------------------------------------------------
317 * Set clock output, timebase and RTC source and divider,
318 * power management and some other internal clocks
319 */
320#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenka522fa02004-01-04 22:51:12 +0000322 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
323 SCCR_DFALCD00)
wdenka522fa02004-01-04 22:51:12 +0000324
325/*-----------------------------------------------------------------------
326 * PCMCIA stuff
327 *-----------------------------------------------------------------------
328 *
329 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0100000)
331#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
332#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4100000)
333#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
334#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8100000)
335#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
336#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC100000)
337#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk68766092004-01-29 09:22:58 +0000338#define PCMCIA_MEM_WIN_NO 5
wdenk1c437712004-01-16 00:30:56 +0000339#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */
wdenka522fa02004-01-04 22:51:12 +0000340
341/*-----------------------------------------------------------------------
342 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
343 *-----------------------------------------------------------------------
344 */
345
wdenk1c437712004-01-16 00:30:56 +0000346#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
wdenka522fa02004-01-04 22:51:12 +0000347
wdenk1c437712004-01-16 00:30:56 +0000348#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
wdenka522fa02004-01-04 22:51:12 +0000349#undef CONFIG_IDE_RESET /* reset for ide not supported */
wdenk1c437712004-01-16 00:30:56 +0000350#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */
351#define CONFIG_IDE_LED 1 /* LED for ide supported */
352#endif
wdenka522fa02004-01-04 22:51:12 +0000353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
355#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenka522fa02004-01-04 22:51:12 +0000356
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenka522fa02004-01-04 22:51:12 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenka522fa02004-01-04 22:51:12 +0000360
361/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenka522fa02004-01-04 22:51:12 +0000363
364/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenka522fa02004-01-04 22:51:12 +0000366
367/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenka522fa02004-01-04 22:51:12 +0000369
370/*-----------------------------------------------------------------------
371 *
372 *-----------------------------------------------------------------------
373 *
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_DER 0
wdenka522fa02004-01-04 22:51:12 +0000376
377/*
378 * Init Memory Controller:
379 *
380 * BR0/1 and OR0/1 (FLASH)
381 */
382
383#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
384#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
385
386/* used to re-map FLASH both when starting from SRAM or FLASH:
387 * restrict access enough to keep SRAM working (if any)
388 * but not too much to meddle with FLASH accesses
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
391#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenka522fa02004-01-04 22:51:12 +0000392
393/*
394 * FLASH timing:
395 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenka522fa02004-01-04 22:51:12 +0000397 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenka522fa02004-01-04 22:51:12 +0000398
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
400#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
401#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenka522fa02004-01-04 22:51:12 +0000402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
404#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
405#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenka522fa02004-01-04 22:51:12 +0000406
407/*
408 * BR2/3 and OR2/3 (SDRAM)
409 *
410 */
411#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
412#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
wdenk1c437712004-01-16 00:30:56 +0000413#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
wdenka522fa02004-01-04 22:51:12 +0000414
415/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenka522fa02004-01-04 22:51:12 +0000417
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
419#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenka522fa02004-01-04 22:51:12 +0000420
wdenk1c437712004-01-16 00:30:56 +0000421#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
423#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenka522fa02004-01-04 22:51:12 +0000424#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
426#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
427#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
428#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenka522fa02004-01-04 22:51:12 +0000429 BR_PS_8 | BR_MS_UPMB | BR_V )
430#endif /* CONFIG_CAN_DRIVER */
431
432/*
433 * Memory Periodic Timer Prescaler
434 *
435 * The Divider for PTA (refresh timer) configuration is based on an
436 * example SDRAM configuration (64 MBit, one bank). The adjustment to
437 * the number of chip selects (NCS) and the actually needed refresh
438 * rate is done by setting MPTPR.
439 *
440 * PTA is calculated from
441 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
442 *
443 * gclk CPU clock (not bus clock!)
444 * Trefresh Refresh cycle * 4 (four word bursts used)
445 *
wdenk1c437712004-01-16 00:30:56 +0000446 * 4096 Rows from SDRAM example configuration
447 * 1000 factor s -> ms
448 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
449 * 4 Number of refresh cycles per period
450 * 64 Refresh cycle in ms per number of rows
wdenka522fa02004-01-04 22:51:12 +0000451 * --------------------------------------------
452 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
453 *
454 * 50 MHz => 50.000.000 / Divider = 98
455 * 66 Mhz => 66.000.000 / Divider = 129
456 * 80 Mhz => 80.000.000 / Divider = 156
457 */
wdenkc3f4d172004-06-25 23:35:58 +0000458
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
460#define CONFIG_SYS_MAMR_PTA 98
wdenka522fa02004-01-04 22:51:12 +0000461
462/*
463 * For 16 MBit, refresh rates could be 31.3 us
464 * (= 64 ms / 2K = 125 / quad bursts).
465 * For a simpler initialization, 15.6 us is used instead.
466 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
468 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenka522fa02004-01-04 22:51:12 +0000469 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
471#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenka522fa02004-01-04 22:51:12 +0000472
473/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
475#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenka522fa02004-01-04 22:51:12 +0000476
477/*
478 * MAMR settings for SDRAM
479 */
480
481/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenka522fa02004-01-04 22:51:12 +0000483 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
484 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
485/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenka522fa02004-01-04 22:51:12 +0000487 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
488 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
489
490
491/*
492 * Internal Definitions
493 *
494 * Boot Flags
495 */
wdenk1c437712004-01-16 00:30:56 +0000496#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenka522fa02004-01-04 22:51:12 +0000497#define BOOTFLAG_WARM 0x02 /* Software reboot */
498
499#endif /* __CONFIG_H */