blob: 8d245bffc2f3d2094da690994b7053cb5260ec57 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Shevchenko495f3772017-07-06 14:41:53 +03002/*
3 * Copyright (c) 2017 Intel Corporation
Andy Shevchenko495f3772017-07-06 14:41:53 +03004 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/x86-gpio.h>
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11/include/ "skeleton.dtsi"
12/include/ "rtc.dtsi"
13/include/ "tsc_timer.dtsi"
14
Simon Glass839d66c2020-11-05 06:32:17 -070015#include "smbios.dtsi"
16
Andy Shevchenko495f3772017-07-06 14:41:53 +030017/ {
18 model = "Intel Edison";
Andy Shevchenko35d29a82020-12-02 12:35:32 +020019 compatible = "intel,edison", "intel,tangier";
Andy Shevchenko495f3772017-07-06 14:41:53 +030020
21 aliases {
Andy Shevchenkod9b59fc2019-02-28 10:10:07 +020022 serial0 = &serial0;
23 serial1 = &serial1;
Andy Shevchenkoab83e5c2019-02-28 10:10:06 +020024 serial2 = &serial2;
Andy Shevchenko495f3772017-07-06 14:41:53 +030025 };
26
Simon Glass2e3b8832020-09-06 10:35:34 -060027 binman: binman {
28 multiple-images;
29 };
30
Andy Shevchenko495f3772017-07-06 14:41:53 +030031 chosen {
Andy Shevchenkoab83e5c2019-02-28 10:10:06 +020032 stdout-path = &serial2;
Andy Shevchenko495f3772017-07-06 14:41:53 +030033 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 cpu@0 {
40 device_type = "cpu";
41 compatible = "cpu-x86";
42 reg = <0>;
43 intel,apic-id = <0>;
44 };
45
46 cpu@1 {
47 device_type = "cpu";
48 compatible = "cpu-x86";
49 reg = <1>;
50 intel,apic-id = <2>;
51 };
52 };
53
54 pci {
55 compatible = "pci-x86";
56 #address-cells = <3>;
57 #size-cells = <2>;
58 u-boot,dm-pre-reloc;
59 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
60 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
61 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
62 };
63
Andy Shevchenkod9b59fc2019-02-28 10:10:07 +020064 serial0: serial@ff010080 {
65 compatible = "intel,mid-uart";
66 reg = <0xff010080 0x100>;
67 reg-shift = <0>;
68 clock-frequency = <29491200>;
69 current-speed = <115200>;
70 };
71
72 serial1: serial@ff010100 {
73 compatible = "intel,mid-uart";
74 reg = <0xff010100 0x100>;
75 reg-shift = <0>;
76 clock-frequency = <29491200>;
77 current-speed = <115200>;
78 };
79
Andy Shevchenkoab83e5c2019-02-28 10:10:06 +020080 serial2: serial@ff010180 {
Andy Shevchenko495f3772017-07-06 14:41:53 +030081 compatible = "intel,mid-uart";
82 reg = <0xff010180 0x100>;
83 reg-shift = <0>;
84 clock-frequency = <29491200>;
85 current-speed = <115200>;
86 };
87
88 emmc: mmc@ff3fc000 {
89 compatible = "intel,sdhci-tangier";
90 reg = <0xff3fc000 0x1000>;
91 };
92
Andy Shevchenko495f3772017-07-06 14:41:53 +030093 sdcard: mmc@ff3fa000 {
94 compatible = "intel,sdhci-tangier";
95 reg = <0xff3fa000 0x1000>;
96 };
Andy Shevchenko495f3772017-07-06 14:41:53 +030097
98 pmu: power@ff00b000 {
99 compatible = "intel,pmu-mid";
100 reg = <0xff00b000 0x1000>;
101 };
102
103 scu: ipc@ff009000 {
104 compatible = "intel,scu-ipc";
105 reg = <0xff009000 0x1000>;
106 };
Bin Mengb37b7b22018-07-19 03:07:33 -0700107
Andy Shevchenko23cdbba2020-12-03 19:45:01 +0200108 usb: usb@f9100000 {
109 compatible = "intel,tangier-dwc3";
Andy Shevchenkof89e8ac2020-12-03 19:45:02 +0200110 #address-cells = <1>;
111 #size-cells = <1>;
112
113 dwc3: dwc3 {
114 reg = <0xf9100000 0x100000>;
115 maximum-speed = "high-speed";
116 dr_mode = "peripheral";
117 };
Andy Shevchenko23cdbba2020-12-03 19:45:01 +0200118 };
119
Andy Shevchenkoc974a3d2019-06-21 13:28:08 +0300120 watchdog: wdt@0 {
121 compatible = "intel,tangier-wdt";
122 };
123
Bin Mengb37b7b22018-07-19 03:07:33 -0700124 reset {
125 compatible = "intel,reset-tangier";
126 u-boot,dm-pre-reloc;
127 };
Georgii Staroselskiif26b2602018-09-11 13:31:08 +0300128
129 pinctrl {
130 compatible = "intel,pinctrl-tangier";
131 reg = <0xff0c0000 0x8000>;
132
133 /*
134 * Initial configuration came from the firmware.
135 * Which quite likely has been used in the phones, where I2C #8,
136 * that is not part of Atom peripheral, is in use.
137 * Thus we need to override the leftover.
138 */
139 i2c6_scl@0 {
140 pad-offset = <111>;
141 mode-func = <1>;
142 protected;
143 };
144 i2c6_sda@0 {
145 pad-offset = <112>;
146 mode-func = <1>;
147 protected;
148 };
149 };
Andy Shevchenko495f3772017-07-06 14:41:53 +0300150};
Simon Glass2e3b8832020-09-06 10:35:34 -0600151
152&binman {
153 u-boot-edison {
154 filename = "u-boot-edison.img";
155
156 /* This is the OSIP */
157 blob {
158 filename = "edison-osip.dat";
159 };
160
161 u-boot {
162 offset = <0x200>;
163 };
164
165 u-boot-env {
166 offset = <0x200200>;
167 filename = "edison-environment.txt";
168 size = <0x10000>;
169 fill-byte = [ff];
170 };
171
172 u-boot-env2 {
173 type = "u-boot-env";
174 offset = <0x500200>;
175 filename = "edison-environment.txt";
176 size = <0x10000>;
177 fill-byte = [ff];
178 };
179 };
180};