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wdenk384cc682005-04-03 22:35:21 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * pm854 board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
38#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41#define CONFIG_MPC8540 1 /* MPC8540 specific */
42#define CONFIG_PM854 1 /* PM854 board specific */
43
44#define CONFIG_PCI
45#define CONFIG_TSEC_ENET /* tsec ethernet support */
46#define CONFIG_ENV_OVERWRITE
47#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup*/
wdenk384cc682005-04-03 22:35:21 +000048#define CONFIG_DDR_DLL /* possible DLL fix needed */
49#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
50
Jon Loeligerd9b94f22005-07-25 14:05:07 -050051#define CONFIG_DDR_ECC /* only for ECC DDR module */
Wolfgang Denk452e8e72005-08-08 00:47:14 +020052#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
Jon Loeligerd9b94f22005-07-25 14:05:07 -050053
Kumar Gala45f21662008-01-16 09:06:48 -060054#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk384cc682005-04-03 22:35:21 +000055
56/*
57 * sysclk for MPC85xx
58 *
59 * Two valid values are:
60 * 33000000
61 * 66000000
62 *
63 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
64 * is likely the desired value here, so that is now the default.
65 * The board, however, can run at 66MHz. In any event, this value
66 * must match the settings of some switches. Details can be found
67 * in the README.mpc85xxads.
68 */
69
70#ifndef CONFIG_SYS_CLK_FREQ
71#define CONFIG_SYS_CLK_FREQ 66000000
72#endif
73
74
75/*
76 * These can be toggled for performance analysis, otherwise use default.
77 */
78#define CONFIG_L2_CACHE /* toggle L2 cache */
79#define CONFIG_BTB /* toggle branch predition */
80#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
81
82#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
83
84#undef CFG_DRAM_TEST /* memory test, takes time */
85#define CFG_MEMTEST_START 0x00200000 /* memtest region */
86#define CFG_MEMTEST_END 0x00400000
87
88
89/*
90 * Base addresses -- Note these are effective addresses where the
91 * actual resources get mapped (not physical addresses)
92 */
93#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
94#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
Kumar Galaf69766e2008-01-30 14:55:14 -060095#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
wdenk384cc682005-04-03 22:35:21 +000096#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
97
98
99/*
100 * DDR Setup
101 */
102#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
103#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
104
105#if defined(CONFIG_SPD_EEPROM)
106 /*
107 * Determine DDR configuration from I2C interface.
108 */
Wolfgang Denk992b4022005-08-05 11:47:10 +0200109 #define SPD_EEPROM_ADDRESS 0x58 /* DDR DIMM */
wdenk384cc682005-04-03 22:35:21 +0000110
111#else
112 /*
113 * Manually set up DDR parameters
114 */
115 #define CFG_SDRAM_SIZE 256 /* DDR is 256 MB */
116 #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-256MB */
117 #define CFG_DDR_CS0_CONFIG 0x80000102
118 #define CFG_DDR_TIMING_1 0x47444321
119 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
120 #define CFG_DDR_CONTROL 0xc2008000 /* unbuffered,no DYN_PWR */
121 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
122 #define CFG_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
123#endif
124
125
126/*
127 * SDRAM on the Local Bus
128 */
129#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
130#define CFG_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */
131
132#define CFG_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */
133#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
134
135#define CFG_OR0_PRELIM 0xfe006f67 /* 32 MB Flash */
136#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
137#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
138#undef CFG_FLASH_CHECKSUM
139#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
140#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
141
142#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
143
144
145#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
146#define CFG_RAMBOOT
147#else
148#undef CFG_RAMBOOT
149#endif
150
Wolfgang Denk992b4022005-08-05 11:47:10 +0200151#define CFG_FLASH_CFI_DRIVER
152#define CFG_FLASH_CFI
153#define CFG_FLASH_EMPTY_INFO
154
155#undef CONFIG_CLOCKS_IN_MHZ
156
wdenk384cc682005-04-03 22:35:21 +0000157/*
158 * Local Bus Definitions
159 */
wdenk384cc682005-04-03 22:35:21 +0000160#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
161#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
162#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
163#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk8b0bfc62005-04-03 23:11:38 +0000164
wdenk384cc682005-04-03 22:35:21 +0000165
166#define CONFIG_L1_INIT_RAM
167#define CFG_INIT_RAM_LOCK 1
168#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
169#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
170
171#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
172#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
173#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
174
175#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
176#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
177
178/* Serial Port */
179#define CONFIG_CONS_INDEX 1
180#undef CONFIG_SERIAL_SOFTWARE_FIFO
181#define CFG_NS16550
182#define CFG_NS16550_SERIAL
183#define CFG_NS16550_REG_SIZE 1
184#define CFG_NS16550_CLK get_bus_freq(0)
185
186#define CFG_BAUDRATE_TABLE \
187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
188
189#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
190#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
191
192/* Use the HUSH parser */
193#define CFG_HUSH_PARSER
194#ifdef CFG_HUSH_PARSER
195#define CFG_PROMPT_HUSH_PS2 "> "
196#endif
197
Jon Loeliger20476722006-10-20 15:50:15 -0500198/*
199 * I2C
200 */
201#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
202#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk384cc682005-04-03 22:35:21 +0000203#undef CONFIG_SOFT_I2C /* I2C bit-banged */
204#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
205#define CFG_I2C_SLAVE 0x7F
206#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500207#define CFG_I2C_OFFSET 0x3000
wdenk384cc682005-04-03 22:35:21 +0000208
209/*
210 * EEPROM configuration
211 */
212#define CFG_I2C_EEPROM_ADDR 0x58
213#define CFG_I2C_EEPROM_ADDR_LEN 1
214#define CFG_EEPROM_PAGE_WRITE_BITS 4
215#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
216
217/*
218 * RTC configuration
219 */
220#define CONFIG_RTC_PCF8563
221#define CFG_I2C_RTC_ADDR 0x51
222
223/* RapidIO MMU */
224#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
225#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
226#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
227
228/*
229 * General PCI
230 * Addresses are mapped 1-1.
231 */
232#define CFG_PCI1_MEM_BASE 0x80000000
233#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
234#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
235#define CFG_PCI1_IO_BASE 0xe2000000
236#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
237#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
238
239#if defined(CONFIG_PCI)
240
241#define CONFIG_NET_MULTI
242#define CONFIG_PCI_PNP /* do pci plug-and-play */
243
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200244#define CONFIG_EEPRO100
Wolfgang Denk29fe1c02005-09-21 09:59:55 +0200245#define CONFIG_E1000
246#undef CONFIG_TULIP
wdenk384cc682005-04-03 22:35:21 +0000247
248#if !defined(CONFIG_PCI_PNP)
249 #define PCI_ENET0_IOADDR 0xe0000000
250 #define PCI_ENET0_MEMADDR 0xe0000000
251 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
252#endif
253
254#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
255#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
256
257#endif /* CONFIG_PCI */
258
259
260#if defined(CONFIG_TSEC_ENET)
261
262#ifndef CONFIG_NET_MULTI
263#define CONFIG_NET_MULTI 1
264#endif
265
266#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500267#define CONFIG_TSEC1 1
268#define CONFIG_TSEC1_NAME "TSEC0"
269#define CONFIG_TSEC2 1
270#define CONFIG_TSEC2_NAME "TSEC1"
Wolfgang Denk992b4022005-08-05 11:47:10 +0200271#define TSEC1_PHY_ADDR 0
272#define TSEC2_PHY_ADDR 1
wdenk384cc682005-04-03 22:35:21 +0000273#define TSEC1_PHYIDX 0
274#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500275#define TSEC1_FLAGS TSEC_GIGABIT
276#define TSEC2_FLAGS TSEC_GIGABIT
wdenk384cc682005-04-03 22:35:21 +0000277
278#define CONFIG_MPC85XX_FEC 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500279#define CONFIG_MPC85XX_FEC_NAME "FEC"
Wolfgang Denk992b4022005-08-05 11:47:10 +0200280#define FEC_PHY_ADDR 3
wdenk384cc682005-04-03 22:35:21 +0000281#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500282#define FEC_FLAGS 0
wdenk384cc682005-04-03 22:35:21 +0000283
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500284/* Options are: TSEC[0-1] */
285#define CONFIG_ETHPRIME "TSEC0"
wdenk384cc682005-04-03 22:35:21 +0000286
Andy Fleming10327dc2007-08-16 16:35:02 -0500287#define CONFIG_HAS_ETH0
wdenk384cc682005-04-03 22:35:21 +0000288#define CONFIG_HAS_ETH1 1
289#define CONFIG_HAS_ETH2 1
290
291#endif /* CONFIG_TSEC_ENET */
292
293
294/*
295 * Environment
296 */
297#ifndef CFG_RAMBOOT
298 #define CFG_ENV_IS_IN_FLASH 1
299 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x80000)
300 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
301 #define CFG_ENV_SIZE 0x2000
302#else
303 #define CFG_NO_FLASH 1 /* Flash is not usable now */
304 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
305 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
306 #define CFG_ENV_SIZE 0x2000
307#endif
308
309#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
310#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
311
Jon Loeliger2835e512007-06-13 13:22:08 -0500312
313/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500314 * BOOTP options
315 */
316#define CONFIG_BOOTP_BOOTFILESIZE
317#define CONFIG_BOOTP_BOOTPATH
318#define CONFIG_BOOTP_GATEWAY
319#define CONFIG_BOOTP_HOSTNAME
320
321
322/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500323 * Command line configuration.
324 */
325#include <config_cmd_default.h>
326
327#define CONFIG_CMD_PING
328#define CONFIG_CMD_I2C
329#define CONFIG_CMD_MII
330#define CONFIG_CMD_DATE
331#define CONFIG_CMD_EEPROM
332
333#if defined(CONFIG_PCI)
334 #define CONFIG_CMD_PCI
wdenk384cc682005-04-03 22:35:21 +0000335#endif
336
Jon Loeliger2835e512007-06-13 13:22:08 -0500337#if defined(CFG_RAMBOOT)
338 #undef CONFIG_CMD_ENV
339 #undef CONFIG_CMD_LOADS
340#endif
341
wdenk384cc682005-04-03 22:35:21 +0000342
343#undef CONFIG_WATCHDOG /* watchdog disabled */
344
345/*
346 * Miscellaneous configurable options
347 */
348#define CFG_LONGHELP /* undef to save memory */
349#define CFG_LOAD_ADDR 0x2000000 /* default load address */
350#define CFG_PROMPT "=> " /* Monitor Command Prompt */
351
Jon Loeliger2835e512007-06-13 13:22:08 -0500352#if defined(CONFIG_CMD_KGDB)
wdenk384cc682005-04-03 22:35:21 +0000353 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
354#else
355 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
356#endif
357
358#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
359#define CFG_MAXARGS 16 /* max number of command args */
360#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
361#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
362#define CONFIG_LOOPW
363
364/*
365 * For booting Linux, the board info and command line data
366 * have to be in the first 8 MB of memory, since this is
367 * the maximum mapped by the Linux kernel during initialization.
368 */
369#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
370
wdenk384cc682005-04-03 22:35:21 +0000371/*
372 * Internal Definitions
373 *
374 * Boot Flags
375 */
376#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
377#define BOOTFLAG_WARM 0x02 /* Software reboot */
378
Jon Loeliger2835e512007-06-13 13:22:08 -0500379#if defined(CONFIG_CMD_KGDB)
wdenk384cc682005-04-03 22:35:21 +0000380#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
381#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
382#endif
383
384
385/*
386 * Environment Configuration
387 */
388
389/* The mac addresses for all ethernet interface */
390#if defined(CONFIG_TSEC_ENET)
391#define CONFIG_ETHADDR 00:40:42:01:00:00
392#define CONFIG_ETH1ADDR 00:40:42:01:00:01
393#define CONFIG_ETH2ADDR 00:40:42:01:00:02
394#endif
395
Wolfgang Denk992b4022005-08-05 11:47:10 +0200396
397#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
398#define CONFIG_BOOTFILE pm854/uImage
399
400#define CONFIG_HOSTNAME pm854
wdenk384cc682005-04-03 22:35:21 +0000401#define CONFIG_IPADDR 192.168.0.103
Wolfgang Denk992b4022005-08-05 11:47:10 +0200402#define CONFIG_SERVERIP 192.168.0.64
wdenk384cc682005-04-03 22:35:21 +0000403#define CONFIG_GATEWAYIP 192.168.0.1
404#define CONFIG_NETMASK 255.255.255.0
405
406#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
407
408#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
409#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
410
411#define CONFIG_BAUDRATE 9600
412
413#define CONFIG_EXTRA_ENV_SETTINGS \
414 "netdev=eth0\0" \
415 "consoledev=ttyS0\0" \
416 "ramdiskaddr=400000\0" \
Wolfgang Denk992b4022005-08-05 11:47:10 +0200417 "ramdiskfile=pm854/uRamdisk\0"
wdenk384cc682005-04-03 22:35:21 +0000418
419#define CONFIG_NFSBOOTCOMMAND \
420 "setenv bootargs root=/dev/nfs rw " \
421 "nfsroot=$serverip:$rootpath " \
422 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
423 "console=$consoledev,$baudrate $othbootargs;" \
424 "tftp $loadaddr $bootfile;" \
425 "bootm $loadaddr"
426
427#define CONFIG_RAMBOOTCOMMAND \
428 "setenv bootargs root=/dev/ram rw " \
429 "console=$consoledev,$baudrate $othbootargs;" \
430 "tftp $ramdiskaddr $ramdiskfile;" \
431 "tftp $loadaddr $bootfile;" \
432 "bootm $loadaddr $ramdiskaddr"
433
434#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
435
436#endif /* __CONFIG_H */