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Magnus Lilja8449f282009-07-01 01:07:55 +02001/*
2 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
3 *
4 * (C) Copyright 2004
5 * Texas Instruments.
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Kshitij Gupta <kshitij@ti.com>
8 *
9 * Configuration settings for the Freescale i.MX31 PDK board.
10 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
Magnus Lilja8449f282009-07-01 01:07:55 +020012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Stefano Babic86271112011-03-14 15:43:56 +010017#include <asm/arch/imx-regs.h>
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010018
Magnus Lilja8449f282009-07-01 01:07:55 +020019/* High Level Configuration Options */
Masahiro Yamada3fd968e2014-11-06 14:59:37 +090020#define CONFIG_MX31 /* This is a mx31 */
Magnus Lilja8449f282009-07-01 01:07:55 +020021
Magnus Liljaf93f2192014-08-05 19:03:07 +020022#define CONFIG_SYS_GENERIC_BOARD
23
Magnus Lilja8449f282009-07-01 01:07:55 +020024#define CONFIG_DISPLAY_CPUINFO
25#define CONFIG_DISPLAY_BOARDINFO
26
Fabio Estevame89f1f92011-04-26 11:04:37 +000027#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
28#define CONFIG_SETUP_MEMORY_TAGS
29#define CONFIG_INITRD_TAG
Magnus Lilja8449f282009-07-01 01:07:55 +020030
Fabio Estevam9aa3c6a2011-09-22 08:07:14 +000031#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
32
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000033#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
35#define CONFIG_SPL_MAX_SIZE 2048
36#define CONFIG_SPL_NAND_SUPPORT
Andreas Bießmannb1573152013-04-18 22:48:48 +000037#define CONFIG_SPL_LIBGENERIC_SUPPORT
Heiko Schocher80402f32015-06-29 09:10:46 +020038#define CONFIG_SPL_SERIAL_SUPPORT
Benoît Thébaudeauda962b72013-04-11 09:35:51 +000039
40#define CONFIG_SPL_TEXT_BASE 0x87dc0000
41#define CONFIG_SYS_TEXT_BASE 0x87e00000
42
43#ifndef CONFIG_SPL_BUILD
Magnus Lilja8449f282009-07-01 01:07:55 +020044#define CONFIG_SKIP_LOWLEVEL_INIT
Magnus Liljad08e5ca2009-07-04 10:31:24 +020045#endif
Magnus Lilja8449f282009-07-01 01:07:55 +020046
47/*
48 * Size of malloc() pool
49 */
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010050#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
Magnus Lilja8449f282009-07-01 01:07:55 +020051
52/*
53 * Hardware drivers
54 */
55
Fabio Estevame89f1f92011-04-26 11:04:37 +000056#define CONFIG_MXC_UART
Stefano Babic40f6fff2011-11-22 15:22:39 +010057#define CONFIG_MXC_UART_BASE UART1_BASE
Stefano Babic6f2a4be2011-09-07 10:51:43 +000058#define CONFIG_MXC_GPIO
Magnus Lilja8449f282009-07-01 01:07:55 +020059
Fabio Estevame89f1f92011-04-26 11:04:37 +000060#define CONFIG_HARD_SPI
61#define CONFIG_MXC_SPI
Magnus Lilja8449f282009-07-01 01:07:55 +020062#define CONFIG_DEFAULT_SPI_BUS 1
Stefano Babic9f481e92010-08-23 20:41:19 +020063#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Magnus Lilja8449f282009-07-01 01:07:55 +020064
Stefano Babic877a4382011-10-08 11:04:22 +020065/* PMIC Controller */
Łukasz Majewskibe3b51a2012-11-13 03:22:14 +000066#define CONFIG_POWER
67#define CONFIG_POWER_SPI
68#define CONFIG_POWER_FSL
Stefano Babicdfe5e142010-04-16 17:11:19 +020069#define CONFIG_FSL_PMIC_BUS 1
70#define CONFIG_FSL_PMIC_CS 2
71#define CONFIG_FSL_PMIC_CLK 1000000
Stefano Babic9f481e92010-08-23 20:41:19 +020072#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babic877a4382011-10-08 11:04:22 +020073#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam4e8b7542011-10-24 06:44:15 +000074#define CONFIG_RTC_MC13XXX
Magnus Lilja8449f282009-07-01 01:07:55 +020075
Magnus Lilja8449f282009-07-01 01:07:55 +020076/* allow to overwrite serial and ethaddr */
77#define CONFIG_ENV_OVERWRITE
78#define CONFIG_CONS_INDEX 1
79#define CONFIG_BAUDRATE 115200
Magnus Lilja8449f282009-07-01 01:07:55 +020080
81/***********************************************************
82 * Command definition
83 ***********************************************************/
Magnus Lilja8449f282009-07-01 01:07:55 +020084#define CONFIG_CMD_MII
85#define CONFIG_CMD_PING
Fabio Estevamfc971022011-06-15 03:36:23 +000086#define CONFIG_CMD_DHCP
Magnus Lilja8449f282009-07-01 01:07:55 +020087#define CONFIG_CMD_SPI
88#define CONFIG_CMD_DATE
Magnus Lilja38a8b3e2010-01-17 17:46:11 +010089#define CONFIG_CMD_NAND
Fabio Estevam0c23d842012-04-23 06:31:18 +000090#define CONFIG_CMD_BOOTZ
Magnus Lilja8449f282009-07-01 01:07:55 +020091
Helmut Raiger9660e442011-10-20 04:19:47 +000092#define CONFIG_BOARD_LATE_INIT
Fabio Estevamb73850f2011-04-10 08:17:50 +000093
Fabio Estevam562e6c62012-11-16 05:09:09 +000094#define CONFIG_BOOTDELAY 1
Magnus Lilja8449f282009-07-01 01:07:55 +020095
96#define CONFIG_EXTRA_ENV_SETTINGS \
97 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
98 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
99 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
100 "bootcmd=run bootcmd_net\0" \
101 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100102 "tftpboot 0x81000000 uImage-mx31; bootm\0" \
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000103 "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100104 "nand erase 0x0 0x40000; " \
105 "nand write 0x81000000 0x0 0x40000\0"
Magnus Lilja8449f282009-07-01 01:07:55 +0200106
Fabio Estevame89f1f92011-04-26 11:04:37 +0000107#define CONFIG_SMC911X
Ben Warren736fead2009-07-20 22:01:11 -0700108#define CONFIG_SMC911X_BASE 0xB6000000
Fabio Estevame89f1f92011-04-26 11:04:37 +0000109#define CONFIG_SMC911X_32_BIT
Magnus Lilja8449f282009-07-01 01:07:55 +0200110
111/*
112 * Miscellaneous configurable options
113 */
114#define CONFIG_SYS_LONGHELP /* undef to save memory */
Magnus Lilja8449f282009-07-01 01:07:55 +0200115#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Magnus Lilja8449f282009-07-01 01:07:55 +0200116/* max number of command args */
117#define CONFIG_SYS_MAXARGS 16
118/* Boot Argument Buffer Size */
119#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
120
121/* memtest works on */
122#define CONFIG_SYS_MEMTEST_START 0x80000000
Fabio Estevam304e49e2012-02-09 14:25:07 +0000123#define CONFIG_SYS_MEMTEST_END 0x80010000
Magnus Lilja8449f282009-07-01 01:07:55 +0200124
125/* default load address */
126#define CONFIG_SYS_LOAD_ADDR 0x81000000
127
Fabio Estevame89f1f92011-04-26 11:04:37 +0000128#define CONFIG_CMDLINE_EDITING
Magnus Lilja8449f282009-07-01 01:07:55 +0200129
130/*-----------------------------------------------------------------------
Magnus Lilja8449f282009-07-01 01:07:55 +0200131 * Physical Memory Map
132 */
133#define CONFIG_NR_DRAM_BANKS 1
134#define PHYS_SDRAM_1 CSD0_BASE
135#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
Fabio Estevame89f1f92011-04-26 11:04:37 +0000136#define CONFIG_BOARD_EARLY_INIT_F
Magnus Lilja8449f282009-07-01 01:07:55 +0200137
Fabio Estevamed3df722011-02-09 01:17:55 +0000138#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
139#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
140#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
Fabio Estevam026ca652011-07-04 09:29:46 +0000141#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
142 GENERATED_GBL_DATA_SIZE)
143#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000144 CONFIG_SYS_INIT_RAM_SIZE)
Fabio Estevamed3df722011-02-09 01:17:55 +0000145
Magnus Lilja8449f282009-07-01 01:07:55 +0200146/*-----------------------------------------------------------------------
147 * FLASH and environment organization
148 */
149/* No NOR flash present */
Fabio Estevame89f1f92011-04-26 11:04:37 +0000150#define CONFIG_SYS_NO_FLASH
Magnus Lilja8449f282009-07-01 01:07:55 +0200151
Fabio Estevame89f1f92011-04-26 11:04:37 +0000152#define CONFIG_ENV_IS_IN_NAND
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100153#define CONFIG_ENV_OFFSET 0x40000
154#define CONFIG_ENV_OFFSET_REDUND 0x60000
155#define CONFIG_ENV_SIZE (128 * 1024)
Magnus Lilja8449f282009-07-01 01:07:55 +0200156
Magnus Lilja38a8b3e2010-01-17 17:46:11 +0100157/*
158 * NAND driver
159 */
160#define CONFIG_NAND_MXC
161#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
162#define CONFIG_SYS_MAX_NAND_DEVICE 1
163#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
164#define CONFIG_MXC_NAND_HWECC
165#define CONFIG_SYS_NAND_LARGEPAGE
Magnus Lilja8449f282009-07-01 01:07:55 +0200166
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200167/* NAND configuration for the NAND_SPL */
168
169/* Start copying real U-boot from the second page */
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000170#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
171#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200172/* Load U-Boot to this address */
Benoît Thébaudeauda962b72013-04-11 09:35:51 +0000173#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200174#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
175
176#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
177#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
178#define CONFIG_SYS_NAND_PAGE_COUNT 64
179#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
180#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
181
182
183/* Configuration of lowlevel_init.S (clocks and SDRAM) */
184#define CCM_CCMR_SETUP 0x074B0BF5
Benoît Thébaudeau9e0081d2012-08-14 08:43:07 +0000185#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
186 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
187 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
188 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
189#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
Magnus Liljad08e5ca2009-07-04 10:31:24 +0200190 PLL_MFN(12))
191
192#define ESDMISC_MDDR_SETUP 0x00000004
193#define ESDMISC_MDDR_RESET_DL 0x0000000c
194#define ESDCFG0_MDDR_SETUP 0x006ac73a
195
196#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
197#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
198 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
199#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
200#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
201#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
202#define ESDCTL_RW ESDCTL_SETTINGS
203
Magnus Lilja8449f282009-07-01 01:07:55 +0200204#endif /* __CONFIG_H */