blob: cea08e6f08dfe8626c53198801f451ad5818d942 [file] [log] [blame]
maxims@google.com14e4b142017-01-18 13:44:56 -08001/*
2 * This device tree is copied from
maxims@google.com17c5fb12017-04-17 12:00:20 -07003 * https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
maxims@google.com14e4b142017-01-18 13:44:56 -08004 */
5#include "skeleton.dtsi"
6
7/ {
8 model = "Aspeed BMC";
9 compatible = "aspeed,ast2500";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&vic>;
13
Cédric Le Goater6bdccc32018-10-29 07:06:39 +010014 aliases {
15 i2c0 = &i2c0;
16 i2c1 = &i2c1;
17 i2c2 = &i2c2;
18 i2c3 = &i2c3;
19 i2c4 = &i2c4;
20 i2c5 = &i2c5;
21 i2c6 = &i2c6;
22 i2c7 = &i2c7;
23 i2c8 = &i2c8;
24 i2c9 = &i2c9;
25 i2c10 = &i2c10;
26 i2c11 = &i2c11;
27 i2c12 = &i2c12;
28 i2c13 = &i2c13;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &vuart;
35 };
36
maxims@google.com14e4b142017-01-18 13:44:56 -080037 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 cpu@0 {
42 compatible = "arm,arm1176jzf-s";
43 device_type = "cpu";
44 reg = <0>;
45 };
46 };
47
Cédric Le Goater6bdccc32018-10-29 07:06:39 +010048 memory@80000000 {
49 device_type = "memory";
50 reg = <0x80000000 0>;
51 };
52
maxims@google.com14e4b142017-01-18 13:44:56 -080053 ahb {
54 compatible = "simple-bus";
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
Cédric Le Goater6bdccc32018-10-29 07:06:39 +010059 fmc: flash-controller@1e620000 {
60 reg = < 0x1e620000 0xc4
61 0x20000000 0x10000000 >;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 compatible = "aspeed,ast2500-fmc";
65 status = "disabled";
66 interrupts = <19>;
67 flash@0 {
68 reg = < 0 >;
69 compatible = "jedec,spi-nor";
70 status = "disabled";
71 };
72 flash@1 {
73 reg = < 1 >;
74 compatible = "jedec,spi-nor";
75 status = "disabled";
76 };
77 flash@2 {
78 reg = < 2 >;
79 compatible = "jedec,spi-nor";
80 status = "disabled";
81 };
82 };
83
84 spi1: flash-controller@1e630000 {
85 reg = < 0x1e630000 0xc4
86 0x30000000 0x08000000 >;
87 #address-cells = <1>;
88 #size-cells = <0>;
89 compatible = "aspeed,ast2500-spi";
90 status = "disabled";
91 flash@0 {
92 reg = < 0 >;
93 compatible = "jedec,spi-nor";
94 status = "disabled";
95 };
96 flash@1 {
97 reg = < 1 >;
98 compatible = "jedec,spi-nor";
99 status = "disabled";
100 };
101 };
102
103 spi2: flash-controller@1e631000 {
104 reg = < 0x1e631000 0xc4
105 0x38000000 0x08000000 >;
106 #address-cells = <1>;
107 #size-cells = <0>;
108 compatible = "aspeed,ast2500-spi";
109 status = "disabled";
110 flash@0 {
111 reg = < 0 >;
112 compatible = "jedec,spi-nor";
113 status = "disabled";
114 };
115 flash@1 {
116 reg = < 1 >;
117 compatible = "jedec,spi-nor";
118 status = "disabled";
119 };
120 };
121
maxims@google.com14e4b142017-01-18 13:44:56 -0800122 vic: interrupt-controller@1e6c0080 {
123 compatible = "aspeed,ast2400-vic";
124 interrupt-controller;
125 #interrupt-cells = <1>;
126 valid-sources = <0xfefff7ff 0x0807ffff>;
127 reg = <0x1e6c0080 0x80>;
128 };
129
maxims@google.com17c5fb12017-04-17 12:00:20 -0700130 mac0: ethernet@1e660000 {
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100131 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
maxims@google.com17c5fb12017-04-17 12:00:20 -0700132 reg = <0x1e660000 0x180>;
133 interrupts = <2>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700134 status = "disabled";
135 };
136
137 mac1: ethernet@1e680000 {
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100138 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
maxims@google.com17c5fb12017-04-17 12:00:20 -0700139 reg = <0x1e680000 0x180>;
140 interrupts = <3>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100141 status = "disabled";
142 };
143
144 ehci0: usb@1e6a1000 {
145 compatible = "aspeed,ast2500-ehci", "generic-ehci";
146 reg = <0x1e6a1000 0x100>;
147 interrupts = <5>;
148 status = "disabled";
149 };
150
151 ehci1: usb@1e6a3000 {
152 compatible = "aspeed,ast2500-ehci", "generic-ehci";
153 reg = <0x1e6a3000 0x100>;
154 interrupts = <13>;
155 status = "disabled";
156 };
157
158 uhci: usb@1e6b0000 {
159 compatible = "aspeed,ast2500-uhci", "generic-uhci";
160 reg = <0x1e6b0000 0x100>;
161 interrupts = <14>;
162 #ports = <2>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700163 status = "disabled";
164 };
165
maxims@google.com14e4b142017-01-18 13:44:56 -0800166 apb {
167 compatible = "simple-bus";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges;
171
maxims@google.com17c5fb12017-04-17 12:00:20 -0700172 syscon: syscon@1e6e2000 {
173 compatible = "aspeed,g5-scu", "syscon", "simple-mfd";
174 reg = <0x1e6e2000 0x1a8>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100175 #clock-cells = <1>;
176 #reset-cells = <1>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700177
178 pinctrl: pinctrl {
179 compatible = "aspeed,g5-pinctrl";
180 aspeed,external-nodes = <&gfx &lhc>;
181
maxims@google.com17c5fb12017-04-17 12:00:20 -0700182 };
183 };
184
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100185 rng: hwrng@1e6e2078 {
186 compatible = "timeriomem_rng";
187 reg = <0x1e6e2078 0x4>;
188 period = <1>;
189 quality = <100>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800190 };
191
maxims@google.com17c5fb12017-04-17 12:00:20 -0700192 gfx: display@1e6e6000 {
193 compatible = "aspeed,ast2500-gfx", "syscon";
194 reg = <0x1e6e6000 0x1000>;
195 reg-io-width = <4>;
196 };
197
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100198 adc: adc@1e6e9000 {
199 compatible = "aspeed,ast2500-adc";
200 reg = <0x1e6e9000 0xb0>;
201 #io-channel-cells = <1>;
202 status = "disabled";
203 };
204
maxims@google.com14e4b142017-01-18 13:44:56 -0800205 sram@1e720000 {
206 compatible = "mmio-sram";
207 reg = <0x1e720000 0x9000>; // 36K
208 };
209
Joel Stanley0b2a7492022-06-23 18:35:29 +0930210 sdmmc: sd-controller@1e740000 {
211 compatible = "aspeed,ast2500-sd-controller";
212 reg = <0x1e740000 0x100>;
213 #address-cells = <1>;
214 #size-cells = <1>;
215 ranges = <0 0x1e740000 0x10000>;
216 clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
217 status = "disabled";
218
219 sdhci0: sdhci@100 {
220 compatible = "aspeed,ast2500-sdhci";
221 reg = <0x100 0x100>;
222 interrupts = <26>;
223 sdhci,auto-cmd12;
224 clocks = <&scu ASPEED_CLK_SDIO>;
225 status = "disabled";
226 };
227
228 sdhci1: sdhci@200 {
229 compatible = "aspeed,ast2500-sdhci";
230 reg = <0x200 0x100>;
231 interrupts = <26>;
232 sdhci,auto-cmd12;
233 clocks = <&scu ASPEED_CLK_SDIO>;
234 status = "disabled";
235 };
236 };
237
maxims@google.com17c5fb12017-04-17 12:00:20 -0700238 gpio: gpio@1e780000 {
239 #gpio-cells = <2>;
240 gpio-controller;
241 compatible = "aspeed,ast2500-gpio";
242 reg = <0x1e780000 0x1000>;
243 interrupts = <20>;
244 gpio-ranges = <&pinctrl 0 0 220>;
Andrew Jeffery7da87542022-02-16 10:26:57 +1030245 ngpios = <228>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700246 interrupt-controller;
247 };
248
maxims@google.com14e4b142017-01-18 13:44:56 -0800249 timer: timer@1e782000 {
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100250 /* This timer is a Faraday FTTMR010 derivative */
maxims@google.com14e4b142017-01-18 13:44:56 -0800251 compatible = "aspeed,ast2400-timer";
252 reg = <0x1e782000 0x90>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800253 };
254
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100255 uart1: serial@1e783000 {
256 compatible = "ns16550a";
257 reg = <0x1e783000 0x20>;
258 reg-shift = <2>;
259 interrupts = <9>;
260 no-loopback-test;
261 status = "disabled";
262 };
maxims@google.com17c5fb12017-04-17 12:00:20 -0700263
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100264 uart5: serial@1e784000 {
265 compatible = "ns16550a";
266 reg = <0x1e784000 0x20>;
267 reg-shift = <2>;
268 interrupts = <10>;
269 no-loopback-test;
270 status = "disabled";
271 };
272
273 wdt1: watchdog@1e785000 {
maxims@google.com14e4b142017-01-18 13:44:56 -0800274 compatible = "aspeed,wdt";
275 reg = <0x1e785000 0x1c>;
276 interrupts = <27>;
277 };
278
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100279 wdt2: watchdog@1e785020 {
maxims@google.com14e4b142017-01-18 13:44:56 -0800280 compatible = "aspeed,wdt";
281 reg = <0x1e785020 0x1c>;
282 interrupts = <27>;
283 status = "disabled";
284 };
285
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100286 wdt3: watchdog@1e785040 {
maxims@google.com14e4b142017-01-18 13:44:56 -0800287 compatible = "aspeed,wdt";
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100288 reg = <0x1e785040 0x1c>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800289 status = "disabled";
290 };
291
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100292 pwm_tacho: pwm-tacho-controller@1e786000 {
293 compatible = "aspeed,ast2500-pwm-tacho";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 reg = <0x1e786000 0x1000>;
297 status = "disabled";
298 };
299
300 vuart: serial@1e787000 {
301 compatible = "aspeed,ast2500-vuart";
302 reg = <0x1e787000 0x40>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800303 reg-shift = <2>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100304 interrupts = <8>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800305 no-loopback-test;
306 status = "disabled";
307 };
308
maxims@google.com17c5fb12017-04-17 12:00:20 -0700309 lpc: lpc@1e789000 {
310 compatible = "aspeed,ast2500-lpc", "simple-mfd";
311 reg = <0x1e789000 0x1000>;
312
313 #address-cells = <1>;
314 #size-cells = <1>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100315 ranges = <0x0 0x1e789000 0x1000>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700316
317 lpc_bmc: lpc-bmc@0 {
318 compatible = "aspeed,ast2500-lpc-bmc";
319 reg = <0x0 0x80>;
320 };
321
322 lpc_host: lpc-host@80 {
323 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
324 reg = <0x80 0x1e0>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100325 reg-io-width = <4>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700326
327 #address-cells = <1>;
328 #size-cells = <1>;
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100329 ranges = <0x0 0x80 0x1e0>;
maxims@google.com17c5fb12017-04-17 12:00:20 -0700330
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100331 lpc_ctrl: lpc-ctrl@0 {
332 compatible = "aspeed,ast2500-lpc-ctrl";
333 reg = <0x0 0x80>;
334 status = "disabled";
335 };
336
337 lpc_snoop: lpc-snoop@0 {
338 compatible = "aspeed,ast2500-lpc-snoop";
339 reg = <0x0 0x80>;
340 interrupts = <8>;
341 status = "disabled";
342 };
maxims@google.com17c5fb12017-04-17 12:00:20 -0700343
344 lhc: lhc@20 {
345 compatible = "aspeed,ast2500-lhc";
346 reg = <0x20 0x24 0x48 0x8>;
347 };
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100348
349 lpc_reset: reset-controller@18 {
350 compatible = "aspeed,ast2500-lpc-reset";
351 reg = <0x18 0x4>;
352 #reset-cells = <1>;
353 };
354
355 ibt: ibt@c0 {
356 compatible = "aspeed,ast2500-ibt-bmc";
357 reg = <0xc0 0x18>;
358 interrupts = <8>;
359 status = "disabled";
360 };
maxims@google.com17c5fb12017-04-17 12:00:20 -0700361 };
362 };
363
maxims@google.com14e4b142017-01-18 13:44:56 -0800364 uart2: serial@1e78d000 {
365 compatible = "ns16550a";
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100366 reg = <0x1e78d000 0x20>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800367 reg-shift = <2>;
368 interrupts = <32>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800369 no-loopback-test;
370 status = "disabled";
371 };
372
373 uart3: serial@1e78e000 {
374 compatible = "ns16550a";
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100375 reg = <0x1e78e000 0x20>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800376 reg-shift = <2>;
377 interrupts = <33>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800378 no-loopback-test;
379 status = "disabled";
380 };
381
382 uart4: serial@1e78f000 {
383 compatible = "ns16550a";
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100384 reg = <0x1e78f000 0x20>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800385 reg-shift = <2>;
386 interrupts = <34>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800387 no-loopback-test;
388 status = "disabled";
389 };
390
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100391 i2c: i2c@1e78a000 {
392 compatible = "simple-bus";
393 #address-cells = <1>;
394 #size-cells = <1>;
395 ranges = <0 0x1e78a000 0x1000>;
maxims@google.com14e4b142017-01-18 13:44:56 -0800396 };
397 };
398 };
399};
Cédric Le Goater6bdccc32018-10-29 07:06:39 +0100400
401&i2c {
402 i2c_ic: interrupt-controller@0 {
403 #interrupt-cells = <1>;
404 compatible = "aspeed,ast2500-i2c-ic";
405 reg = <0x0 0x40>;
406 interrupts = <12>;
407 interrupt-controller;
408 };
409
410 i2c0: i2c-bus@40 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 #interrupt-cells = <1>;
414
415 reg = <0x40 0x40>;
416 compatible = "aspeed,ast2500-i2c-bus";
417 bus-frequency = <100000>;
418 interrupts = <0>;
419 interrupt-parent = <&i2c_ic>;
420 status = "disabled";
421 /* Does not need pinctrl properties */
422 };
423
424 i2c1: i2c-bus@80 {
425 #address-cells = <1>;
426 #size-cells = <0>;
427 #interrupt-cells = <1>;
428
429 reg = <0x80 0x40>;
430 compatible = "aspeed,ast2500-i2c-bus";
431 bus-frequency = <100000>;
432 interrupts = <1>;
433 interrupt-parent = <&i2c_ic>;
434 status = "disabled";
435 /* Does not need pinctrl properties */
436 };
437
438 i2c2: i2c-bus@c0 {
439 #address-cells = <1>;
440 #size-cells = <0>;
441 #interrupt-cells = <1>;
442
443 reg = <0xc0 0x40>;
444 compatible = "aspeed,ast2500-i2c-bus";
445 bus-frequency = <100000>;
446 interrupts = <2>;
447 interrupt-parent = <&i2c_ic>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_i2c3_default>;
450 status = "disabled";
451 };
452
453 i2c3: i2c-bus@100 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 #interrupt-cells = <1>;
457
458 reg = <0x100 0x40>;
459 compatible = "aspeed,ast2500-i2c-bus";
460 bus-frequency = <100000>;
461 interrupts = <3>;
462 interrupt-parent = <&i2c_ic>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_i2c4_default>;
465 status = "disabled";
466 };
467
468 i2c4: i2c-bus@140 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 #interrupt-cells = <1>;
472
473 reg = <0x140 0x40>;
474 compatible = "aspeed,ast2500-i2c-bus";
475 bus-frequency = <100000>;
476 interrupts = <4>;
477 interrupt-parent = <&i2c_ic>;
478 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_i2c5_default>;
480 status = "disabled";
481 };
482
483 i2c5: i2c-bus@180 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 #interrupt-cells = <1>;
487
488 reg = <0x180 0x40>;
489 compatible = "aspeed,ast2500-i2c-bus";
490 bus-frequency = <100000>;
491 interrupts = <5>;
492 interrupt-parent = <&i2c_ic>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_i2c6_default>;
495 status = "disabled";
496 };
497
498 i2c6: i2c-bus@1c0 {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 #interrupt-cells = <1>;
502
503 reg = <0x1c0 0x40>;
504 compatible = "aspeed,ast2500-i2c-bus";
505 bus-frequency = <100000>;
506 interrupts = <6>;
507 interrupt-parent = <&i2c_ic>;
508 pinctrl-names = "default";
509 pinctrl-0 = <&pinctrl_i2c7_default>;
510 status = "disabled";
511 };
512
513 i2c7: i2c-bus@300 {
514 #address-cells = <1>;
515 #size-cells = <0>;
516 #interrupt-cells = <1>;
517
518 reg = <0x300 0x40>;
519 compatible = "aspeed,ast2500-i2c-bus";
520 bus-frequency = <100000>;
521 interrupts = <7>;
522 interrupt-parent = <&i2c_ic>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_i2c8_default>;
525 status = "disabled";
526 };
527
528 i2c8: i2c-bus@340 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 #interrupt-cells = <1>;
532
533 reg = <0x340 0x40>;
534 compatible = "aspeed,ast2500-i2c-bus";
535 bus-frequency = <100000>;
536 interrupts = <8>;
537 interrupt-parent = <&i2c_ic>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&pinctrl_i2c9_default>;
540 status = "disabled";
541 };
542
543 i2c9: i2c-bus@380 {
544 #address-cells = <1>;
545 #size-cells = <0>;
546 #interrupt-cells = <1>;
547
548 reg = <0x380 0x40>;
549 compatible = "aspeed,ast2500-i2c-bus";
550 bus-frequency = <100000>;
551 interrupts = <9>;
552 interrupt-parent = <&i2c_ic>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&pinctrl_i2c10_default>;
555 status = "disabled";
556 };
557
558 i2c10: i2c-bus@3c0 {
559 #address-cells = <1>;
560 #size-cells = <0>;
561 #interrupt-cells = <1>;
562
563 reg = <0x3c0 0x40>;
564 compatible = "aspeed,ast2500-i2c-bus";
565 bus-frequency = <100000>;
566 interrupts = <10>;
567 interrupt-parent = <&i2c_ic>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_i2c11_default>;
570 status = "disabled";
571 };
572
573 i2c11: i2c-bus@400 {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 #interrupt-cells = <1>;
577
578 reg = <0x400 0x40>;
579 compatible = "aspeed,ast2500-i2c-bus";
580 bus-frequency = <100000>;
581 interrupts = <11>;
582 interrupt-parent = <&i2c_ic>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_i2c12_default>;
585 status = "disabled";
586 };
587
588 i2c12: i2c-bus@440 {
589 #address-cells = <1>;
590 #size-cells = <0>;
591 #interrupt-cells = <1>;
592
593 reg = <0x440 0x40>;
594 compatible = "aspeed,ast2500-i2c-bus";
595 bus-frequency = <100000>;
596 interrupts = <12>;
597 interrupt-parent = <&i2c_ic>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&pinctrl_i2c13_default>;
600 status = "disabled";
601 };
602
603 i2c13: i2c-bus@480 {
604 #address-cells = <1>;
605 #size-cells = <0>;
606 #interrupt-cells = <1>;
607
608 reg = <0x480 0x40>;
609 compatible = "aspeed,ast2500-i2c-bus";
610 bus-frequency = <100000>;
611 interrupts = <13>;
612 interrupt-parent = <&i2c_ic>;
613 pinctrl-names = "default";
614 pinctrl-0 = <&pinctrl_i2c14_default>;
615 status = "disabled";
616 };
617};
618
619&pinctrl {
620 pinctrl_acpi_default: acpi_default {
621 function = "ACPI";
622 groups = "ACPI";
623 };
624
625 pinctrl_adc0_default: adc0_default {
626 function = "ADC0";
627 groups = "ADC0";
628 };
629
630 pinctrl_adc1_default: adc1_default {
631 function = "ADC1";
632 groups = "ADC1";
633 };
634
635 pinctrl_adc10_default: adc10_default {
636 function = "ADC10";
637 groups = "ADC10";
638 };
639
640 pinctrl_adc11_default: adc11_default {
641 function = "ADC11";
642 groups = "ADC11";
643 };
644
645 pinctrl_adc12_default: adc12_default {
646 function = "ADC12";
647 groups = "ADC12";
648 };
649
650 pinctrl_adc13_default: adc13_default {
651 function = "ADC13";
652 groups = "ADC13";
653 };
654
655 pinctrl_adc14_default: adc14_default {
656 function = "ADC14";
657 groups = "ADC14";
658 };
659
660 pinctrl_adc15_default: adc15_default {
661 function = "ADC15";
662 groups = "ADC15";
663 };
664
665 pinctrl_adc2_default: adc2_default {
666 function = "ADC2";
667 groups = "ADC2";
668 };
669
670 pinctrl_adc3_default: adc3_default {
671 function = "ADC3";
672 groups = "ADC3";
673 };
674
675 pinctrl_adc4_default: adc4_default {
676 function = "ADC4";
677 groups = "ADC4";
678 };
679
680 pinctrl_adc5_default: adc5_default {
681 function = "ADC5";
682 groups = "ADC5";
683 };
684
685 pinctrl_adc6_default: adc6_default {
686 function = "ADC6";
687 groups = "ADC6";
688 };
689
690 pinctrl_adc7_default: adc7_default {
691 function = "ADC7";
692 groups = "ADC7";
693 };
694
695 pinctrl_adc8_default: adc8_default {
696 function = "ADC8";
697 groups = "ADC8";
698 };
699
700 pinctrl_adc9_default: adc9_default {
701 function = "ADC9";
702 groups = "ADC9";
703 };
704
705 pinctrl_bmcint_default: bmcint_default {
706 function = "BMCINT";
707 groups = "BMCINT";
708 };
709
710 pinctrl_ddcclk_default: ddcclk_default {
711 function = "DDCCLK";
712 groups = "DDCCLK";
713 };
714
715 pinctrl_ddcdat_default: ddcdat_default {
716 function = "DDCDAT";
717 groups = "DDCDAT";
718 };
719
720 pinctrl_espi_default: espi_default {
721 function = "ESPI";
722 groups = "ESPI";
723 };
724
725 pinctrl_fwspics1_default: fwspics1_default {
726 function = "FWSPICS1";
727 groups = "FWSPICS1";
728 };
729
730 pinctrl_fwspics2_default: fwspics2_default {
731 function = "FWSPICS2";
732 groups = "FWSPICS2";
733 };
734
735 pinctrl_gpid0_default: gpid0_default {
736 function = "GPID0";
737 groups = "GPID0";
738 };
739
740 pinctrl_gpid2_default: gpid2_default {
741 function = "GPID2";
742 groups = "GPID2";
743 };
744
745 pinctrl_gpid4_default: gpid4_default {
746 function = "GPID4";
747 groups = "GPID4";
748 };
749
750 pinctrl_gpid6_default: gpid6_default {
751 function = "GPID6";
752 groups = "GPID6";
753 };
754
755 pinctrl_gpie0_default: gpie0_default {
756 function = "GPIE0";
757 groups = "GPIE0";
758 };
759
760 pinctrl_gpie2_default: gpie2_default {
761 function = "GPIE2";
762 groups = "GPIE2";
763 };
764
765 pinctrl_gpie4_default: gpie4_default {
766 function = "GPIE4";
767 groups = "GPIE4";
768 };
769
770 pinctrl_gpie6_default: gpie6_default {
771 function = "GPIE6";
772 groups = "GPIE6";
773 };
774
775 pinctrl_i2c10_default: i2c10_default {
776 function = "I2C10";
777 groups = "I2C10";
778 };
779
780 pinctrl_i2c11_default: i2c11_default {
781 function = "I2C11";
782 groups = "I2C11";
783 };
784
785 pinctrl_i2c12_default: i2c12_default {
786 function = "I2C12";
787 groups = "I2C12";
788 };
789
790 pinctrl_i2c13_default: i2c13_default {
791 function = "I2C13";
792 groups = "I2C13";
793 };
794
795 pinctrl_i2c14_default: i2c14_default {
796 function = "I2C14";
797 groups = "I2C14";
798 };
799
800 pinctrl_i2c3_default: i2c3_default {
801 function = "I2C3";
802 groups = "I2C3";
803 };
804
805 pinctrl_i2c4_default: i2c4_default {
806 function = "I2C4";
807 groups = "I2C4";
808 };
809
810 pinctrl_i2c5_default: i2c5_default {
811 function = "I2C5";
812 groups = "I2C5";
813 };
814
815 pinctrl_i2c6_default: i2c6_default {
816 function = "I2C6";
817 groups = "I2C6";
818 };
819
820 pinctrl_i2c7_default: i2c7_default {
821 function = "I2C7";
822 groups = "I2C7";
823 };
824
825 pinctrl_i2c8_default: i2c8_default {
826 function = "I2C8";
827 groups = "I2C8";
828 };
829
830 pinctrl_i2c9_default: i2c9_default {
831 function = "I2C9";
832 groups = "I2C9";
833 };
834
835 pinctrl_lad0_default: lad0_default {
836 function = "LAD0";
837 groups = "LAD0";
838 };
839
840 pinctrl_lad1_default: lad1_default {
841 function = "LAD1";
842 groups = "LAD1";
843 };
844
845 pinctrl_lad2_default: lad2_default {
846 function = "LAD2";
847 groups = "LAD2";
848 };
849
850 pinctrl_lad3_default: lad3_default {
851 function = "LAD3";
852 groups = "LAD3";
853 };
854
855 pinctrl_lclk_default: lclk_default {
856 function = "LCLK";
857 groups = "LCLK";
858 };
859
860 pinctrl_lframe_default: lframe_default {
861 function = "LFRAME";
862 groups = "LFRAME";
863 };
864
865 pinctrl_lpchc_default: lpchc_default {
866 function = "LPCHC";
867 groups = "LPCHC";
868 };
869
870 pinctrl_lpcpd_default: lpcpd_default {
871 function = "LPCPD";
872 groups = "LPCPD";
873 };
874
875 pinctrl_lpcplus_default: lpcplus_default {
876 function = "LPCPLUS";
877 groups = "LPCPLUS";
878 };
879
880 pinctrl_lpcpme_default: lpcpme_default {
881 function = "LPCPME";
882 groups = "LPCPME";
883 };
884
885 pinctrl_lpcrst_default: lpcrst_default {
886 function = "LPCRST";
887 groups = "LPCRST";
888 };
889
890 pinctrl_lpcsmi_default: lpcsmi_default {
891 function = "LPCSMI";
892 groups = "LPCSMI";
893 };
894
895 pinctrl_lsirq_default: lsirq_default {
896 function = "LSIRQ";
897 groups = "LSIRQ";
898 };
899
900 pinctrl_mac1link_default: mac1link_default {
901 function = "MAC1LINK";
902 groups = "MAC1LINK";
903 };
904
905 pinctrl_mac2link_default: mac2link_default {
906 function = "MAC2LINK";
907 groups = "MAC2LINK";
908 };
909
910 pinctrl_mdio1_default: mdio1_default {
911 function = "MDIO1";
912 groups = "MDIO1";
913 };
914
915 pinctrl_mdio2_default: mdio2_default {
916 function = "MDIO2";
917 groups = "MDIO2";
918 };
919
920 pinctrl_ncts1_default: ncts1_default {
921 function = "NCTS1";
922 groups = "NCTS1";
923 };
924
925 pinctrl_ncts2_default: ncts2_default {
926 function = "NCTS2";
927 groups = "NCTS2";
928 };
929
930 pinctrl_ncts3_default: ncts3_default {
931 function = "NCTS3";
932 groups = "NCTS3";
933 };
934
935 pinctrl_ncts4_default: ncts4_default {
936 function = "NCTS4";
937 groups = "NCTS4";
938 };
939
940 pinctrl_ndcd1_default: ndcd1_default {
941 function = "NDCD1";
942 groups = "NDCD1";
943 };
944
945 pinctrl_ndcd2_default: ndcd2_default {
946 function = "NDCD2";
947 groups = "NDCD2";
948 };
949
950 pinctrl_ndcd3_default: ndcd3_default {
951 function = "NDCD3";
952 groups = "NDCD3";
953 };
954
955 pinctrl_ndcd4_default: ndcd4_default {
956 function = "NDCD4";
957 groups = "NDCD4";
958 };
959
960 pinctrl_ndsr1_default: ndsr1_default {
961 function = "NDSR1";
962 groups = "NDSR1";
963 };
964
965 pinctrl_ndsr2_default: ndsr2_default {
966 function = "NDSR2";
967 groups = "NDSR2";
968 };
969
970 pinctrl_ndsr3_default: ndsr3_default {
971 function = "NDSR3";
972 groups = "NDSR3";
973 };
974
975 pinctrl_ndsr4_default: ndsr4_default {
976 function = "NDSR4";
977 groups = "NDSR4";
978 };
979
980 pinctrl_ndtr1_default: ndtr1_default {
981 function = "NDTR1";
982 groups = "NDTR1";
983 };
984
985 pinctrl_ndtr2_default: ndtr2_default {
986 function = "NDTR2";
987 groups = "NDTR2";
988 };
989
990 pinctrl_ndtr3_default: ndtr3_default {
991 function = "NDTR3";
992 groups = "NDTR3";
993 };
994
995 pinctrl_ndtr4_default: ndtr4_default {
996 function = "NDTR4";
997 groups = "NDTR4";
998 };
999
1000 pinctrl_nri1_default: nri1_default {
1001 function = "NRI1";
1002 groups = "NRI1";
1003 };
1004
1005 pinctrl_nri2_default: nri2_default {
1006 function = "NRI2";
1007 groups = "NRI2";
1008 };
1009
1010 pinctrl_nri3_default: nri3_default {
1011 function = "NRI3";
1012 groups = "NRI3";
1013 };
1014
1015 pinctrl_nri4_default: nri4_default {
1016 function = "NRI4";
1017 groups = "NRI4";
1018 };
1019
1020 pinctrl_nrts1_default: nrts1_default {
1021 function = "NRTS1";
1022 groups = "NRTS1";
1023 };
1024
1025 pinctrl_nrts2_default: nrts2_default {
1026 function = "NRTS2";
1027 groups = "NRTS2";
1028 };
1029
1030 pinctrl_nrts3_default: nrts3_default {
1031 function = "NRTS3";
1032 groups = "NRTS3";
1033 };
1034
1035 pinctrl_nrts4_default: nrts4_default {
1036 function = "NRTS4";
1037 groups = "NRTS4";
1038 };
1039
1040 pinctrl_oscclk_default: oscclk_default {
1041 function = "OSCCLK";
1042 groups = "OSCCLK";
1043 };
1044
1045 pinctrl_pewake_default: pewake_default {
1046 function = "PEWAKE";
1047 groups = "PEWAKE";
1048 };
1049
1050 pinctrl_pnor_default: pnor_default {
1051 function = "PNOR";
1052 groups = "PNOR";
1053 };
1054
1055 pinctrl_pwm0_default: pwm0_default {
1056 function = "PWM0";
1057 groups = "PWM0";
1058 };
1059
1060 pinctrl_pwm1_default: pwm1_default {
1061 function = "PWM1";
1062 groups = "PWM1";
1063 };
1064
1065 pinctrl_pwm2_default: pwm2_default {
1066 function = "PWM2";
1067 groups = "PWM2";
1068 };
1069
1070 pinctrl_pwm3_default: pwm3_default {
1071 function = "PWM3";
1072 groups = "PWM3";
1073 };
1074
1075 pinctrl_pwm4_default: pwm4_default {
1076 function = "PWM4";
1077 groups = "PWM4";
1078 };
1079
1080 pinctrl_pwm5_default: pwm5_default {
1081 function = "PWM5";
1082 groups = "PWM5";
1083 };
1084
1085 pinctrl_pwm6_default: pwm6_default {
1086 function = "PWM6";
1087 groups = "PWM6";
1088 };
1089
1090 pinctrl_pwm7_default: pwm7_default {
1091 function = "PWM7";
1092 groups = "PWM7";
1093 };
1094
1095 pinctrl_rgmii1_default: rgmii1_default {
1096 function = "RGMII1";
1097 groups = "RGMII1";
1098 };
1099
1100 pinctrl_rgmii2_default: rgmii2_default {
1101 function = "RGMII2";
1102 groups = "RGMII2";
1103 };
1104
1105 pinctrl_rmii1_default: rmii1_default {
1106 function = "RMII1";
1107 groups = "RMII1";
1108 };
1109
1110 pinctrl_rmii2_default: rmii2_default {
1111 function = "RMII2";
1112 groups = "RMII2";
1113 };
1114
1115 pinctrl_rxd1_default: rxd1_default {
1116 function = "RXD1";
1117 groups = "RXD1";
1118 };
1119
1120 pinctrl_rxd2_default: rxd2_default {
1121 function = "RXD2";
1122 groups = "RXD2";
1123 };
1124
1125 pinctrl_rxd3_default: rxd3_default {
1126 function = "RXD3";
1127 groups = "RXD3";
1128 };
1129
1130 pinctrl_rxd4_default: rxd4_default {
1131 function = "RXD4";
1132 groups = "RXD4";
1133 };
1134
1135 pinctrl_salt1_default: salt1_default {
1136 function = "SALT1";
1137 groups = "SALT1";
1138 };
1139
1140 pinctrl_salt10_default: salt10_default {
1141 function = "SALT10";
1142 groups = "SALT10";
1143 };
1144
1145 pinctrl_salt11_default: salt11_default {
1146 function = "SALT11";
1147 groups = "SALT11";
1148 };
1149
1150 pinctrl_salt12_default: salt12_default {
1151 function = "SALT12";
1152 groups = "SALT12";
1153 };
1154
1155 pinctrl_salt13_default: salt13_default {
1156 function = "SALT13";
1157 groups = "SALT13";
1158 };
1159
1160 pinctrl_salt14_default: salt14_default {
1161 function = "SALT14";
1162 groups = "SALT14";
1163 };
1164
1165 pinctrl_salt2_default: salt2_default {
1166 function = "SALT2";
1167 groups = "SALT2";
1168 };
1169
1170 pinctrl_salt3_default: salt3_default {
1171 function = "SALT3";
1172 groups = "SALT3";
1173 };
1174
1175 pinctrl_salt4_default: salt4_default {
1176 function = "SALT4";
1177 groups = "SALT4";
1178 };
1179
1180 pinctrl_salt5_default: salt5_default {
1181 function = "SALT5";
1182 groups = "SALT5";
1183 };
1184
1185 pinctrl_salt6_default: salt6_default {
1186 function = "SALT6";
1187 groups = "SALT6";
1188 };
1189
1190 pinctrl_salt7_default: salt7_default {
1191 function = "SALT7";
1192 groups = "SALT7";
1193 };
1194
1195 pinctrl_salt8_default: salt8_default {
1196 function = "SALT8";
1197 groups = "SALT8";
1198 };
1199
1200 pinctrl_salt9_default: salt9_default {
1201 function = "SALT9";
1202 groups = "SALT9";
1203 };
1204
1205 pinctrl_scl1_default: scl1_default {
1206 function = "SCL1";
1207 groups = "SCL1";
1208 };
1209
1210 pinctrl_scl2_default: scl2_default {
1211 function = "SCL2";
1212 groups = "SCL2";
1213 };
1214
1215 pinctrl_sd1_default: sd1_default {
1216 function = "SD1";
1217 groups = "SD1";
1218 };
1219
1220 pinctrl_sd2_default: sd2_default {
1221 function = "SD2";
1222 groups = "SD2";
1223 };
1224
1225 pinctrl_sda1_default: sda1_default {
1226 function = "SDA1";
1227 groups = "SDA1";
1228 };
1229
1230 pinctrl_sda2_default: sda2_default {
1231 function = "SDA2";
1232 groups = "SDA2";
1233 };
1234
1235 pinctrl_sgps1_default: sgps1_default {
1236 function = "SGPS1";
1237 groups = "SGPS1";
1238 };
1239
1240 pinctrl_sgps2_default: sgps2_default {
1241 function = "SGPS2";
1242 groups = "SGPS2";
1243 };
1244
1245 pinctrl_sioonctrl_default: sioonctrl_default {
1246 function = "SIOONCTRL";
1247 groups = "SIOONCTRL";
1248 };
1249
1250 pinctrl_siopbi_default: siopbi_default {
1251 function = "SIOPBI";
1252 groups = "SIOPBI";
1253 };
1254
1255 pinctrl_siopbo_default: siopbo_default {
1256 function = "SIOPBO";
1257 groups = "SIOPBO";
1258 };
1259
1260 pinctrl_siopwreq_default: siopwreq_default {
1261 function = "SIOPWREQ";
1262 groups = "SIOPWREQ";
1263 };
1264
1265 pinctrl_siopwrgd_default: siopwrgd_default {
1266 function = "SIOPWRGD";
1267 groups = "SIOPWRGD";
1268 };
1269
1270 pinctrl_sios3_default: sios3_default {
1271 function = "SIOS3";
1272 groups = "SIOS3";
1273 };
1274
1275 pinctrl_sios5_default: sios5_default {
1276 function = "SIOS5";
1277 groups = "SIOS5";
1278 };
1279
1280 pinctrl_siosci_default: siosci_default {
1281 function = "SIOSCI";
1282 groups = "SIOSCI";
1283 };
1284
1285 pinctrl_spi1_default: spi1_default {
1286 function = "SPI1";
1287 groups = "SPI1";
1288 };
1289
1290 pinctrl_spi1cs1_default: spi1cs1_default {
1291 function = "SPI1CS1";
1292 groups = "SPI1CS1";
1293 };
1294
1295 pinctrl_spi1debug_default: spi1debug_default {
1296 function = "SPI1DEBUG";
1297 groups = "SPI1DEBUG";
1298 };
1299
1300 pinctrl_spi1passthru_default: spi1passthru_default {
1301 function = "SPI1PASSTHRU";
1302 groups = "SPI1PASSTHRU";
1303 };
1304
1305 pinctrl_spi2ck_default: spi2ck_default {
1306 function = "SPI2CK";
1307 groups = "SPI2CK";
1308 };
1309
1310 pinctrl_spi2cs0_default: spi2cs0_default {
1311 function = "SPI2CS0";
1312 groups = "SPI2CS0";
1313 };
1314
1315 pinctrl_spi2cs1_default: spi2cs1_default {
1316 function = "SPI2CS1";
1317 groups = "SPI2CS1";
1318 };
1319
1320 pinctrl_spi2miso_default: spi2miso_default {
1321 function = "SPI2MISO";
1322 groups = "SPI2MISO";
1323 };
1324
1325 pinctrl_spi2mosi_default: spi2mosi_default {
1326 function = "SPI2MOSI";
1327 groups = "SPI2MOSI";
1328 };
1329
1330 pinctrl_timer3_default: timer3_default {
1331 function = "TIMER3";
1332 groups = "TIMER3";
1333 };
1334
1335 pinctrl_timer4_default: timer4_default {
1336 function = "TIMER4";
1337 groups = "TIMER4";
1338 };
1339
1340 pinctrl_timer5_default: timer5_default {
1341 function = "TIMER5";
1342 groups = "TIMER5";
1343 };
1344
1345 pinctrl_timer6_default: timer6_default {
1346 function = "TIMER6";
1347 groups = "TIMER6";
1348 };
1349
1350 pinctrl_timer7_default: timer7_default {
1351 function = "TIMER7";
1352 groups = "TIMER7";
1353 };
1354
1355 pinctrl_timer8_default: timer8_default {
1356 function = "TIMER8";
1357 groups = "TIMER8";
1358 };
1359
1360 pinctrl_txd1_default: txd1_default {
1361 function = "TXD1";
1362 groups = "TXD1";
1363 };
1364
1365 pinctrl_txd2_default: txd2_default {
1366 function = "TXD2";
1367 groups = "TXD2";
1368 };
1369
1370 pinctrl_txd3_default: txd3_default {
1371 function = "TXD3";
1372 groups = "TXD3";
1373 };
1374
1375 pinctrl_txd4_default: txd4_default {
1376 function = "TXD4";
1377 groups = "TXD4";
1378 };
1379
1380 pinctrl_uart6_default: uart6_default {
1381 function = "UART6";
1382 groups = "UART6";
1383 };
1384
1385 pinctrl_usbcki_default: usbcki_default {
1386 function = "USBCKI";
1387 groups = "USBCKI";
1388 };
1389
1390 pinctrl_usb2ah_default: usb2ah_default {
1391 function = "USB2AH";
1392 groups = "USB2AH";
1393 };
1394
1395 pinctrl_usb11bhid_default: usb11bhid_default {
1396 function = "USB11BHID";
1397 groups = "USB11BHID";
1398 };
1399
1400 pinctrl_usb2bh_default: usb2bh_default {
1401 function = "USB2BH";
1402 groups = "USB2BH";
1403 };
1404
1405 pinctrl_vgabiosrom_default: vgabiosrom_default {
1406 function = "VGABIOSROM";
1407 groups = "VGABIOSROM";
1408 };
1409
1410 pinctrl_vgahs_default: vgahs_default {
1411 function = "VGAHS";
1412 groups = "VGAHS";
1413 };
1414
1415 pinctrl_vgavs_default: vgavs_default {
1416 function = "VGAVS";
1417 groups = "VGAVS";
1418 };
1419
1420 pinctrl_vpi24_default: vpi24_default {
1421 function = "VPI24";
1422 groups = "VPI24";
1423 };
1424
1425 pinctrl_vpo_default: vpo_default {
1426 function = "VPO";
1427 groups = "VPO";
1428 };
1429
1430 pinctrl_wdtrst1_default: wdtrst1_default {
1431 function = "WDTRST1";
1432 groups = "WDTRST1";
1433 };
1434
1435 pinctrl_wdtrst2_default: wdtrst2_default {
1436 function = "WDTRST2";
1437 groups = "WDTRST2";
1438 };
1439};